JPS60762A - Manufacture of hybrid integrated circuit - Google Patents
Manufacture of hybrid integrated circuitInfo
- Publication number
- JPS60762A JPS60762A JP58108660A JP10866083A JPS60762A JP S60762 A JPS60762 A JP S60762A JP 58108660 A JP58108660 A JP 58108660A JP 10866083 A JP10866083 A JP 10866083A JP S60762 A JPS60762 A JP S60762A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- film
- sputtering
- tantalum
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/702—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof
- H01L21/707—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof of thin-film circuits or parts thereof
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は混成集積回路の製造方法、特に信頼性が高く、
且つ、製造方法の簡略化されたタンタル薄膜CR基板の
製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for manufacturing a hybrid integrated circuit, which is particularly reliable and
The present invention also relates to a method of manufacturing a tantalum thin film CR substrate, which is a simplified manufacturing method.
第4図(a)〜(h) [、従来の混成集積回路の製造
方法を示す。まず、第1図(a)に示すように、セラミ
ック基板1上にタンタル薄膜2を約4000〜5000
λの厚さにスパッタリングによシ付着する。さらに同図
(b)に示すように、所定領域のタンタル薄膜2を公知
のフォトエツチング技術によりパターン形成する。次に
、タンタル薄膜2の一部を選択的に陽極化成し、同図(
C)のように、誘電体層3に変換し、さらに、同図(d
)のように、上記全面にスパッタリングによシ窒化タン
タル薄膜4を約800〜1000Aの厚さに付着形成す
る。更に同図(e)に示すように、窒化タンタル薄膜4
の一部所定領域を残す形状にエツチング除去する。しか
る後、誘電体層3を再度陽極化成し、同図(f)のよう
に、誘電体層3aに変換する。更に同図(g)のように
、電極用導体5f:上記構体全面に付着形成し、同図(
h)のように、これを所望形状にパターン形成する。FIGS. 4(a) to 4(h) show a conventional method for manufacturing a hybrid integrated circuit. First, as shown in FIG. 1(a), a tantalum thin film 2 of about 4000 to 5000
Deposit by sputtering to a thickness of λ. Furthermore, as shown in FIG. 2B, a pattern is formed on the tantalum thin film 2 in a predetermined area by a known photoetching technique. Next, a part of the tantalum thin film 2 is selectively anodized, as shown in the figure (
Convert to dielectric layer 3 as shown in C), and then convert to dielectric layer 3 as shown in (d).
), a tantalum nitride thin film 4 is deposited on the entire surface by sputtering to a thickness of about 800 to 1000 Å. Furthermore, as shown in the same figure (e), a tantalum nitride thin film 4
Etching is performed to leave a predetermined area of a portion of the area. Thereafter, the dielectric layer 3 is anodized again to convert it into a dielectric layer 3a as shown in FIG. 3(f). Furthermore, as shown in the same figure (g), an electrode conductor 5f: is deposited and formed on the entire surface of the structure, and as shown in the same figure (g).
This is patterned into a desired shape as in h).
前記従来例においては、陽極化成工程が2工程含まれて
いる。まず、2回目の陽極化成(同図f)の目的は、言
うまでもなく、回路設計に基づいた容量値を形成の誘電
体層を得ることである。また、1回目の陽極化成(同図
C)の目的は、銹電休層3を形成することにより、窒化
タンタル膜4を選択エツチングする際のストップ層の役
目を果たすことである。また、1回目の隣接化成におい
て、直接誘電体層3ali形成すると、次工程の窒化タ
ンタル薄膜スパッタリングによシ誘電体層3aの表面に
熱的影響による欠陥が生じ、最終的にコンデンサショー
ト、耐圧劣化という不良発生につながる。従って、窒化
タンタル形成後再度陽極化成を行なうことで、上記欠陥
の修復をするのである。In the conventional example, two anodization steps are included. First, the purpose of the second anodization (f in the same figure) is, needless to say, to obtain a dielectric layer with a capacitance value based on the circuit design. The purpose of the first anodization (C in the same figure) is to form a galvanic resting layer 3 which serves as a stop layer when selectively etching the tantalum nitride film 4. In addition, if the dielectric layer 3a is directly formed in the first adjacent chemical formation, defects will occur on the surface of the dielectric layer 3a due to thermal effects during the tantalum nitride thin film sputtering process in the next step, which will eventually lead to capacitor short-circuiting and breakdown voltage deterioration. This leads to the occurrence of defects. Therefore, by performing anodization again after forming tantalum nitride, the above defects are repaired.
本発明の目的は、このような煩雑な工程を簡略化し、且
つ、同等以上の精度を有する混成集積回路を容易に製造
できる製造方法ケ提供するものである。An object of the present invention is to provide a manufacturing method that simplifies such complicated steps and can easily manufacture a hybrid integrated circuit having an accuracy equal to or higher than that described above.
つぎに実施例により本発明を説明する。Next, the present invention will be explained with reference to Examples.
第2図(a)ないしくh)は本発明の一実施例の工程順
の断面図である。先ず、第2図(a)に示すように、セ
ラミック基板1上にタンタル薄膜2を約4000〜50
00Aの厚さにスパッタリングにより付着する。つぎに
同図(b)に示すように、所定領域のタンタル薄膜2を
公知のフォトエツチング技術によりパターン形成する。FIGS. 2(a) to 2h) are cross-sectional views showing the steps of an embodiment of the present invention. First, as shown in FIG.
Deposited by sputtering to a thickness of 00A. Next, as shown in FIG. 4(b), the tantalum thin film 2 in a predetermined area is patterned by a known photoetching technique.
次にタンタル薄膜2の一部を選択的に陽極化成し、第2
図(C)のように、誘電体層3aに変換し、さらに、上
記全面に、同図(d)のように、タンタル系皮膜とは異
なる金属皮膜、例えば、ニクロム皮膜6を蒸着またはス
パッタリングにより付着形成する。しかる後、窒化タン
タル薄膜4をスパッタリングにより被着する。つぎに同
図(e)のように、電極用導体5を付着形成する。Next, a part of the tantalum thin film 2 is selectively anodized, and a second
As shown in Figure (C), it is converted into a dielectric layer 3a, and then, as shown in Figure (d), a metal film different from the tantalum film, such as a nichrome film 6, is applied by vapor deposition or sputtering. Forms adhesion. Thereafter, a tantalum nitride thin film 4 is deposited by sputtering. Next, as shown in FIG. 4(e), an electrode conductor 5 is deposited and formed.
更に同図(f) 、 (g−1、(h)の順に、順次所
望の形にパターン形成する。Further, patterns are sequentially formed into desired shapes in the order of (f), (g-1, and (h)) in the figure.
木兄乳fよれば、陽極化成工程が1工程ですみ、また、
良導電体で、かつ、タンゲルとの密着性にすぐれたニク
ロムを誘電体層の表面に付着することにより、窒化タン
タル4のスパッタリングのダメージを緩和するバッファ
となるので、前記に説明したように不良発生はない。According to Kinenyu f, the anodization process is only one step, and
By adhering nichrome, which is a good conductor and has excellent adhesion to tangel, on the surface of the dielectric layer, it acts as a buffer that alleviates the damage caused by sputtering of tantalum nitride 4, so as to prevent defects as explained above. There have been no outbreaks.
第1図(a)ないしくh)は、従来の混成集積回路の製
造方法を説明するためのタンタル薄膜CR,基板の8誹
音
工程順の断面図、第2 発明の一実施例に係るタンタル
薄膜CR基板の製造工程順の断面図である。
1・・・・・・セラミック基板、2・・・・・・ダンタ
ル薄膜、3.3a・・・・・・誘電体層、4・・・・・
・窒化タンタル薄膜、第1図
第2図1(a) to h) are cross-sectional views of a tantalum thin film CR and a substrate in the order of 8 steps for explaining a conventional method for manufacturing a hybrid integrated circuit; FIG. FIG. 3 is a cross-sectional view of the thin film CR substrate in the order of manufacturing steps. 1... Ceramic substrate, 2... Dantal thin film, 3.3a... Dielectric layer, 4...
・Tantalum nitride thin film, Fig. 1 Fig. 2
Claims (1)
ル薄膜の所定領域を選択的に陽極化成する工程と、全面
にタンタル系皮膜を付着する工程と、さらに窒化タンタ
ル薄膜及び電極用導体を付着する工程と、上記構体を順
次所望の形状にパターン形成する工程とを含むことを特
徴とする混成集積回路の製造方法。A step of forming a tantalum thin film on an insulating substrate, a step of selectively anodizing a predetermined region of the tantalum thin film, a step of attaching a tantalum-based film to the entire surface, and further adhering a tantalum nitride thin film and an electrode conductor. 1. A method of manufacturing a hybrid integrated circuit, the method comprising: step of patterning the structure in sequence into a desired shape.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58108660A JPS60762A (en) | 1983-06-17 | 1983-06-17 | Manufacture of hybrid integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58108660A JPS60762A (en) | 1983-06-17 | 1983-06-17 | Manufacture of hybrid integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60762A true JPS60762A (en) | 1985-01-05 |
Family
ID=14490438
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58108660A Pending JPS60762A (en) | 1983-06-17 | 1983-06-17 | Manufacture of hybrid integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60762A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02116721U (en) * | 1989-03-07 | 1990-09-19 | ||
JPH02262392A (en) * | 1989-03-31 | 1990-10-25 | Toshiba Corp | Circuit board |
-
1983
- 1983-06-17 JP JP58108660A patent/JPS60762A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02116721U (en) * | 1989-03-07 | 1990-09-19 | ||
JPH02262392A (en) * | 1989-03-31 | 1990-10-25 | Toshiba Corp | Circuit board |
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