JP4984855B2 - Thin film chip resistor, thin film chip capacitor, and thin film chip inductor manufacturing method - Google Patents

Description

  The present invention relates to a method of manufacturing a thin film chip resistor, a thin film chip capacitor, and a thin film chip inductor used in various electronic devices.

  In recent years, with the miniaturization of electronic devices, in order to increase the mounting density of circuit boards, there is an increasing demand for miniaturization of electronic components to be mounted. For example, the miniaturization of thin film chip resistors including thin film resistor elements has been promoted, and thin film chip resistors with high accuracy (resistance tolerance, resistance temperature characteristics) and excellent current noise characteristics have been developed. The demand is growing.

  FIG. 17 is a cross-sectional view of a conventional thin film chip resistor, and FIG. 18 is a flowchart showing a method for manufacturing the thin film chip resistor.

  As shown in FIG. 17, the conventional thin film chip resistor includes a pair of thin film upper surface electrode layers 2 made of gold formed on both ends of the upper surface of a rectangular 96% alumina insulating substrate 1, and the insulating substrate 1. A pair of thin film back electrode layers 3 made of gold formed at both ends of the back surface and the pair of thin film top electrode layers 2 are formed so as to be electrically connected to the pair of thin film top electrode layers 2 A thin film resistor layer 4 made of a nickel-chromium alloy or the like; a re-upper surface electrode layer 5 made of a pair of conductive resins covering the thin film resistor layer 4 and formed at both ends of the upper surface of the insulating substrate 1; The protective film layer 6 made of an epoxy resin that covers the thin film resistor layer 4 and covers a part of the pair of upper surface electrode layers 5 is electrically connected to the upper surface electrode layer 5 and the thin film back electrode layer 3. So that both ends of the insulating substrate 1 are A pair of thin-film edge electrode layer 7 formed was constituted by the electrode plating layer 8 formed on the exposed electrode portions.

  Next, a conventional method of manufacturing a thin film chip resistor is shown in the flowchart of FIG. 18, FIGS. 19 (a) to 19 (c), 20 (a) to (c), 21 (a) to (c), and FIG. A description will be given based on the manufacturing process diagrams (a) to (d).

  First, as shown in FIG. 19A, a sheet-like insulating substrate 1 having a primary division groove 1a and a secondary division groove 1b and made of 96% alumina is prepared.

  Next, as shown in FIG. 19 (b), the electrode paste made of a metal organic material mainly composed of gold is screen-printed across the primary division grooves 1a on the upper surface and the back surface of the insulating substrate 1 and dried. Thereafter, in order to remove only the organic component of the electrode paste made of the metal organic material and to burn only the metal component onto the insulating substrate 1, it is fired by a belt-type continuous firing furnace, and the thin film top electrode layer 2 and the thin film back electrode layer 3 ( (Not shown) is formed (rear surface / upper surface electrode layer forming step of FIG. 18).

  Next, as shown in FIG. 19C, a thin film resistor layer 4 made of a nickel chromium alloy or the like is formed on the entire upper surface of the insulating substrate 1 by sputtering (resistor deposition step in FIG. 18).

  Next, as shown in FIGS. 20A to 20C, a photolithography process step for forming the thin film resistor layer 4 in a predetermined resistor pattern 4a (photoresist coating / drying, pattern exposure, development, etching, After performing each step of resist stripping, heat treatment is performed in an atmosphere of 300 to 400 ° C. in order to make the resistor pattern 4a a stable film (step of forming a thin film resistor layer in FIG. 18).

  Next, as shown in FIG. 21A, the upper surface electrode layer 5 made of a conductive resin is formed so as to cover the thin film resistor layer 4 on the thin film upper surface electrode layer 2 (the formation of the upper surface electrode layer in FIG. 18). Process).

  Next, as shown in FIG. 21B, in order to correct the resistance value of the resistor pattern 4a to a predetermined value, the resistance value is corrected by laser trimming to obtain a resistor pattern 4b whose resistance value has been corrected. (Resistance value correcting step in FIG. 18).

  Next, as shown in FIG. 21C, a protective film layer 6 made of a thermosetting epoxy resin is formed to protect the resistor pattern 4b whose resistance value has been corrected (the protective film of FIG. 18). Layer forming step).

  Next, as shown in FIG. 22A, a strip-shaped substrate 1c is obtained by dividing the sheet-like insulating substrate 1 along the primary dividing grooves 1a.

  Next, as shown in FIG. 22B, the thin film end face electrode layer 7 is formed on the end face of the strip-shaped substrate 1c by sputtering (end face electrode forming step in FIG. 18).

  Next, as shown in FIG. 22C, the strip-shaped substrate 1c is divided along the secondary dividing grooves 1b to obtain the individual substrate 1d.

  Finally, as shown in FIG. 22D, a conventional thin film chip resistor is manufactured by performing a step of forming the electrode plating layer 8 on the exposed electrode portion (electrode plating layer forming step of FIG. 18). It was.

  Since the conventional thin film chip resistor manufactured as described above uses the thin film resistor layer 4 made of a nickel-chromium alloy or the like, it can achieve high accuracy and low TCR characteristics.

As prior art document information relating to the invention of this application, for example, Patent Document 1 is known.
JP 2003-45703 A

  However, in the conventional thin film chip resistor manufacturing method described above, as shown in FIG. 23, the thin film upper surface electrode layer 2 is formed across the primary dividing groove 1a, and the thin film resistor layer 4 is deposited. Then, when the photoresist 9 is applied to expose the thin film resistor pattern, the photoresist 9 is not uniformly applied to the portion where the step is generated in the primary dividing groove 1a, and the thin film upper surface electrode layer 2 made of gold and Since the material of the thin film resistor layer 4 made of a nickel-chromium alloy or the like is exposed at the step portion of the primary dividing groove 1a, the thin film resistor is formed during wet etching in the resistor pattern forming process in the photolithography process step. The phenomenon that the exposed portion was etched and the over-etching phenomenon of the thin film resistor due to the local battery reaction occurred. This over-etching phenomenon means that when a relatively noble metal and a base metal are electrically joined, a potential difference due to a standard electrode potential difference occurs between the noble metal and the base metal. When it is exposed locally in an etching solution (hereinafter referred to as an etchant) in this state, it becomes energized through the etchant. In addition, by adding the action of electrolysis, it means a phenomenon in which etching proceeds excessively from the side of the portion masked with the resist pattern. Conventionally, even if this overetching phenomenon occurred, it was not a problem because it was possible to design with a resistor pattern with a thick line width that has almost no effect on the resistance value after etching, but in recent years it has not been a problem, but in recent years thin film chip resistors In order to obtain a thin film chip resistor having a large resistance value using a resistance material having an upper limit on the sheet resistance value, the resistor pattern is long and the line width is fine. It is necessary to form a pattern. In this case, when the above-described overetching phenomenon occurs, a desired fine pattern of the thin film resistor cannot be obtained with high accuracy, and the resistance value yield deteriorates. This problem is not only a thin film chip resistor using a thin film resistor layer, but also a thin film chip capacitor using a capacitor element formed by forming a thin film metal layer on a sheet-like insulating substrate having divided grooves. Even in thin-film chip inductors using inductor elements constructed by forming thin-film metal wiring layers, fine patterns must be formed with high precision in order to meet the demands for device miniaturization and higher precision. This is what happens.

  The present invention solves the above-mentioned conventional problems, and a first object is to expose a thin film resistor in the vicinity of a dividing groove and perform an overetching phenomenon due to a local battery reaction during wet etching in a resistor pattern forming process. It is an object of the present invention to provide a method of manufacturing a thin film chip resistor that can reduce defects due to overetching of a resistor pattern and thereby improve the yield of resistance value. is there.

  The second object is to suppress the exposure of the thin film metal layer in the vicinity of the dividing groove and the overetching phenomenon due to the local cell reaction during the wet etching in the process of forming the thin film metal layer sandwiching the thin film dielectric layer. Accordingly, it is an object of the present invention to provide a method of manufacturing a thin film chip capacitor that can reduce defects due to overetching of a thin film metal layer sandwiching a dielectric layer and can improve the yield of capacitance value.

  The third object is to suppress the over-etching phenomenon due to the exposure of the thin-film metal wiring layer in the vicinity of the dividing groove and the local cell reaction during the wet etching in the process of forming the thin-film metal wiring layer constituting the thin-film inductor element. Thus, an object of the present invention is to provide a method of manufacturing a thin film chip inductor that can reduce defects due to over-etching of a thin film metal wiring layer constituting a thin film inductor element and can improve the yield of inductance value. is there.

  In order to achieve the above object, the present invention has the following configuration.

  The invention according to claim 1 of the present invention includes a step of forming a plurality of thin film upper surface electrode layers across the division grooves on the upper surface of a sheet-like insulating substrate having division grooves, and the plurality of thin film upper surface electrode layers; Forming a plurality of thin film resistor layers so as to be electrically connected, and forming the thin film resistor layer includes a resistor film deposition step, a photoresist coating step, a pattern exposure step, and a development step. A split groove resist so as to cover the thin film upper surface electrode layer, the resistor depositing portion, and the photoresist located in the split groove between the developing step and the wet etching step. According to this manufacturing method, a thin film upper surface electrode layer and a resistor are placed between the development process and the wet etching process. Since the resist printing process for dividing the groove is printed so as to cover the photoresist, the thin film upper surface electrode layer of the dividing groove step portion that was not completely covered with the photoresist is used for the dividing groove. A thin film that can be completely covered with resist, which can reduce the loss of the resistor pattern near the dividing groove during wet etching in the process of forming the resistor pattern, thereby greatly improving the resistance yield. This has the effect of obtaining a chip resistor.

  The invention described in claim 2 of the present invention uses a metal more noble than the thin film resistor layer as a material for forming the thin film upper surface electrode layer. Since noble metal is used as a material to be formed, the thin film upper surface electrode layer dissolves before the thin film resistor layer even when the etchant penetrates into the dividing groove in the etching process. In addition, a split groove resist is printed between the development process and the wet etching process so as to cover the thin film upper surface electrode layer, the resistor depositing portion, and the photoresist located in the split groove. Since the groove resist printing process is provided, the thin film upper surface electrode layer of the step portion of the split groove that was not completely covered with the photoresist can be completely covered with the resist for the split groove. As a result, it is possible to reduce the defect of the resistor pattern in the vicinity of the dividing groove during the wet etching in the resistor pattern formation process, thereby obtaining a thin film chip resistor having a greatly improved resistance value yield. It is what has.

  According to a third aspect of the present invention, there is provided a step of forming a plurality of thin film upper surface electrode layers across the division grooves on an upper surface of a sheet-like insulating substrate having division grooves, and the plurality of thin film upper surface electrode layers. At least a step of forming a plurality of thin film metal layers constituting a capacitive element so as to be electrically connected, and a step of forming a thin film dielectric layer between the plurality of thin film metal layers, The forming step includes a thin film metal layer deposition step, a photoresist coating step, a pattern exposure step, a development step, and a wet etching step, and between the development step and the wet etching step, the upper surface of the thin film located on the dividing groove A dividing groove resist printing process for printing a dividing groove resist so as to cover the electrode layer, the thin film metal layer and the photoresist is provided. Since there is a split groove resist printing process to print the split groove resist so as to cover the thin film upper surface electrode layer, thin film metal layer and photoresist located on the split groove between the etching process, the photoresist is completely The thin film upper surface electrode layer of the step portion of the split groove that was not covered by the thin film can be completely covered with the resist for the split groove, so that the thin film in the vicinity of the split groove at the time of wet etching in the thin film metal layer pattern formation process Defects in the metal layer pattern can be reduced, and as a result, a thin film chip capacitor having a significantly improved capacitance value yield can be obtained.

  The invention according to claim 4 of the present invention uses a metal more precious than the thin film metal layer as the material for forming the thin film upper electrode layer. According to this manufacturing method, the thin film upper electrode layer is formed. Since noble metal is used as the material for the thin film, even if the etchant penetrates into the dividing groove in the etching process, the thin film upper surface electrode layer is dissolved before the thin film metal layer. In addition, between the development process and the wet etching process, for the split groove, the resist for the split groove is printed so as to cover the thin film upper surface electrode layer, the thin film metal layer deposited portion, and the photoresist located in the split groove. Since the resist printing process is provided, the thin film upper surface electrode layer of the step portion of the split groove that was not completely covered with the photoresist can be completely covered with the resist for the split groove, As a result, defects in the thin film metal layer pattern in the vicinity of the dividing groove during wet etching in the process of forming the thin film metal layer pattern can be reduced, thereby obtaining a thin film chip capacitor with a significantly improved capacitance value yield. It has an effect.

  According to a fifth aspect of the present invention, there is provided a step of forming a plurality of thin film upper surface electrode layers across the division grooves on an upper surface of a sheet-like insulating substrate having division grooves, and the plurality of thin film upper surface electrode layers; Forming at least one thin-film metal wiring layer constituting the inductor element so as to be electrically connected, and forming the thin-film metal wiring layer includes: a thin-film metal wiring layer deposition process; A resist coating process, a pattern exposure process, a development process, and a wet etching process are provided, and the thin film upper surface electrode layer, the thin film metal wiring layer, and the photoresist located on the dividing groove are covered between the development process and the wet etching process. In this manufacturing method, the dividing groove resist printing process for printing the dividing groove resist is provided between the development process and the wet etching process. Since there is a split groove resist printing process that prints the resist for the split groove so as to cover the thin film upper surface electrode layer, the thin metal wiring layer deposition part, and the photoresist located in the groove, it can be completely covered with the photoresist. The thin film upper surface electrode layer of the step portion of the divided groove that has not been covered can be completely covered with the resist for the divided groove, thereby enabling the thin film metal wiring in the vicinity of the divided groove at the time of wet etching in the process of forming the thin film metal wiring layer pattern. The loss of the layer pattern can be reduced, and this has the effect of obtaining a thin film chip inductor with a significantly improved inductance value yield.

  The invention according to claim 6 of the present invention uses a metal more precious than the thin film metal wiring layer as a material for forming the thin film upper electrode layer. According to this manufacturing method, the thin film upper electrode layer is As the material to be formed, a noble metal is used rather than the thin film metal wiring layer, so even if the etchant penetrates into the dividing groove in the etching process, the thin film upper electrode layer is dissolved before the thin film metal wiring layer. In addition, during the development process and wet etching process, the resist for the groove is formed so as to cover the thin film upper surface electrode layer, the thin film metal wiring layer deposition portion, and the photoresist located in the groove. Since the resist printing process for dividing grooves to be printed is provided, the thin film upper surface electrode layer of the step part of the dividing groove that was not completely covered with the photoresist is completely covered with the resist for dividing grooves. This can reduce the loss of the thin metal wiring layer pattern in the vicinity of the dividing groove during wet etching in the process of forming the thin metal wiring layer pattern, thereby significantly improving the inductance yield. This has the effect of obtaining a chip inductor.

  As described above, the manufacturing method of the thin film chip resistor of the present invention covers the thin film upper surface electrode layer, the resistor depositing portion, and the photoresist located in the dividing groove between the development process and the wet etching process. Since there is a split groove resist printing process for printing the split groove resist, the thin film upper surface electrode layer of the step portion of the split groove that was not completely covered with the photoresist can be completely covered with the resist for the split groove. As a result, it is possible to reduce the defect of the resistor pattern in the vicinity of the dividing groove during the wet etching in the resistor pattern forming process, thereby obtaining a thin film resistance element having a greatly improved resistance value yield. This provides an excellent effect that a small and highly accurate thin film chip resistor can be obtained by using a resistance element.

(Embodiment 1)
Hereinafter, the first and second aspects of the present invention will be described with reference to the drawings.

  1A is a cross-sectional view of the thin film chip resistor according to the first embodiment of the present invention, FIG. 1B is an enlarged cross-sectional view of the main part of the substrate immediately before the wet etching process of the thin film chip resistor, and FIG. It is a flowchart which shows the manufacturing method of the same thin film chip resistor. The thin film chip resistor manufacturing method according to the first embodiment of the present invention is characterized in that, as shown in the flowchart of FIG. 2, in the step of forming the thin film resistor layer, that is, in the photolithography process step, the developing step This is the point that a dividing groove resist printing process is added between the wet etching process and the wet etching process. The cross-sectional structure of the thin film chip resistor according to the first embodiment of the present invention shown in FIG. 1A is the same as that of the conventional thin film chip resistor shown in FIG. Is omitted.

  Next, the manufacturing method of the thin film chip resistor in the first embodiment of the present invention is shown in the flowchart of FIG. 2, FIGS. 3 (a) to (c), FIGS. 4 (a) to (c), and FIGS. A description will be given based on (c) and the manufacturing process diagrams of FIGS.

  First, as shown in FIG. 3A, a sheet-like insulating substrate 1 made of 96% alumina having a primary division groove 1a and a secondary division groove 1b is prepared.

  Next, as shown in FIG. 3B, an electrode paste made of a metal organic material containing gold as a main component, for example, a gold resinate paste, is screen printed on the upper surface and the back surface of the insulating substrate 1 so as to straddle the primary divided grooves 1a. Then, in order to remove only the organic component of the metal organic electrode paste and to burn only the metal component onto the insulating substrate 1, it is fired by a belt-type continuous firing furnace, and the thin film top electrode layer 2 and the thin film back electrode Layer 3 (not shown) is formed (step of forming back and top electrode layers in FIG. 2).

  Next, as shown in FIG. 3C, a thin film resistor layer 4 made of a Ni—Cr alloy or the like is formed on the entire upper surface of the insulating substrate 1 by sputtering (resistor deposition step in FIG. 2). .

  Next, as shown in FIG. 4A, the first half of the photolithography process for forming the thin film resistor layer 4 on the predetermined resistor pattern 4a, that is, the steps of photoresist coating / drying, pattern exposure, and development. I do. Here, a roll coating method, a spin coating method or the like is used for applying the photoresist, and the film thickness is a uniform film thickness of about several μm with little film thickness variation in order to faithfully reproduce the desired resistor pattern 4a. To do.

  Next, as shown in FIG. 4B, the dividing groove resist 10 is printed so as to straddle the primary dividing groove 1a. At this time, as shown in FIG. 23, since the thin film upper surface electrode layer 2 and the thin film resistor layer 4 have been exposed at the step portion of the primary dividing groove 1a, the wet process in the resistor pattern forming process in the photolithography process step is conventionally performed. In the etching, an overetching phenomenon due to a local cell reaction was caused and the resistor pattern was disconnected. However, in the first embodiment of the present invention, as shown in FIG. By printing the dividing groove resist 10 so as to straddle the dividing groove 1a, exposed portions of the thin film upper surface electrode layer 2 and the thin film resistor layer 4 at the stepped portion of the primary dividing groove 1a as shown in FIG. Is completely covered with the resist 10 for the dividing grooves, and therefore, in the wet etching step shown in FIG. 4C, etching is performed according to the resistor pattern formed on the photoresist 9. Becomes DOO, thereby, those capable of reducing the loss of the resistor pattern due to excessive etching. In this wet etching, a strongly acidic aqueous solution that selectively dissolves the material of the thin film resistor layer 4 without dissolving the material of the thin film upper surface electrode layer 2 is used.

  Next, as shown in FIG. 5A, a resist stripping process for stripping both the photoresist 9 and the dividing groove resist 10 is performed, and then, in order to make the resistor pattern 4a a stable film, 300 Heat treatment is performed in an atmosphere at ˜400 ° C. (step of forming the thin film resistor layer in FIG. 2). Note that the photoresist 9 and the dividing groove resist 10 may be used as part of the protective film without providing a resist stripping step.

  Next, as shown in FIG. 5B, the upper surface electrode layer 5 made of a conductive resin is formed so as to cover the thin film resistor layer 4 on the thin film upper surface electrode layer 2 (the formation of the upper surface electrode layer in FIG. 2). Process). The re-upper surface electrode layer 5 is provided in order to improve the contact of the trimming meter reading in the resistance value correcting step described later.

  Next, as shown in FIG. 5C, a resistance value correction process is performed by laser trimming to correct the resistance value of the resistor pattern 4a to a predetermined value, thereby obtaining a resistance pattern 4b whose resistance value has been corrected. (Resistance value correcting step in FIG. 2).

  Next, as shown in FIG. 6A, in order to protect the resistance pattern 4b whose resistance value has been corrected, a protective film layer 6 made of a thermosetting epoxy resin is formed (protective film layer formation in FIG. 2). Process).

  Next, as shown in FIG. 6B, the strip-shaped substrate 1c is obtained by dividing the sheet-like insulating substrate 1 along the primary dividing grooves 1a.

  Next, as shown in FIG. 6C, the thin film end face electrode layer 7 is formed on the end face of the strip-like substrate 1c by sputtering (end face electrode layer forming step in FIG. 2).

  Next, as shown in FIG. 6D, the strip-shaped substrate 1c is divided along the secondary dividing grooves 1b to obtain the individual substrate 1d. Here, since a resistor that has not been sufficiently removed by wet etching remains in the secondary divided groove 1b, a residual resistor such as a laser scribe is used when dividing along the secondary divided groove 1b. Use an effective method to remove In this case, if the removal of the resistor inside the secondary dividing groove 1b is insufficient, plating adheres to portions other than the thin-film end face electrode layer 7 in the electrode plating step described later, resulting in a defective appearance product.

  Finally, as shown in FIG. 6E, in order to ensure reliability during soldering, a step of forming the electrode plating layer 8 on the exposed electrode portion (electrode plating layer forming step of FIG. 2) is performed. Thus, the thin film chip resistor in the first embodiment of the present invention is completed.

  In the manufacturing method of the thin film chip resistor according to the first embodiment of the present invention described above, the thin film upper surface electrode layer 2 and the thin film resistor layer at the step portion of the primary dividing groove 1a that were not completely covered with the photoresist 9 Since the exposed portion 4 is completely covered by the printing of the resist 10 for the dividing groove, the overetching phenomenon due to the local cell reaction in the vicinity of the primary dividing groove 1a during the wet etching in the resistor pattern forming process. As a result, defects due to over-etching of the resistor pattern can be reduced, and the resistance yield can be greatly improved. Further, this effect is obtained by using a noble metal organic paste such as gold resinate as a material for forming the thin film upper surface electrode layer 2 and using a base metal as a material for forming the thin film resistor layer 4 as compared with the thin film upper surface electrode layer 2. Therefore, in the prior art, overdissolution of the thin film resistor layer 4 which is a relatively base metal is promoted by the local battery reaction, and thus, the first embodiment of the present invention is adopted. The effect of the above-mentioned by will appear more notably.

  In the first embodiment of the present invention, when the thin film resistor layer 4 is deposited, it is deposited on the entire top surface of the insulating substrate 1 as shown in FIG. The thin film resistor layer 4 may be deposited on all the upper surface of the insulating substrate 1 except for the primary dividing groove 1a and the vicinity thereof. In this case, since the thin film resistor layer 4 does not exist in the primary dividing groove 1a from the beginning, even when the dividing groove resist 10 is printed, even when the adjacent groove is short-circuited with the dividing groove resist, the elements are connected to each other. The thin film resistor layer 4 does not exist on the upper surface of the insulating substrate 1 near the primary dividing groove 1a, and the thin film upper surface electrode layer 2 is exposed on the upper surface of the insulating substrate 1. Due to the presence of the portion, the contact between the upper electrode layer 5 and the thin film upper electrode layer 2 is achieved, and the electrical connection is stabilized.

  Alternatively, the thin film resistor layer 4 may be deposited on all the upper surface of the insulating substrate 1 except for the secondary dividing groove 1b and its vicinity by using a mask sputtering method. The step of removing the thin film resistor layer 4 inside the secondary dividing groove 1b that cannot be sufficiently removed by laser scribing or the like can be omitted, and an appearance defect in which plating adheres to portions other than the thin film end electrode layer 7 occurs. The ratio can be reduced.

(Embodiment 2)
Next, the second and third aspects of the present invention will be described with reference to the drawings.

  FIG. 7 is a cross-sectional view of the thin film chip capacitor according to Embodiment 2 of the present invention, FIG. 8 is an enlarged cross-sectional view of the main part after the wet etching process of the first thin film metal layer of the thin film chip capacitor, and FIG. FIG. 10 is an enlarged cross-sectional view of the main part after the wet etching process of the thin film dielectric layer of the capacitor, FIG. 10 is an enlarged cross-sectional view of the main part after the wet etching process of the second thin film metal layer of the thin film chip capacitor, and FIG. It is a flowchart which shows the manufacturing method of a capacitor | condenser.

  The thin film chip capacitor manufacturing method according to the second embodiment of the present invention is characterized in that in the step of forming a thin film metal layer, that is, in the photolithography process step of the thin film metal layer, as shown in the flowchart of FIG. This is that a dividing groove resist printing step is added between the development step and the wet etching step.

  Next, a cross-sectional structure of the thin film chip capacitor according to the second embodiment of the present invention will be described with reference to FIG. Reference numeral 21 denotes an insulating substrate made of an alumina substrate having an alumina content of 96% or more. Reference numeral 22 denotes a pair of thin film upper surface electrode layers formed at both ends of the upper surface of the insulating substrate 21. Reference numeral 23 denotes a pair of thin film back electrode layers formed at both ends of the back surface of the insulating substrate 21. Reference numeral 24 denotes a first thin film metal layer formed on the insulating substrate 21 so as to cover the pair of thin film upper surface electrode layers 22. Reference numeral 25 denotes a thin film dielectric layer formed so as to cover at least a part of the first thin film metal layer 24. Reference numeral 26 denotes a second thin film metal layer formed so as to face at least a part of the first thin film metal layer 24 with the thin film dielectric layer 25 interposed therebetween. A thin film metal layer 24 and a thin film dielectric layer 25 constitute a capacitive element. A protective film layer 27 is formed so as to cover at least a portion where the first thin film metal layer 24 and the second thin film metal layer 26 face each other with the thin film dielectric layer 25 interposed therebetween. 28 is an end face formed on the end face of the insulating substrate 21 so as to be electrically connected to the thin film back electrode layer 23, the thin film top electrode layer 22, the first thin film metal layer 24 and the second thin film metal layer 26. It is an electrode layer. Reference numeral 29 denotes a first plating layer formed so as to cover the thin film back electrode layer 23, the end face electrode layer 28 and the second thin film metal layer 26. Reference numeral 30 denotes a second plating layer formed so as to cover the first plating layer 29.

  Next, the manufacturing method of the thin film chip capacitor in Embodiment 2 of this invention is demonstrated based on sectional drawing shown in FIGS. 8-10, and the flowchart shown in FIG.

  First, as shown in FIG. 8, a sheet-like insulating substrate 21 made of 96% alumina having primary dividing grooves 21a is prepared, and the upper surface and the back surface of the insulating substrate 21 are made of a metal organic material mainly composed of gold. An electrode paste, for example, a gold resinate paste, is screen-printed so as to straddle the primary dividing grooves 21a and dried, and then only the organic component of the metal organic electrode paste is blown off and only the metal component is baked on the insulating substrate 21. Then, the thin film upper surface electrode layer 22 and the thin film back electrode layer 23 are formed by baking in a belt type continuous baking furnace (rear surface / upper surface electrode layer forming step in FIG. 11).

  Next, a first thin film metal layer 24 made of a gold-based metal is formed on the entire upper surface of the insulating substrate 21 so as to cover the thin film upper surface electrode layer 22 by sputtering. At this time, in order to enhance the adhesion of gold, an adhesion layer such as titanium is formed by sputtering or the like as a gold base (first thin film metal layer deposition step in FIG. 11).

  Next, the first half of the photolithography process step for forming the first thin film metal layer 24 in a predetermined pattern, that is, the steps of coating and drying the first photoresist 31, pattern exposure, and development are performed. Here, a roll coating method, a spin coating method or the like is used for applying the first photoresist 31, and the film thickness is a uniform film having a thickness variation of about several μm with little variation in film thickness in order to faithfully reproduce a desired pattern. It is formed with a thickness (first photoresist coating, pattern exposure, and development steps in FIG. 11).

  Next, by printing and drying the first dividing groove resist 32 so as to straddle the primary dividing groove 21a, the thin film upper surface electrode layer 22 and the first thin film metal layer at the step portion of the primary dividing groove 21a. The exposed portion 24 is completely covered with the first dividing groove resist 32. In this state, first wet etching of the first thin film metal layer 24 is performed. Here, when the first thin film metal layer 24 made of a gold-based metal is etched, aqua regia made of hydrochloric acid and nitric acid is used as an etchant at a temperature of 40 ° C. to 80 ° C. (first division of FIG. 11). Each process of resist printing for grooves and first wet etching).

  At this time, since the edge of the primary dividing groove 21a is steep and deep, the first photoresist 31 is the end of the primary dividing groove 21a when the first dividing groove resist 32 is not printed. Since the thin film upper surface electrode layer 22 and the first thin film metal layer 24 are exposed in the vicinity of the step portion of the primary dividing groove 21a, the thin film upper surface electrode layer 22 and the first thin film metal layer 24 are exposed to the first thin film upper electrode layer 22 during the wet etching. Although the thin metal layer 24 has been a factor that is etched around the primary dividing groove 21a, in the second embodiment of the present invention, as shown in FIG. 8, it extends across the primary dividing groove 21a. By printing the first dividing groove resist 32, the exposed portions of the thin film upper surface electrode layer 22 and the first thin film metal layer 24 in the stepped portion of the primary dividing groove 21 a are completely covered with the first dividing groove resist 32. The first c In Tsu DOO etching process, it would be etched according to a pattern formed on the first photoresist 31, thereby, the defect of the pattern of the first thin film metal layer 24 is made difficult to occur.

  Next, a resist stripping step for stripping both the first photoresist 31 and the first dividing groove resist 32 shown in FIG. 8 is performed. At this time, as the resist stripping solution, use a stripping solution capable of stripping both the first photoresist 31 and the first split groove resist 32 made of an alkaline stripping solution such as NaOH aqueous solution or a solvent, After stripping, the substrate is thoroughly rinsed with pure water and then dried (first resist stripping step in FIG. 11).

Next, a thin film dielectric layer 25 is formed on the entire top surface of the insulating substrate 21 by sputtering so as to cover the first thin film metal layer 24. As materials for the thin film dielectric layer 25, strontium titanate (hereinafter referred to as STO), barium strontium titanate (hereinafter referred to as BST), barium titanate (hereinafter referred to as BTO), silicon dioxide (hereinafter referred to as SiO ₂ ). In order to create a desired capacitance, a material having an appropriate dielectric constant ε is selected and a film is formed with an appropriate thickness (a thin film dielectric layer deposition step in FIG. 11).

  Next, the first half of the photolithography process step for forming the thin film dielectric layer 25 in a predetermined pattern, that is, the steps of coating / drying the second photoresist 33, pattern exposure, and development are performed. Here, a roll coating method, a spin coating method, or the like is used for applying the second photoresist 33, and the film thickness is a uniform film having a thickness variation of several μm with little variation in film thickness in order to faithfully reproduce a desired pattern. It is formed with a thickness (second photoresist coating, pattern exposure, and development steps in FIG. 11).

Next, as shown in FIG. 9, second wet etching is performed so as to remove portions other than the second photoresist 33 in the thin film dielectric layer 25 formed on the first thin film metal layer 24. At this time, when a material such as STO, BST, BTO, or SiO ₂ is used as the material of the thin film dielectric layer 25, an aqueous solution of hydrofluoric acid is used for wet etching of the thin film dielectric layer 25 and etching is performed at room temperature. To do. At this time, since it is necessary to remove the thin film dielectric layer 25 formed on the primary dividing groove 21a, the dividing groove resist is not formed during wet etching of the thin film dielectric layer 25 (FIG. 11). Second wet etching step).

  Next, a resist stripping process for stripping the second photoresist 33 shown in FIG. 9 is performed. At this time, as the resist stripping solution, an alkaline stripping solution such as an aqueous NaOH solution or a stripping solution capable of stripping the second photoresist 33 made of a solvent or the like is used. Dry (second resist stripping step in FIG. 11).

  Next, as shown in FIG. 10, a second thin film metal layer 26 made of a copper-based metal is sputtered on the entire upper surface of the insulating substrate 21 so as to cover the first thin film metal layer 24 and the thin film dielectric layer 25. It forms using. At this time, in order to increase the adhesion of the copper-based thin film metal layer, an adhesion layer such as chromium is formed by sputtering or the like as the base of the copper-based metal (second thin film metal layer deposition step in FIG. 11). ).

  Next, the first half of the photolithography process for forming the second thin film metal layer 26 in a predetermined pattern, that is, the steps of coating / drying the third photoresist 34, pattern exposure, and development are performed. Here, a roll coating method, a spin coating method, or the like is used for applying the third photoresist 34, and the film thickness is a uniform film thickness of about several μm with little film thickness variation in order to faithfully reproduce a desired pattern. (Third photoresist coating, pattern exposure, and development steps in FIG. 11).

  Next, the second dividing groove resist 35 is printed and dried so as to straddle the primary dividing groove 21a, and thereby the thin film upper surface electrode layer 22 at the step portion of the primary dividing groove 21a and the first thin film metal. The exposed portions of the layer 24 and the second thin film metal layer 26 are completely covered with the second dividing groove resist 35. In this state, the third wet etching of the second thin film metal layer 26 is performed. Here, when the second thin film metal layer 26 has a two-layer structure of a chromium-based metal and a copper-based metal, an etchant is first etched with an aqueous solution of ammonium persulfate, and then, Etching the chromium-based metal with an aqueous solution of potassium permanganate and sodium metasilicate (third wet etching step in FIG. 11).

  At this time, since the edge of the primary dividing groove 21a is steep and deep, the third photoresist 34 is an end portion of the primary dividing groove 21a when the second dividing groove resist 35 is not formed. Since the thin film upper surface electrode layer 22 and the first thin film metal layer 24 are exposed in the vicinity of the step portion of the primary dividing groove 21a, gold, which is a precious metal, is used in the third wet etching. The potential difference between the thin film upper surface electrode layer 22 and the first thin film metal layer 24 made of a metallic metal and the second thin film metal layer 26 made of a copper based metal which is a relatively base metal compared to gold. However, in the second embodiment of the present invention, as shown in FIG. 10, the second split groove is formed so as to straddle the primary split groove 21a. By printing resist 35, primary dividing grooves The exposed portions of the thin film upper surface electrode layer 22 and the first thin film metal layer 24 and the second thin film metal layer 26 in the step portion 1a are completely covered with the second dividing groove resist 35. In the third wet etching process, etching is performed in accordance with the pattern formed in the third photoresist 34, whereby the pattern defect of the second thin film metal layer 26 is less likely to occur.

  Next, a resist stripping process for stripping both the third photoresist 34 and the second dividing groove resist 35 is performed. At this time, as the resist stripping solution, use a stripping solution capable of stripping both the third photoresist 34 and the second split groove resist 35 made of an alkaline stripping solution such as NaOH aqueous solution or a solvent, After stripping, the substrate is sufficiently rinsed with pure water and then dried (third resist stripping step in FIG. 11).

  Next, in order to protect the formation part of the capacitive element, a protective film layer 27 made of a thermosetting epoxy resin or the like is formed by printing and curing (protective film layer forming step in FIG. 11).

  Thereafter, the primary division step, the end face electrode formation step, the secondary division step, and the electrode plating layer formation step are performed, because these are the same as the manufacturing steps of the thin film chip resistor in the first embodiment of the present invention described above. The description is omitted. And the thin film chip capacitor in Embodiment 2 of this invention is manufactured by implementation of an above-described process.

  In the method of manufacturing the thin film chip capacitor according to the second embodiment of the present invention described above, the primary divided groove 21a that was not completely covered with the first photoresist 31 in the process of forming the first thin film metal layer 24. Since the exposed portions of the thin film upper surface electrode layer 22 and the first thin film metal layer 24 in the step portion are completely covered by the printing of the first dividing groove resist 32, the pattern of the first thin film metal layer 24 The exposure of the first thin film metal layer 24 and the thin film upper surface electrode layer 22 in the vicinity of the primary dividing groove 21a in the first wet etching in the formation process is suppressed, and thereby the first thin film in the vicinity of the primary dividing groove 21a is suppressed. Excessive etching of the thin film metal layer 24 and the thin film upper surface electrode layer 22 can be suppressed, and the second thin film metal layer 26 is completely covered with the third photoresist 34 in the process of forming the second thin film metal layer 26. The exposed portions of the thin film upper surface electrode layer 22, the first thin film metal layer 24, and the second thin film metal layer 26 at the step portion of the primary divided groove 21a are completely covered by printing of the second divided groove resist 35. Therefore, the overetching phenomenon of the second thin-film metal layer 26 due to the local cell reaction in the vicinity of the primary dividing groove 21a during the third wet etching can be suppressed. Since the pattern defects of the thin film metal layer 24 and the second thin film metal layer 26 can be reduced, the yield of the capacitance value can be greatly improved.

  In the second embodiment of the present invention, the first thin film metal layer 24 is formed directly on the insulating substrate 21. However, glass glaze is applied to the area where the capacitor element is formed on the insulating substrate 21. Even if a smoother surface is obtained, the same effect can be obtained.

(Embodiment 3)
Next, using Embodiment 3 of the present invention, the inventions described in claims 5 and 6 of the present invention will be described with reference to the drawings.

  12 is a cross-sectional view of the chip inductor according to the third embodiment of the present invention, FIG. 13 is an enlarged cross-sectional view of the main part after etching the first thin film metal wiring layer of the chip inductor, and FIG. 14 is an interlayer insulating layer of the chip inductor. 15 is an enlarged cross-sectional view of the main part after the wet etching step, FIG. 15 is an enlarged cross-sectional view of the main part after etching the second thin film metal wiring layer of the chip inductor, and FIG. 16 is a flowchart showing a method for manufacturing the chip inductor.

  The feature of the chip inductor manufacturing method according to the third embodiment of the present invention is that, as shown in the flowchart of FIG. 16, the photolithography process step and the second thin film metal in the first thin film metal wiring layer forming step. In the photolithography process step in the wiring layer forming step, a dividing groove resist printing step is added between the development step and the wet etching step.

  Next, a cross-sectional structure of the chip inductor according to the third embodiment of the present invention will be described with reference to FIG. Reference numeral 41 denotes an insulating substrate made of an alumina substrate having an alumina content of 96% or more. Reference numeral 42 denotes a pair of thin film upper surface electrode layers formed at both ends of the upper surface of the insulating substrate 41. Reference numeral 43 denotes a pair of thin film back electrode layers formed at both ends of the back surface of the insulating substrate 41. Reference numeral 44 denotes a first thin film metal wiring layer formed on the insulating substrate 41 so as to cover the pair of thin film upper surface electrode layers 42, and the first thin film metal wiring layer 44 has a spiral shape on the insulating substrate 41. Thus, an inductor element is formed. Reference numeral 45 denotes an interlayer insulating layer made of polyimide or the like formed so as to cover at least a part of the first thin film metal wiring layer 44. 46 opposes at least a part of the first thin-film metal wiring layer 44 via the interlayer insulating layer 45, and a through hole provided in the interlayer insulating layer 45 and a part of the first thin-film metal wiring layer 44. The second thin film metal wiring layer 46 is electrically connected to the pair of thin film upper surface electrode layers 42 by the second thin film metal wiring layer 46. is there. The second thin film metal wiring layer 46 and the first thin film metal wiring layer 44 constitute an inductor element. A protective film layer 47 is formed so as to cover at least a portion where the first thin film metal wiring layer 44 and the second thin film metal wiring layer 46 are opposed to each other through the interlayer insulating layer 45. 48 is formed on the end face of the insulating substrate 41 so as to be electrically connected to the thin film back electrode layer 43, the thin film top electrode layer 42, the first thin film metal wiring layer 44 and the second thin film metal wiring layer 46. This is an end face electrode layer. Reference numeral 49 denotes a first plating layer formed so as to cover the thin film back electrode layer 43, the end face electrode layer 48, and the second thin film metal wiring layer 46. Reference numeral 50 denotes a second plating layer formed so as to cover the first plating layer 49.

  Next, a manufacturing method of the chip inductor according to the third embodiment of the present invention will be described based on the cross-sectional views shown in FIGS. 13 to 15 and the flowchart shown in FIG.

  First, as shown in FIG. 13, a sheet-like insulating substrate 41 made of 96% alumina having primary dividing grooves 41a is prepared, and the upper and rear surfaces of the insulating substrate 41 are made of a metal organic material mainly composed of gold. In order to screen-dry the electrode paste so as to straddle the primary dividing grooves 41a and dry it, and then to remove only the organic component of the metal organic electrode paste and to burn only the metal component on the insulating substrate 41, a belt type continuous The thin film upper surface electrode layer 42 and the thin film back electrode layer 43 are formed by baking at a temperature of 600 ° C. or higher in a baking furnace (back surface / upper surface electrode layer forming step in FIG. 16).

  Next, a first thin film metal wiring layer 44 made of a copper-based metal is formed on the entire upper surface of the insulating substrate 41 so as to cover the thin film upper surface electrode layer 42 by using a film forming method such as sputtering. At this time, in order to increase the adhesion of copper, an adhesion layer of chromium or the like is formed as a copper base by sputtering or the like (first thin film metal wiring layer deposition step in FIG. 16).

  Next, the first half of the photolithography process step for forming the first thin film metal wiring layer 44 in a predetermined pattern (spiral shape for forming the inductor element), that is, coating / drying of the first photoresist 51, pattern exposure. Each step of development is performed. Here, a roll coating method, a spin coating method, or the like is used for applying the first photoresist 51, and the film thickness is a uniform film having a thickness variation of several μm with little variation in film thickness in order to faithfully reproduce a desired pattern. It is formed with a thickness (first photoresist coating, pattern exposure, and development steps in FIG. 16).

  Next, the first dividing groove resist 52 is printed and dried so as to straddle the primary dividing groove 41a, and thereby the thin film upper surface electrode layer 42 and the first thin film metal wiring in the step portion of the primary dividing groove 41a. The exposed portion of the layer 44 is completely covered with the first dividing groove resist 52. In this state, the first wet etching of the first thin film metal wiring layer 44 is performed. Here, when the first thin film metal wiring layer 44 has a two-layer structure of a chromium-based metal and a copper-based metal, the copper-based metal is first etched with an aqueous solution of ammonium persulfate as an etchant, and then The chromium metal is etched with an aqueous solution of potassium permanganate and sodium metasilicate (first wet etching step in FIG. 16).

  At this time, since the edge of the primary dividing groove 41a is steep and deep, the first photoresist 51 is formed at the end of the primary dividing groove 41a when the first dividing groove resist 52 is not formed. The thin film upper surface electrode layer 42 and the first thin film metal wiring layer 44 are exposed in the vicinity of the stepped portion of the primary dividing groove 41a, so that the first thin film metal is formed during the first wet etching. The wiring layer 44 is a factor that is etched around the primary dividing groove 41a. However, in the third embodiment of the present invention, as shown in FIG. 13, the wiring layer 44 extends across the primary dividing groove 41a. By printing one dividing groove resist 52, the exposed portions of the thin film upper surface electrode layer 42 and the first thin film metal wiring layer 44 in the stepped portion of the primary dividing groove 41 a are completely covered with the first dividing groove resist 52. The first c In Tsu DOO etching process, it would be etched according to a pattern formed on the first photoresist 51, thereby, the defect of the pattern of the first thin film metal wiring layer 44 is made difficult to occur.

  Next, a resist stripping process is performed for stripping both the first photoresist 51 and the first dividing groove resist 52 shown in FIG. At this time, as the resist stripping solution, use a stripping solution capable of stripping both the first photoresist 51 and the first split groove resist 52 made of an alkaline stripping solution such as an aqueous NaOH solution or a solvent, After stripping, the substrate is sufficiently rinsed with pure water and then dried (first resist stripping step in FIG. 16).

  Next, the material of the interlayer insulating layer 45 made of photosensitive polyimide or the like is applied to the entire upper surface of the insulating substrate 41 on which the first thin film metal wiring layer 44 is formed by a method such as spin coating and dried (see FIG. 16 interlayer insulation layer coating steps).

  Next, a photolithography process step for forming the interlayer insulating layer 45 in a predetermined pattern, that is, each step of pattern exposure and development is performed. When photosensitive polyimide is used as the material of the interlayer insulating layer 45, desired pattern formation is completed by the above-described pattern exposure and development processes (pattern exposure and development processes in FIG. 16). In addition, as a material of the interlayer insulation layer 45, a non-photosensitive polyimide material can also be used. In that case, after applying and drying a non-photosensitive polyimide material by a method such as spin coating, the insulating layer photoresist 53 is applied and dried by a method such as spin coating or roll coating, and the insulating layer After the photoresist 53 for light is exposed and developed, wet etching is performed to obtain a shape as shown in FIG. 14, and then the interlayer photoresist 45 is peeled off to form the interlayer insulating layer 45.

Next, the interlayer insulating layer 45 made of polyimide is cured at a temperature of 300 ° C. to 500 ° C. (baking (baking) step in FIG. 16). In addition to the polyimide, the interlayer insulating layer 45 may be formed by patterning an inorganic insulating layer such as SiO ₂ formed by a method such as sputtering or CVD using a photolithography method.

  Next, as shown in FIG. 15, a second thin film metal wiring layer 46 made of a copper-based metal is formed on the entire upper surface of the insulating substrate 41 so as to cover the first thin film metal wiring layer 44 and the interlayer insulating layer 45. It is formed using sputtering. At this time, in order to enhance the adhesion of the copper-based metal, an adhesion layer of chromium or the like is formed by sputtering or the like as the base of the copper-based metal (second thin film metal wiring layer deposition step in FIG. 16).

  Next, the first half of the photolithography process step for forming the second thin film metal wiring layer 46 in a predetermined pattern, that is, the steps of coating / drying the second photoresist 54, pattern exposure, and development are performed. Here, the second photoresist 54 is applied by a roll coating method, a spin coating method, or the like, and the film thickness is a uniform film thickness of about several μm with little film thickness variation in order to faithfully reproduce a desired pattern. (Second photoresist coating, pattern exposure, and development steps in FIG. 16).

  Next, as shown in FIG. 15, the second divided groove resist 55 is printed and dried so as to straddle the primary divided grooves 41a, and thereby the thin film upper surface electrode layer 42 at the step portion of the primary divided grooves 41a. The exposed portions of the first thin film metal wiring layer 44 and the second thin film metal wiring layer 46 are completely covered with the second dividing groove resist 55. In this state, the second wet etching of the second thin film metal wiring layer 46 is performed. Here, when the second thin film metal wiring layer 46 is formed of a two-layer structure of a chromium-based metal and a copper-based metal, the copper-based metal is first etched with an aqueous solution of ammonium persulfate as an etchant, and thereafter The chromium metal is etched with an aqueous solution of potassium permanganate and sodium metasilicate (second wet etching step in FIG. 16).

  At this time, since the edge of the primary dividing groove 41a is steep and deep, the second photoresist 54 is formed at the end of the primary dividing groove 41a when the second dividing groove resist 55 is not formed. In the second wet etching, the thin film upper surface electrode layer 42 made of gold and the first thin film metal wiring layer 44 made of copper are exposed in the vicinity of the step portion of the primary dividing groove 41a. The thin film upper surface electrode layer 42 made of a gold-based metal that is a relatively noble metal, the first thin-film metal wiring layer 44 made of a copper-based metal that is a relatively base metal compared to gold, and the first In the third embodiment of the present invention, the second division is performed so as to straddle the primary division groove 41a. However, in the third embodiment of the present invention, a potential difference is generated between the thin film metal wiring layer 46 and the thin film metal wiring layer 46. By printing the groove resist 55, the primary portion In the second wet etching process, the exposed portions of the thin film upper surface electrode layer 42 and the second thin film metal wiring layer 46 in the stepped portion of the groove 41a are completely covered with the second dividing groove resist 55. Etching is performed in accordance with the pattern formed in the second photoresist 54, thereby making it difficult for the pattern defect of the second thin film metal wiring layer 46 to occur.

  Next, a resist stripping process for stripping both the second photoresist 54 and the second dividing groove resist 55 is performed. At this time, as the resist stripping solution, use a stripping solution capable of stripping both the second photoresist 54 and the second dividing groove resist 55 made of an alkaline stripping solution such as NaOH aqueous solution or a solvent, After stripping, the substrate is sufficiently rinsed with pure water and then dried (second resist stripping step in FIG. 16).

  Next, in order to protect the formation portion of the thin film inductor element, a protective film layer 47 made of a thermosetting epoxy resin or the like is formed by printing and curing (protective film layer forming step in FIG. 16).

  Thereafter, the primary division step, the end face electrode formation step, the secondary division step, and the electrode plating layer formation step are performed, because these are the same as the manufacturing steps of the thin film chip resistor in the first embodiment of the present invention described above. The description is omitted. And the thin film chip inductor in Embodiment 3 of this invention is manufactured by implementation of an above-described process.

  In the method of manufacturing the thin film chip inductor according to the third embodiment of the present invention described above, the primary divided groove that was not completely covered with the first photoresist 51 in the process of forming the first thin film metal wiring layer 44. Since the exposed portions of the thin film upper surface electrode layer 42 and the first thin film metal wiring layer 44 in the step portion 41a are completely covered by the printing of the first dividing groove resist 52, the first thin film metal wiring layer The exposure of the first thin film metal wiring layer 44 and the thin film upper surface electrode layer 42 in the vicinity of the primary division groove 41a in the first wet etching in the pattern formation process 44 is suppressed, and thereby the vicinity of the primary division groove 41a. The excessive etching of the first thin film metal wiring layer 44 and the thin film upper surface electrode layer 42 can be suppressed, and in the formation process of the second thin film metal wiring layer 46, the second photoresist is formed. 4, the exposed portions of the thin film upper surface electrode layer 42, the first thin film metal wiring layer 44, and the second thin film metal wiring layer 46 in the stepped portion of the primary divided groove 41 a that were not completely covered with 4 are divided into the second divided grooves. Since the resist 55 is completely covered by printing, the overetching phenomenon of the second thin-film metal wiring layer 46 due to the local cell reaction in the vicinity of the primary dividing groove 41a during the second wet etching is suppressed. As a result, the pattern defects of the first thin film metal wiring layer 44 and the second thin film metal wiring layer 46 can be reduced, and the yield can be greatly improved. .

  In the third embodiment of the present invention, the first thin film metal wiring layer 44 is formed directly on the insulating substrate 41. However, glass glaze is formed in the range where the thin film inductor element on the insulating substrate 41 is formed. The same effect can be obtained even if a smoother surface is obtained.

  The thin film chip resistor, the thin film chip capacitor, and the thin film chip inductor manufacturing method according to the present invention can suppress an over-etching phenomenon caused by a local cell reaction in the vicinity of a dividing groove when a pattern is formed by wet etching. In particular, the present invention is useful when applied to a method of manufacturing a thin film chip resistor, a thin film chip capacitor, and a thin film chip inductor that are particularly small and require high precision.

(A) Cross-sectional view of the thin film chip resistor in the first embodiment of the present invention, (b) An enlarged cross-sectional view of the main part of the substrate immediately before the wet etching process of the thin film chip resistor Flow chart showing the manufacturing method of the thin film chip resistor (A)-(c) Manufacturing process diagram of the thin film chip resistor (A)-(c) Manufacturing process diagram of the thin film chip resistor (A)-(c) Manufacturing process diagram of the thin film chip resistor (A)-(e) Manufacturing process diagram of the thin film chip resistor Sectional drawing of the thin film chip capacitor in Embodiment 2 of this invention The principal part expanded sectional view of the board | substrate after the 1st thin film metal layer etching of the thin film chip capacitor The principal part expanded sectional view of the board after dielectric layer etching of the thin film chip capacitor The principal part expanded sectional view of the board | substrate after the 2nd thin film metal layer etching of the thin film chip capacitor Flow chart showing manufacturing method of the thin film chip capacitor Sectional drawing of the thin film chip inductor in Embodiment 3 of this invention The principal part expanded sectional view of the board | substrate after the 1st thin film metal wiring layer etching of the thin film chip inductor An enlarged cross-sectional view of the main part of the substrate after etching the interlayer insulating layer of the thin film chip inductor The principal part expanded sectional view of the board | substrate after the 2nd thin film metal wiring layer etching of the same thin film chip inductor Flow chart showing manufacturing method of the thin film chip inductor Cross-sectional view of a conventional thin film chip resistor Flow chart showing the manufacturing method of the thin film chip resistor (A)-(c) Manufacturing process diagram of the thin film chip resistor (A)-(c) Manufacturing process diagram of the thin film chip resistor (A)-(c) Manufacturing process diagram of the thin film chip resistor (A)-(d) Manufacturing process diagram of the thin film chip resistor The principal part expanded sectional view of the board | substrate just before the wet etching process of the thin film chip resistor

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Insulation substrate 1a Primary division groove 1b Secondary division groove 2 Thin film upper surface electrode layer 4 Thin film resistor layer 9 Photoresist 10 Divided groove resist 21 Insulation substrate 21a Primary division groove 22 Thin film upper surface electrode layer 24 Layer 25 thin film dielectric layer 26 second thin film metal layer 31 first photoresist 32 first dividing groove resist 33 second photoresist 34 third photoresist 35 second dividing groove resist 41 insulating substrate 41a Primary dividing groove 42 Thin film upper surface electrode layer 44 First thin film metal wiring layer 46 Second thin film metal wiring layer 51 First photoresist 52 First dividing groove resist 53 Insulating layer photoresist 54 Second Photoresist 55 Second split groove resist

Claims (6)

Forming a plurality of thin film upper surface electrode layers across the division grooves on the upper surface of the sheet-like insulating substrate having the division grooves, and a plurality of thin film resistors so as to be electrically connected to the plurality of thin film upper surface electrode layers A step of forming a body layer, and the step of forming the thin film resistor layer includes a resistor film forming step, a photoresist coating step, a pattern exposure step, a development step, and a wet etching step, and the development. A thin film provided with a split groove resist printing step for printing a split groove resist so as to cover the thin film upper surface electrode layer, the resistor film deposition portion, and the photoresist located in the split groove between the step and the wet etching step Manufacturing method of chip resistor. 2. The method of manufacturing a thin film chip resistor according to claim 1, wherein a metal nobler than the thin film resistor layer is used as a material for forming the thin film upper surface electrode layer. A step of forming a plurality of thin film upper surface electrode layers across the division grooves on the upper surface of a sheet-like insulating substrate having division grooves, and a capacitor element configured to be electrically connected to the plurality of thin film upper surface electrode layers A step of forming a plurality of thin film metal layers, and a step of forming a thin film dielectric layer between the plurality of thin film metal layers, wherein the step of forming the thin film metal layer comprises: a thin film metal layer deposition step; A photoresist coating process, a pattern exposure process, a development process, and a wet etching process are provided, and a thin film upper surface electrode layer, a thin film metal layer, and a photoresist located on the dividing groove are covered between the development process and the wet etching process. A method of manufacturing a thin film chip capacitor provided with a dividing groove resist printing step for printing a dividing groove resist on the substrate. 4. The method of manufacturing a thin film chip capacitor according to claim 3, wherein a metal nobler than the thin film metal layer is used as a material for forming the thin film upper surface electrode layer. A step of forming a plurality of thin film upper surface electrode layers across the division grooves on an upper surface of a sheet-like insulating substrate having division grooves, and an inductor element configured to be electrically connected to the plurality of thin film upper surface electrode layers Forming at least one thin-film metal wiring layer, and forming the thin-film metal wiring layer includes a thin-film metal wiring layer deposition process, a photoresist coating process, a pattern exposure process, a development process, and a wet process. A split groove resist that includes an etching process and prints a resist for the split groove so as to cover the thin film upper surface electrode layer, the thin film metal wiring layer, and the photoresist located on the split groove between the developing process and the wet etching process. A method of manufacturing a thin film chip inductor provided with a printing process. 6. The method of manufacturing a thin film chip inductor according to claim 5, wherein a metal nobler than the thin film metal wiring layer is used as a material for forming the thin film upper surface electrode layer.

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