JP2003158097A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To hardly cause breakage and damages at a chip edge during die- bonding a chip by using a pyramid collet or the like for instance. SOLUTION: A semiconductor element (FET) 22 is formed on a surface of a wafer (substrate) 21, and a ground metal layer 31 conducted to a source electrode pad is formed around the element formation area. Also, on a backside of the wafer 21, a back electrode 44 is formed. A surface side edge 37 between a side face and an upper surface of the wafer 21 is sloped so as to be obliquely downward to the outer side, a side face metal layer 40 is formed from the ground metal layer 31 to the front surface side edge 37 and the outer peripheral surface of the wafer 21, and the side face metal layer 40 electrically and thermally connects the source electrode pad and the back electrode 44.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device such as a field effect transistor (FET) for high output and a method for manufacturing the same.

[0002]

2. Description of the Related Art When a field effect transistor (hereinafter referred to as FET) using a compound semiconductor is operated at high output, heat generated during the operation deteriorates the characteristics of the FET. In order to prevent the characteristic deterioration of the FET, F
It is necessary to lower the thermal resistance of ET, and for that purpose, it is necessary to polish the substrate to make it thin, and to form a back electrode on the back surface of the substrate and connect it to the source electrode formed on the front surface of the substrate. Further, such a structure also has an effect of reducing the source inductance of the FET.

As a method of connecting the back electrode of the substrate and the source electrode of the front surface, a through hole (via hole) is provided in the substrate at the source pad portion of the front surface and a metal film formed inside the through hole is used for connection. Is common. However, since it is not easy to inexpensively manufacture the through-hole and the metal film on the substrate, the through-hole is not used, and the element is surrounded by the outer peripheral portion of the chip surface so that the ground metal layer electrically connected to the source electrode is formed. In some cases, a method of connecting the back surface electrode on the back surface of the chip and the ground metal layer with the side surface metal layer formed through the outer side surface of the chip is used.

1A to 1F are views for explaining a process of forming a side surface metal layer on a side surface of a chip for electrically connecting a ground metal layer around a source electrode and a back surface electrode. FIG. 1A shows a FET structure f formed on an active layer 2 on the surface of a wafer (compound semiconductor substrate) 1, and the FET structure f is a source electrode extended from a source electrode pad 3. 4, a drain electrode 6 extending from the drain electrode pad 5, and a gate electrode 8 extending from the gate electrode pad 7. The surface of the wafer 1 is sectioned in a grid pattern by lattice-shaped element division lines 9, and each element formation region 10 surrounded by the element division lines 9 is divided.
Inside, an FET structure f as shown in FIG. 1A is formed. The ground metal layer 1 is formed over the element dividing line 9 on the surface of the wafer 1 over a width wider than the element dividing line 9.
1 is formed, and the ground metal layer 11 is electrically connected to the source electrode pad 3.

As shown in FIG. 1B, a protective film 12 is formed on the entire surface of the wafer 1 excluding the element dividing lines 9 and is supported on the surface of the wafer 1 using a patch 13. The plate 14 is attached. Then, the back surface of the wafer 1 is polished to reduce the wafer thickness to about 20 to 200 μm. Further, on the back surface of the wafer 1, a region other than the element dividing line is covered with the resist film 15,
By etching the wafer 1 through the opening portion of (1), the wafer 1 is opened at the element dividing line 9 to expose the ground metal layer 11 (FIG. 1C). After that, the resist film 15 is removed from the wafer 1.

Then, as shown in FIG. 1 (d), a plating power supply film 1 for electrolytic plating by sputtering or the like.
6 is thinly formed on the entire back surface of the wafer 1, and the resist pattern 1 is formed in the central portion of the element dividing line 9 that has been etched previously.
7 is formed thick. By this process, the plating power supply film 16
Comes into contact with the ground metal layer 11 and is electrically connected to the ground metal layer 11.

Thereafter, as shown in FIG. 1 (e), a metal plating film 18 is formed on the plating power supply film 16 by electrolytic plating using the plating power supply film 16 as a plating electrode. At this time, the metal plating film 18 is formed in a region other than the resist pattern 17 to be slightly thinner than the resist pattern 17. Then, the resist pattern 17 is removed,
The plating power supply film 16 and the ground metal layer 11 in the element dividing line 9 are etched to remove the wafer 1 from the element forming region 10
Divide into each. The width of the resist pattern 17 is so thin that the ground metal layer 11, the plating power supply film 16 and the metal plating film 18 are not separated in this step.

Finally, when the patch 13 is removed, the divided wafer 1 (chip) is separated from the support plate 14 to obtain individual divided chips 19 (FIG. 1 (f)).

Through the above steps, the FET chip 19 is divided, and the back surface electrode and the side surface metal layer composed of the plating power supply film 16 and the metal plating film 18 are formed on the back surface and the side surface of the chip to form the FET source. The electrode and the back surface electrode are electrically connected. According to such a method, it is not necessary to form a through hole in the substrate, and the thermal resistance and the source inductance can be reduced relatively inexpensively.

[0010]

However, as shown in FIG.
In the FET chip 19 having the structure as shown in (f), when a pyramid collet is used during die bonding, the pyramid collet may come into contact with the chip edge portion. If the pyramid collet comes into contact with the chip edge portion, , The metal layer (metal plating film, ground metal layer, etc.) formed on the chip edge part is damaged, or the metal layer is crushed and becomes thin, chipping or cracking occurs in the metal layer, resistance or inductance However, there is a problem in that the electrical characteristics and reliability are deteriorated.

The present invention has been made in view of the above-mentioned problems of the conventional example, and an object of the present invention is to provide a semiconductor device in which breakage or damage is unlikely to occur at a chip edge portion.

[0012]

DISCLOSURE OF THE INVENTION A semiconductor device according to claim 1 of the present invention is a semiconductor device in which a metal layer formed on a surface of a substrate and a side metal layer formed from a side surface to a surface of the substrate are connected to each other. It is characterized in that the surface side edge portion of the side surface of the substrate on which the layer is formed is formed obliquely.

Particularly, it is preferable that the inclined surface of the surface side edge portion is formed obliquely downward from the substrate surface to the side surface of the substrate, as in the second embodiment.

In the semiconductor device according to the present invention, as described above, the edge portion on the surface side of the side surface of the substrate on which the side surface metal layer is formed is formed obliquely. Therefore, for example, a pyramid collet is used to form a die. When bonding, the pyramid collet is less likely to contact the chip edge, and even if it is contacted, the chip edge is less likely to deteriorate and the side metal layer is less likely to be damaged, and the collet is evenly stable on the chip. It is possible to apply force, and it is possible to reduce chipping and cracks that occur during die bonding.

According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the metal layer formed on the front surface of the substrate and the metal layer formed on the back surface of the substrate are
Since the connection is made by the side surface metal layer, the heat dissipation from the semiconductor device can be improved and the source inductance of the high power semiconductor device can be reduced.

An embodiment of claim 4 is at least 2 of the substrates in the semiconductor device according to claim 1, 2 or 3.
Since the side surface metal layer is formed on the side surface above the surface and the surface side edge portion of the side surface is formed obliquely, the surface side edge portion of the side surface metal layer is less likely to be damaged by the collision of the collet or the like. However, even if the side surface metal layer on one surface is damaged, the side surface metal layer on the other surface remains without being damaged. Therefore, the reliability at the time of bonding the semiconductor device is further improved.

According to a fifth aspect of the present invention, in the semiconductor device according to the second aspect, the inclination angle of the front side edge portion is
The angle is 30 ° or more and 45 ° or less with respect to the surface of the substrate.
The chipping occurrence rate at which the inclination angle of the surface side edge portion of the substrate is set to such an angle could be made extremely small.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a dividing groove is formed in a substrate having a plurality of elements formed therein, and finally each element is divided by the dividing groove. In the manufacturing method, by forming the dividing groove on the substrate with a dicing blade having a tapered portion,
It is characterized in that the edge portion of the dividing groove is formed obliquely.

According to the method of claim 6, the semiconductor device according to claim 1 of the present invention can be manufactured, and the front surface side edge portion of the side surface of the substrate can be easily formed obliquely. Moreover, the inclination angle of the front surface side edge portion can be arbitrarily changed only by changing the blade angle of the blade.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a dividing groove is formed in a substrate having a plurality of elements formed therein, and finally each element is divided by the dividing groove. In the manufacturing method, after forming a groove having a taper in the substrate by isotropic wet etching, a groove is further formed in the groove by anisotropic wet etching to form a dividing groove having an oblique edge portion. It is characterized by that.

According to the method of claim 7, the semiconductor device according to claim 1 of the present invention can be manufactured, and the surface side edge portion of the side surface of the substrate can be formed obliquely. Moreover, by changing the etching solution and performing the isotropic wet etching and the anisotropic wet etching, the surface side edge portion of the substrate side surface can be easily formed obliquely only by the wet etching step. Note that it is desirable to use the same resist mask in the isotropic wet etching process and the anisotropic wet etching process.

According to the eighth aspect of the present invention, there is provided a semiconductor device manufacturing method, wherein a dividing groove is formed in a substrate having a plurality of elements formed therein, and finally the dividing groove is used to divide each element. In the manufacturing method, after a groove having a taper is formed in the substrate by isotropic wet etching, a groove is further formed in the groove by dry etching to form a dividing groove having an oblique edge portion. I am trying.

According to the method of claim 8, the semiconductor device according to claim 1 of the present invention can be manufactured, and the surface side edge portion of the substrate side surface can be formed obliquely. Note that it is desirable to use the same resist mask in the isotropic wet etching process and the dry etching process.

According to a ninth aspect of the present invention, in the method of manufacturing a semiconductor device according to the sixth, seventh or eighth aspect, the dividing groove has a depth that does not reach the rear surface of the substrate from the front surface of the substrate, and finally. It is characterized in that it is deeper than the thickness of the chip obtained in 1. According to this embodiment, since the chips are maintained in the connected state without being separated by the dividing groove, the post-process can be easily performed.

According to a tenth aspect of the present invention, after the side surface metal layer is formed from the inner surface of the dividing groove to the front surface of the substrate in the method of manufacturing a semiconductor device according to the ninth aspect, the dividing groove is exposed on the rear surface of the substrate. The chip division can be performed by polishing the back surface of the substrate.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) FIG.
3D, 3E to 3I, and 4J to 4N are views for explaining the manufacturing process of the semiconductor device according to the embodiment of the present invention. FIG. 2A shows an FET (field effect transistor) or MMI formed on a wafer (semiconductor substrate, particularly a compound semiconductor substrate) 21 having an active layer formed on the surface.
A semiconductor element 22 such as C (monolithic microwave integrated circuit) is shown. In the case of a FET, the semiconductor element 22 includes a source electrode 24 extending from the source electrode pad 23, a drain electrode 26 extending from the drain electrode pad 25, and a gate extending from the gate electrode pad 27. It is composed of electrodes 28. Wafer 2
The surface of No. 1 is divided in a grid pattern by grid-like element dividing lines 29, and each element forming region 30 surrounded by the element dividing lines 29 has a semiconductor element 22 as shown in FIG. Are formed. A ground metal layer 31 is formed over the element division line 29 on the surface of the wafer 21 over a width wider than the element division line 29, and the ground metal layer 31 is electrically connected to the source electrode pad 23. A protective film 32 made of a resist or the like is formed on the surface of the wafer 21 so as to cover the semiconductor element 22.

Next, as shown in FIG. 2B, after the back surface of the wafer 21 is attached onto the dividing tape 33, the element dividing line 29 of the wafer 21 is formed by using a dicing device.
The dicing blade 34 is run along the
As shown in (c), a dicing line (division groove) 35 is cut on the surface of the wafer 21 to separate the element formation regions 30. Dicing blade 34 used at this time
Has a uniform blade thickness, and the cut dicing line 35 also has a rectangular cross section. The cutting depth of the dicing line 35 by the dicing blade 34 is half cut with respect to the thickness of the wafer 21 so that it does not reach the back surface of the wafer 21 and is deeper than the desired thickness of the semiconductor chip.

Next, as shown in FIG. 2D, the opening portion of the dicing line 35 is cut by using a dicing blade 36 having a tapered cutting edge to taper the opening portion of the dicing line 35. The cross-sectional shape of the dicing blade 36 used at this time has a taper shape in which the thickness of the outermost peripheral portion is the smallest and the thickness gradually increases toward the center. Dicing blade 3
The tip angle φ of 6 is about 90 ° to 120 °. As a result, as shown in FIG. 3E, a dicing line 35 having a tapered opening is formed on the surface of the wafer 21, and the element forming regions 30 are separated from each other by the dicing line 35. By doing so, the front side edge portion 37 of each semiconductor chip is tapered by the taper of the opening portion of the dicing line 35. Figure 3
The taper angle θ (=
180 ° -inclination angle) is effectively 135 ° to 150 °.

Then, the plating power supply film 38 is formed on the entire surface of the wafer 21 on which the half-cut dicing line 35 is formed.
Are formed (FIG. 3 (g)). The plating power supply film 38 is T
It may be formed of a single material such as i, Au, W, WSi, and Ni, or may have a laminated structure of two or more kinds of these materials, for example, upper layer Au / lower layer Ti. Further, the plating power supply film 38 is 0.05 to 0.3.
A film thickness of about μm is desirable.

After a resist film is applied and formed on the plating power supply film 38, the resist film is exposed and developed to form a resist pattern 39 for selective plating (FIG. 3). (H)). As a material for the resist pattern 39, a usual photoresist or film resist can be used. A contact exposure device or a stepper may be used as the exposure device.

Thereafter, the side surface metal layer 40 is grown by electrolytic plating using the plating power supply film 38 as a plating electrode.
The side surface metal layer 40 is a region excluding the resist pattern 39,
That is, the outer peripheral portion of the element forming region 30 and the surface side edge portion 3
7 and the inner surface of the dicing line 35 (see FIG. 3).
(I)). Au or Cu can be used as the plating metal for forming the side surface metal layer 40, and the plating film thickness is preferably about 3 to 30 μm. Further, it is desirable that the film thickness of the resist pattern 39 is about 30% thicker than the thickness of the plating to be the side surface metal layer 40.

After plating, the resist pattern 39
Is removed by organic cleaning, oxygen plasma, or a combination thereof, the plating power supply film 38 exposed from the side surface metal layer 40 is removed by etching, and the protective film 32 is removed by etching (FIG. 4 (j)). Then, the wafer 21
The separating tape 33 is peeled from the back surface of the wafer, and the reinforcing resin 4 for polishing the back surface is formed on the front surface of the wafer 21 using the adhesive resin 41.
Paste 2 (FIG. 4 (k)).

Thereafter, the back surface of the wafer 21 is polished until it reaches the half-cut dicing line 35,
The dicing line 35 is exposed on the back surface of the wafer 21 and the chips 43 are divided into elements (FIG. 4 (l)).
Here, as shown in FIG. 4 (m), a back surface electrode 44 may be formed on the back surface of each chip 43 held by the reinforcing plate 42 by plating or metal deposition.

Finally, from the reinforcing plate 42 to the individual chips 43
When peeled off, F having the structure as shown in FIG.
A chip 43 such as ET is obtained. In the thus obtained chip 43, the semiconductor element (F
ET) 22 is formed, and the ground metal layer 3 electrically connected to the source electrode pad 23 is formed around the element formation region.
1 is formed. A back electrode 44 is formed on the back surface of the wafer 21. The front surface side edge portion 37 between the side surface and the upper surface of the wafer 21 is inclined so as to be obliquely downward toward the outside, and the side surface extends from the ground metal layer 31 to the front surface side edge portion 37 and the outer peripheral surface of the wafer 21. The metal layer 40 is formed, and the side surface metal layer 40 electrically and thermally connects the source electrode pad 23 and the back surface electrode 44.

In this chip, the side surface metal layer 40 electrically connected to the source electrode pad 23 and the ground metal layer 31.
Since the taper is formed on the front surface side edge portion 37 of the pyramid collet, when the chip 43 is mounted by die bonding or the like using the pyramid collet, the pyramid collet is less likely to collide with the front surface side edge portion 37 of the chip. The side surface metal layer 40 is chipped or peeled off due to a collision with
Alternatively, it is possible to reduce the risk that the chip 43 will be chipped.

FIG. 5 shows the occurrence of chipping in each chip when the taper angle θ (see FIG. 3 (f)) of the surface side edge portion 37 is changed from 90 ° to about 160 ° and die bonding is performed with a pyramid collet. The result of obtaining the rate is shown. As can be seen from FIG. 4, the taper angle θ is 1 as compared with the case where the cross section of the surface side edge portion 37 is a right angle.
When the angle is 35 ° to 150 °, the chipping occurrence rate can be significantly reduced.

In the above embodiment, the dicing line 35 having a rectangular groove in cross section is formed in advance, and then the edge of the dicing line 35 is tapered by using the dicing blade 36, but the outermost peripheral portion is sharp. 6A and FIG. 6B having a tapered cross-section with the thickness gradually increasing toward the center of the blade to form a dicing line 35 by cutting, and the thickness of the outermost peripheral portion is compared. 7 has a tapered cross-section in which the thickness gradually increases toward the center of the blade.
It is also possible to form the dicing line 35 by cutting with the dicing blade 36 as shown in (a) and (b), or to form the tapered surface side edge portion 37 by one dicing.

(Second Embodiment) FIGS. 8A to 8E are views for explaining a manufacturing process of a semiconductor device according to another embodiment of the present invention. In the first embodiment, the tapered dicing blade is used to form the tapered dicing line on the chip surface side. In this embodiment, the dicing line is formed by wet etching as follows. To do.

As the wafer 51, GaAs (00
1) A case of using a substrate will be described as an example. In that case, the cross sections shown in FIGS. 8A to 8E are (0
11) Represents a surface. First, semiconductor elements such as FETs are formed in the element formation region 52 on the surface of the wafer 51 (FIG. 8).
(A)). Then, a photoresist is applied to the surface of the wafer 51, and the photoresist is exposed and developed to cover the entire element forming region 52 and both edges of the element dividing region 53 between the element forming regions 52, and to divide the element dividing region. A resist pattern 54 is formed on the wafer 21 so that the central portion of 53 is exposed (FIG. 8B).

Next, the first stage chip division etching is performed by wet etching. In this first stage chip division etching, an etching solution having an isotropic etching characteristic (such as an etching solution composed of a mixed solution of phosphoric acid + hydrogen peroxide + water) is used to form the resist pattern 54.
The element dividing region 53 is etched from the opening of FIG. 8 and is etched up to the middle of the wafer 51 so as to have a forward mesa shape that widens on the upper surface side of the wafer to form a first dividing groove 55a (FIG. 8C). At this time, a desired taper angle θ (= 135 ° to 150 °) is obtained in the first dividing groove 55a by adjusting the mixing ratio of the etching liquid.

Next, a second stage chip division etching is performed. In this second stage chip dividing etching, the first dividing groove 55a is etched downward with an anisotropic etching solution to make it deep, and the second dividing groove 55a is formed under the first dividing groove 55a.
The dividing groove 55b is formed, and the dividing groove 56 in which the first dividing groove 55a and the second dividing groove 55b are vertically continuous is formed (FIG. 8).
(D)). By this second stage chip division etching, the cross-sectional shape of the second division groove 55b is made wider toward the lower side on at least two sides of the four sides (chip four sides) around the element formation region 52. As a result, on at least two sides of the dividing groove 56, the wall surface of the dividing groove 56 projects in a dogleg shape around the vertical center of the dividing groove 56.

The second stage chip division etching can be realized by the following method, for example. GaAs with an etching solution consisting of 5% bromine and methanol solution
When the (001) surface of the wafer 51 is etched, [01
It is known that a groove in the 1] direction has an inverted mesa. The plane direction of this reverse mesa is the (111) A plane, and the angle formed with the wafer surface is 55 °. Therefore, when the second-stage etching is performed using this solution, the first dividing groove 55a of the forward mesa formed in the first stage does not become a reverse mesa, so that at least FIG. ) In the cross section, a dividing groove 56 is obtained in which the central portions of both side surfaces project.

After that, when the resist pattern 54 is removed, the dividing groove 56 for separating the element forming regions 52 from each other is Ga.
Appear in a grid pattern on the surface of the As wafer 51 (FIG. 8).
(E)). After this, as in the case of the first embodiment (via the ground metal layer or directly).
A step of forming a plating power supply film so as to be electrically connected to the source electrode pad, a step of forming a side surface metal layer by electrolytic plating, and a step of polishing the chip up to, for example, line C in FIG. A chip of a semiconductor element is formed through a dividing process and the like.

(Third Embodiment) Next, an embodiment in which wet etching and dry etching are used together to form a dividing groove will be described with reference to FIGS. In this embodiment, first, the element formation region 52 on the surface of the wafer 51.
A semiconductor element such as an FET or MMIC is formed on the substrate, and a ground metal layer 57 is formed around the element forming region 52 (FIG. 9A). Then, a photoresist is applied to the surface of the wafer 51, and the photoresist is exposed and developed to pattern the photoresist so that the element division regions 53 are exposed. The resist pattern 54 thus formed covers the entire element formation region 52 and the ground metal layer 57 (FIG. 9B).

Then, the wafer 51 is wet-etched from the surface by using the resist pattern 54 as a mask,
The first dividing groove 55a is formed on the surface of the wafer 51. At this time, an isotropic etching solution (for example, a mixed solution of phosphoric acid + hydrogen peroxide + water) is used to form the resist pattern 5
The first dividing groove 55a is formed in a forward mesa shape so that the edge of the opening 4 is under-etched (FIG. 9).
(C)). However, the upper end of the side surface of the under-etched region is etched so as to stop outside the outer periphery of the ground metal layer 57.

After that, dry etching such as ion milling or RIE (reactive ion etching) is performed using the same resist pattern 54 as a mask to form the first dividing groove 5.
Anisotropic etching is performed so as to be substantially vertical in 5a, and a second dividing groove 55b is formed under the first dividing groove 55a. Thus, the first dividing groove 55a and the second dividing groove 5
The etching depth of the dividing groove 56 formed by 5b is a half cut with respect to the thickness of the wafer 51 so that the dividing groove 56 does not reach the back surface of the wafer 51, and
It is made deeper than the desired thickness of the semiconductor chip (FIG. 9D).

Next, when the resist pattern 54 is removed, the dividing groove 56 for separating the element forming regions 52 from each other is Ga.
Appear in a grid pattern on the surface of the As wafer 51. Thereafter, as in the case of the first embodiment, the step of forming the plating power supply film so as to be electrically connected to the source electrode pad (through the ground metal layer or directly), the side surface metal layer by electrolytic plating The semiconductor element chip is formed through the steps of forming the chip, the step of polishing the chip to the line C in FIG. 9D by backside polishing, and dividing the chip into individual chips.

[0048]

According to the semiconductor device according to claims 1 and 2 of the present invention, since the surface side edge portion of the side surface of the substrate on which the side surface metal layer is formed is formed obliquely, for example, a pyramid collet is used. When die bonding is performed, it becomes difficult for the pyramid collet to come into contact with the chip edge, and even if it comes into contact, the chip edge is less likely to deteriorate or the side metal layer is less likely to be damaged, and the collet is evenly applied to the chip. It is possible to apply a stable force and reduce chipping and cracks that occur during die bonding. Therefore, the reliability of the semiconductor device is also improved.

According to the third aspect of the present invention, since the metal layer on the front surface of the substrate and the metal layer on the back surface of the substrate are connected by the side surface metal layer, heat dissipation from the semiconductor device is improved, and The source inductance of the high power semiconductor device can be reduced.

According to the embodiment of claim 4, since the side surface metal layers are formed on at least two side surfaces of the substrate, even if one side surface metal layer is damaged, the other side surface metal layers are damaged. The side surface metal layer remains without being damaged, and reliability during bonding is further improved.

According to the fifth aspect of the present invention, the chipping rate can be made extremely small by setting the inclination angle of the surface side edge portion to 30 ° or more and 45 ° or less with respect to the surface of the substrate. .

According to the method of manufacturing a semiconductor device of the sixth aspect, since the dividing groove is formed in the substrate by the dicing blade having the tapered portion and the edge portion of the dividing groove is formed obliquely, The surface side edge portion of the side surface can be easily formed obliquely. Moreover, the inclination angle of the front surface side edge portion can be arbitrarily changed only by changing the blade angle of the blade.

According to the semiconductor device manufacturing method of the seventh aspect, since the dividing groove having the inclined edge portion is formed by the isotropic wet etching and the anisotropic wet etching, the side surface of the substrate is formed. The front side edge portion can be formed obliquely. Moreover, by changing the etching solution and performing the isotropic wet etching and the anisotropic wet etching, the surface side edge portion of the substrate side surface can be easily formed obliquely only by the wet etching step.

According to the semiconductor device manufacturing method of the eighth aspect, since the dividing groove having the inclined edge portion is formed by the isotropic wet etching and the dry etching, the surface side edge of the substrate side surface is formed. The part can be formed obliquely.

According to the ninth aspect of the invention, since the dividing groove is formed with a depth that does not reach the back surface of the substrate from the front surface of the substrate and is deeper than the thickness of the finally obtained chip.
Since the dicing grooves maintain the chips in a connected state without being disjointed, the post-process can be easily performed.

According to the tenth aspect, after the side surface metal layer is formed from the inner surface of the dividing groove to the substrate surface,
Chip division can be performed by polishing the back surface of the substrate until the dividing groove is exposed on the back surface of the substrate.

[Brief description of drawings]

1A to 1F are diagrams illustrating a step of forming a side surface metal layer on a side surface of a chip for electrically connecting a ground metal layer around a source electrode and a back surface electrode.

FIG. 2A to FIG. 2D are views for explaining a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIGS. 3 (e) to 3 (i) are views for explaining a process performed subsequent to the above-described manufacturing process.

FIG. 4 (j) to (n) are views for explaining a process performed subsequent to the above-described manufacturing process.

FIG. 5 is a diagram showing a result of obtaining a chipping occurrence rate of each chip when a plurality of chips having different taper angles θ on the surface side edge portion are prepared and die bonding is performed with a pyramid collet.

6A and 6B are schematic diagrams illustrating another method of forming a dicing line using a dicing blade.

7A and 7B are schematic views illustrating another method for forming a dicing line using a dicing blade.

8A to 8E are views for explaining a manufacturing process of a semiconductor device according to another embodiment of the present invention.

9A to 9D are views for explaining a manufacturing process of a semiconductor device according to another embodiment of the present invention.

[Explanation of symbols]

21 wafers 22 Semiconductor element 23 Source Electrode Pad 29 element division line 30 element formation area 31 ground metal layer 32 Protective film 34 dicing blade 35 dicing line 36 dicing blade 37 Front side edge 38 Plating power supply film 40 Side metal layer 43 chips 44 Backside electrode

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hajime Onishi             2-10-10 Tenjin, Nagaokakyo, Kyoto Stock             Murata Manufacturing Co., Ltd. (72) Inventor Hidefumi Nakata             2-10-10 Tenjin, Nagaokakyo, Kyoto Stock             Murata Manufacturing Co., Ltd. (72) Inventor Hiroyuki Nakano             2-10-10 Tenjin, Nagaokakyo, Kyoto Stock             Murata Manufacturing Co., Ltd. F-term (reference) 5F043 AA03 BB07 FF04 FF05 GG01                 5F047 CB00

Claims (10)

[Claims] 1. A semiconductor device in which a metal layer formed on a surface of a substrate and a side surface metal layer formed from a side surface to a surface of the substrate are connected to each other, wherein a surface side edge of a side surface of the substrate on which the side surface metal layer is formed. A semiconductor device in which a portion is formed obliquely. 2. The semiconductor device according to claim 1, wherein the inclined surface of the edge portion on the front surface side is formed obliquely downward from the substrate surface to the side surface of the substrate. 3. The side surface metal layer connects the metal layer formed on the front surface of the substrate and the metal layer formed on the back surface of the substrate to each other.
The semiconductor device according to. 4. The side surface metal layer is formed on at least two or more side surfaces of the substrate, and a surface side edge portion of the side surface is formed obliquely. Semiconductor device. 5. The semiconductor device according to claim 2, wherein an inclination angle of the edge portion on the front surface side is 30 ° or more and 45 ° or less with respect to the surface of the substrate. 6. A method of manufacturing a semiconductor device, wherein a dividing groove is formed on a substrate having a plurality of elements formed therein, and finally each element is divided by the dividing groove, wherein a dicing blade having a taper portion is used. A method of manufacturing a semiconductor device, comprising forming a dividing groove in a substrate to form an edge portion of the dividing groove obliquely. 7. A method of manufacturing a semiconductor device, wherein a dividing groove is formed in a substrate having a plurality of elements formed therein, and finally each element is divided by the dividing groove, wherein the substrate is formed by isotropic wet etching. A method for manufacturing a semiconductor device, comprising: forming a groove having a taper in the groove, and further forming a groove in the groove by anisotropic wet etching to form a dividing groove having an oblique edge portion. 8. A method of manufacturing a semiconductor device, wherein a dividing groove is formed on a substrate having a plurality of elements formed therein, and finally each element is divided by the dividing groove, wherein the substrate is formed by isotropic wet etching. A method for manufacturing a semiconductor device, comprising: forming a groove having a taper in the groove, and further forming a groove in the groove by dry etching to form a dividing groove having an oblique edge portion. 9. The dividing groove has a depth that does not reach the back surface of the substrate from the front surface of the substrate and is deeper than the thickness of the finally obtained chip. 7. The method for manufacturing a semiconductor device according to 7 or 8. 10. The chip division is performed by forming a side surface metal layer from the inner surface of the dividing groove to the front surface of the substrate, and then polishing the back surface of the substrate until the dividing groove is exposed on the back surface of the substrate. The method for manufacturing a semiconductor device according to claim 9.