JP2007123756A - Manufacturing method for semiconductor device and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device that enables a wiring structure to be formed by a low-cost process, the wiring structure connecting to the backside, and the semiconductor device. <P>SOLUTION: The manufacturing method of this invention for a semiconductor device includes a half-cut step of doing half-cut dicing on a scribe area from the front surface side, where an element region 101 of a silicon substrate 100 is formed, to form a groove in the silicon substrate 100, a protection film formation step of forming a protection film on the surface where the groove is to be cut, a metal film formation step of forming a metal film on the silicon substrate 100's front surface side, a wiring structure formation step of patterning a metal film to form a wiring structure, and a grinding step of grinding the backside of the substrate 100 to expose the wiring structure at the backside. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and more particularly to a method for manufacturing a semiconductor device and a semiconductor device capable of forming a wiring structure connected to the back surface in a low-cost process.

  With recent downsizing and higher performance of electronic devices, semiconductor devices constituting electronic devices are required to be smaller, thinner, higher performance, and higher reliability. For this reason, semiconductor chip mounting methods have also shifted from pin insertion type packages to surface mount type packages. In particular, recently, bare chip mounting in which a bare semiconductor chip (hereinafter referred to as “bare chip”) at the stage before packaging is directly mounted on a printed circuit board, and a chip size using an interposer instead of a lead frame A mounting method called a package (CSP) or a wafer scale package (WSP) in which the CSP is created in a wafer size is used.

  With reference to FIG. 7 and FIG. 8, the outline of the formation process of the back surface electrode in the manufacturing method of the conventional wafer scale package is demonstrated (for example, refer patent document 1). 7 and 8 are views for explaining an outline of the back surface electrode forming step in the conventional method for manufacturing a wafer scale package, and FIG. 8A is a cross-sectional view taken along the line AA of FIG.

First, a through hole 502 is formed by performing laser beam, wet edging or dry etching on a silicon wafer 501 before forming a semiconductor element (see FIGS. 7 and 8A). Thereafter, the surface of the silicon wafer 501 is sintered at 700 to 800 ° C. in an O ₂ atmosphere to form an insulating oxide film (SiO ₂ ) 503 (see FIG. 8B).

  Next, the through hole is filled with metal 504 using sputtering, CVD, plating, or the like (see FIG. 8C). The front and back surfaces of the metal 504 are grounded and polished to form the electrode 504a (see FIG. 8D).

JP-A-2005-159103

  However, the conventional backside electrode forming method requires additional steps such as formation of a through hole, formation of an insulating film, metal embedding, grounding, and polishing, and there is a problem that the manufacturing process cannot be performed at low cost. Further, this forming method has a problem that a semiconductor element cannot be formed after the back electrode is formed.

  The present invention has been made in view of the above, and an object of the present invention is to provide a method for manufacturing a semiconductor device and a semiconductor device capable of forming a wiring structure connected to the back surface in a low-cost process.

  In order to solve the above-described problems and achieve the object, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device by manufacturing a plurality of semiconductor devices by scribing a substrate on which a plurality of element regions are formed. In the method, a half-cut step of forming a groove in the substrate by performing half-cut dicing on the scribe area of each element region from the surface side of the substrate on which the element region is formed, and cutting the groove A protective film forming step of forming a protective film on the surface; a metal film forming step of forming a metal film on the surface side of the substrate; a wiring structure forming step of patterning the metal film to form a wiring structure; and the substrate And a grounding step for exposing the wiring structure to the back surface.

  According to a preferred aspect of the present invention, the half-cut process is performed after applying a resist to the surface side of the substrate where the element region is formed, and the metal film forming process removes the resist. It is desirable to do this after.

  According to a preferred aspect of the present invention, it is desirable that the wiring structure has a standoff.

  According to a preferred aspect of the present invention, it is desirable that the wiring structure is substantially flush with the back surface.

  According to a preferred aspect of the present invention, the semiconductor device is preferably a chip size package (CSP) or a wafer scale package (WSP).

  According to a preferred aspect of the present invention, it is desirable that the wiring structure includes a back electrode.

  According to a preferred aspect of the present invention, it is desirable that the wiring structure includes a wiring for connecting to another chip when another chip is mounted.

  According to a preferred aspect of the present invention, it is desirable that the wiring structure includes a power line for power supply reinforcement.

  According to a preferred aspect of the present invention, it is desirable that the wiring structure includes a heat dissipation plate.

  In order to solve the above-described problems and achieve the object of the present invention, the present invention provides a surface-mount type semiconductor device, a pad formed on the surface side where an element region of the substrate is formed, and the substrate And a wiring structure electrically connected to the pad and formed on the protective film and extending to the back surface.

  According to a preferred aspect of the present invention, it is desirable that the wiring structure has a standoff.

  According to a preferred aspect of the present invention, it is desirable that the wiring structure is substantially flush with the back surface.

  According to a preferred aspect of the present invention, the semiconductor device is preferably a chip size package (CSP) or a wafer scale package (WSP).

  According to the present invention, in a semiconductor device manufacturing method for manufacturing a plurality of semiconductor devices by scribing a substrate on which a plurality of element regions are formed, each element is formed from the surface side of the substrate on which the element regions are formed. Half-cut dicing is performed on the scribe area of the region to form a groove in the substrate, a protective film forming step of forming a protective film on the cut surface of the groove, and a surface side of the substrate A metal film forming step for forming a metal film, a wiring structure forming step for patterning the metal film to form a wiring structure, and a grounding step for grounding the back surface of the substrate to expose the wiring structure on the back surface. In the normal process of semiconductor manufacturing, the scribe line is half cut to form a groove, and by using this groove, Most processing processes can be performed from the side where the element is formed, and it is possible to form a wiring structure that connects to the back surface with a small number of steps and simple steps. There is an effect that it is possible to provide a method of manufacturing a semiconductor device that can be formed by a low-cost process.

  Hereinafter, the best mode of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiments. In addition, constituent elements in the following embodiments include those that can be easily assumed by those skilled in the art or those that are substantially the same.

  With reference to FIGS. 1-2, the formation process of the wiring structure in the manufacturing method of the semiconductor device which concerns on Example 1 is demonstrated. In Example 1, a case where a back electrode is formed as a wiring structure will be described. 1 and 2 are a plan view and a cross-sectional view for explaining a back surface wiring forming step in the method of manufacturing a semiconductor device according to the first embodiment.

  In the semiconductor manufacturing method according to the first embodiment, when a plurality of semiconductor devices are manufactured by cutting each element region of a substrate on which a plurality of LSI element regions are formed, the scribe line is half-cut, and the substrate A groove is formed in the groove, and the depth of the groove is the length of the back electrode wiring. Hereinafter, a case where a wafer scale package or a chip scale package is manufactured will be described as an example.

  FIG. 1 is a plan view showing a silicon (Si) substrate on which a plurality of LSI elements have been formed. In the figure, reference numeral 100 denotes a silicon substrate on which a plurality of LSI elements have been formed, and 101 denotes an LSI element region. A partial enlarged cross-sectional view of the region indicated by the wavy line a in FIG.

  FIG. 2A illustrates a cross-sectional configuration of the silicon substrate 100 across the scribe line. In the figure, reference numeral 102 denotes an LSI wiring layer in which LSI wiring is formed and protected by an insulating film, 103 denotes a pad, and a wavy line portion b denotes a cut area of a scribe line.

  As shown in FIG. 2B, a resist 104 for preventing oxidation of the pad 103 is applied to the silicon substrate 100 in which element formation has been completed. As shown in FIG. 2-3, half-cut dicing is performed on the cut area b of the scribe line from above the resist 104 to form a groove 105 having a depth L1 in the silicon substrate 100 to expose the silicon. The cut surface 100a is formed. Here, for example, L1 = 100 to 200 μm can be set. The depth L1 of the groove 105 is the length of the back electrode wiring.

As shown in FIG. 2-4, the cut surface 100a is cured in oxygen (O ₂ ) to form an insulating film 106 as a protective film. Thereafter, as shown in FIG. 2-5, the resist 104 is removed and the surface thereof is washed. As shown in FIG. 2-6, a metal film 107 is formed on the entire surface by depositing a metal such as Cu or Al by sputtering or CVD. The thickness of the metal film 107 can be set to, for example, 50 to 100 μm.

  As shown in FIG. 2-7, the metal film 107 is patterned to form the back electrode 107a. Specifically, a resist is applied to the metal film 107, the resist is left in a portion to be left as a wiring, and other metal edging is performed, and then the resist is removed to form the back electrode 107a. Here, in order to prevent peeling of the back electrode 107a, a protective film such as an epoxy resin may be formed on the surface. FIG. 2-8 shows a schematic plan view of FIG. 2-7.

  Next, as shown in FIG. 2-9, the entire back surface of the silicon substrate 100 is cut using a back grinder and a polisher, so that the back electrode 107 a is exposed on the back surface of the silicon substrate 100. Thereafter, as shown in FIG. 2-10, the entire back surface of the silicon substrate 100 is dry or wet etched to form a standoff S by the back electrode 107a. Here, for example, the standoff S can be set to 50 to 100 μm. Through the above process, a semiconductor device in which the back electrode 107a as shown in FIG. 2-11 is formed can be manufactured.

  The semiconductor device shown in FIG. 2-11 includes a pad 103 formed on the side of the silicon substrate 100 where the element region is formed, an insulating film (protective film) 106 formed on the side surface of the silicon substrate 100, and the pad 103. And a back surface electrode (wiring structure) 107a that is formed on the insulating film (protective film) 106 and extends to the back surface. Space can be saved, and the semiconductor device can be reduced in size and thickness.

  For example, when realizing a multi-pin wafer scale package or chip scale package, it is possible to reduce thermal stress by setting the standoff S higher as shown in FIG. 3-1. Become. Moreover, as shown to FIGS. 3-2, it is good also as a structure which does not form the standoff S. FIG.

  As described above, according to the first embodiment, the resist coating process for applying the resist 104 to the surface of the silicon substrate 100 on which the plurality of element regions 101 are formed, and the resist 104 with respect to the scribe area of each element region 101. Half-cut dicing from above to form a groove 105 in the silicon substrate 100, an insulating film forming process to form the protective film 105 on the cut surface 100a of the groove 105, and resist removal to remove the resist 104 A metal film forming step for forming a metal film 107 on the entire surface of the silicon substrate 100, a wiring structure forming step for patterning the metal film 107 to form a back electrode (wiring structure) 107a, and a back surface of the silicon substrate 100. A grounding process for grounding to expose the back electrode (wiring structure) 107a on the back side. Therefore, in a normal process of semiconductor manufacturing, the scribe line is half-cut to form a groove, and the depth L1 of this groove can be the length of the wiring of the back electrode. Can be used to perform almost all processing processes from the side where the element is formed, and the back electrode can be formed with a small number of steps and a simple process. It becomes possible to execute.

  A method of manufacturing a semiconductor device and a semiconductor device according to the second embodiment will be described with reference to FIG. The semiconductor device according to the second embodiment is obtained by applying the wiring structure forming method of the semiconductor device according to the first embodiment to LSI rewiring. In the second embodiment, wiring when another chip is mounted on an LSI will be described as a wiring structure. FIG. 4A is a diagram illustrating a planar configuration of a main part of the semiconductor device according to the second embodiment, and FIG. 4-2 is a schematic cross-sectional view taken along the line AA in FIG.

  4A and 4B, reference numeral 200 denotes a multi-pin LSI chip formed on the silicon substrate 201. FIG. In this LSI chip 200, an LSI wiring is formed on a silicon substrate 201, and an LSI wiring layer 201, a pad 211, and the like protected by an insulating film are formed. When the IC chip 220 is mounted, the wiring (wiring structure) 212 is formed by the same method as in the first embodiment, and the pad 221 and the wiring (wiring structure) 212 of the IC chip 220 are wire-bonded by the bonding wire 230.

  A semiconductor device manufacturing method and a semiconductor device according to Example 3 will be described with reference to FIG. The semiconductor device according to the third embodiment is obtained by applying the wiring structure forming method of the semiconductor device according to the first embodiment to the formation of a power line that reinforces the power supply of the LSI. In Example 3, a power line will be described as a wiring structure. FIG. 5-1 is a diagram illustrating a planar configuration of a main part of the semiconductor device according to the third embodiment, and FIG. 5-2 is a schematic AA cross-sectional view of FIG.

  5A and 5B, reference numeral 300 denotes an LSI chip. In this LSI chip 300, LSI wiring is formed on a silicon substrate 301, and an LSI wiring layer 310, a pad 311, a power contact via 321, a power post 322, and the like protected by an insulating film are formed. . Then, the power line (wiring structure) 320 and the wiring (wiring structure) 330 can be formed by the same method as in the first embodiment.

  A method for manufacturing a semiconductor device and a semiconductor device according to Example 4 will be described with reference to FIG. In Example 6, the wiring structure forming method for a semiconductor device according to Example 1 is applied to the formation of a heat dissipation plate (heat dissipating heat spreader). In Example 4, a heat dissipation plate will be described as a wiring structure. FIG. 6A is a diagram illustrating a plan configuration of a main part of the semiconductor device according to the fourth embodiment, and FIG. 6B is a schematic cross-sectional view taken along line AA in FIG.

  7A and 7B, reference numeral 400 denotes an LSI chip. In this LSI chip 400, LSI wiring is formed on a silicon substrate 401 and protected by an insulating film. 402, a pad 403, a heat dissipation junk connector 404, and the like are formed. Then, the heat spreader for heat dissipation (wiring structure) 410 and the wiring (wiring structure) 405 can be formed by the same method as in the first embodiment.

  The method for manufacturing a semiconductor device and the semiconductor device according to the present invention can be widely applied to a surface mount type semiconductor device, and can be suitably used for, for example, a chip size package (CSP) or a wafer scale package (WSP).

FIG. 6 is a view for explaining a back surface wiring formation step in the method for manufacturing a semiconductor device according to the first embodiment (plan view). FIG. 6 is a diagram for explaining a back surface wiring formation step in the method for manufacturing a semiconductor device according to Example 1 (cross-sectional view). FIG. 6 is a diagram for explaining a back surface wiring formation step in the method for manufacturing a semiconductor device according to Example 1 (cross-sectional view). FIG. 6 is a diagram for explaining a back surface wiring formation step in the method for manufacturing a semiconductor device according to Example 1 (cross-sectional view). FIG. 6 is a diagram for explaining a back surface wiring formation step in the method for manufacturing a semiconductor device according to Example 1 (cross-sectional view). FIG. 6 is a diagram for explaining a back surface wiring formation step in the method for manufacturing a semiconductor device according to Example 1 (cross-sectional view). FIG. 6 is a diagram for explaining a back surface wiring formation step in the method for manufacturing a semiconductor device according to Example 1 (cross-sectional view). FIG. 6 is a diagram for explaining a back surface wiring formation step in the method for manufacturing a semiconductor device according to Example 1 (cross-sectional view). FIG. 6 is a diagram for explaining a back surface wiring formation step in the method for manufacturing a semiconductor device according to Example 1 (cross-sectional view). FIG. 6 is a diagram for explaining a back surface wiring formation step in the method for manufacturing a semiconductor device according to Example 1 (cross-sectional view). FIG. 6 is a diagram for explaining a back surface wiring formation step in the method for manufacturing a semiconductor device according to Example 1 (cross-sectional view). FIG. 6 is a diagram for explaining a back surface wiring formation step in the method for manufacturing a semiconductor device according to Example 1 (cross-sectional view). 11 is a cross-sectional view showing a semiconductor device according to Modification 1. FIG. 10 is a cross-sectional view showing a semiconductor device according to Modification 2. FIG. FIG. 6 is a diagram illustrating a plan configuration of a main part of a semiconductor device according to a second embodiment. It is AA sectional drawing of the outline of FIGS. FIG. 10 is a diagram illustrating a planar configuration of a main part of a semiconductor device according to Example 3. It is AA sectional drawing of the outline of FIGS. FIG. 10 is a diagram illustrating a plan configuration of a main part of a semiconductor device according to a fourth embodiment. It is AA sectional drawing of the outline of FIGS. It is a figure for demonstrating the prior art of the formation process of the back surface wiring in the manufacturing method of a semiconductor device. It is a figure for demonstrating the prior art of the formation process of the back surface wiring in the manufacturing method of a semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Silicon substrate 100a Cut surface 101 Element area 102 LSI wiring layer 103 Pad 104 Resist 105 Groove 106 Insulating film 107 Metal film 107a Back surface electrode (wiring structure)
200 LSI chip 201 Silicon substrate 210 LSI wiring layer 211 Pad 212 Wiring (wiring structure)
220 IC chip 221 pad 230 Bonding wire 300 LSI chip 301 Silicon substrate 310 LSI wiring layer 311 pad 320 Power line 321 Power contact via 322 Power post 400 LSI chip 401 Silicon substrate 402 LSI wiring layer 403 pad 404 Heat dissipation junk connector 405 chip Size package 410 Heat spreader for heat dissipation (wiring structure)

Claims (14)

In a semiconductor device manufacturing method for manufacturing a plurality of semiconductor devices by scribing a substrate on which a plurality of element regions are formed,
A half-cut step of forming a groove in the substrate by performing half-cut dicing on the scribe area of each element region from the surface side where the element region of the substrate is formed,
A protective film forming step of forming a protective film on the cut surface of the groove;
A metal film forming step of forming a metal film on the surface side of the substrate;
A wiring structure forming step of patterning the metal film to form a wiring structure;
A grounding step of grounding the back surface of the substrate to expose the wiring structure on the back surface;
A method for manufacturing a semiconductor device, comprising: The half-cut process is performed after applying a resist on the surface side where the element region of the substrate is formed,
The method of manufacturing a semiconductor device according to claim 1, wherein the metal film forming step is performed after removing the resist.   The method for manufacturing a semiconductor device according to claim 1, wherein the wiring structure has a standoff.   The method of manufacturing a semiconductor device according to claim 1, wherein the wiring structure is substantially flush with the back surface.   5. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a chip size package (CSP) or a wafer scale package (WSP). 6.   The method for manufacturing a semiconductor device according to claim 1, wherein the wiring structure includes a back electrode.   6. The method of manufacturing a semiconductor device according to claim 1, wherein the wiring structure includes a wiring for connecting to another chip when the other chip is mounted. .   The method of manufacturing a semiconductor device according to claim 1, wherein the wiring structure includes a power line for power supply reinforcement.   The method of manufacturing a semiconductor device according to claim 1, wherein the wiring structure includes a heat dissipation plate.   A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1. In surface mount semiconductor devices,
A pad formed on the surface side where the element region of the substrate is formed;
A protective film formed on a side surface of the substrate;
A wiring structure electrically connected to the pad and formed on the protective film and extending to the back surface;
A semiconductor device comprising:   The semiconductor device according to claim 11, wherein a standoff is formed in the wiring structure.   The semiconductor device according to claim 11, wherein the wiring structure is substantially flush with the back surface.   The semiconductor device according to claim 11, wherein the semiconductor device is a chip size package (CSP) or a wafer scale package (WSP).

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