JP2003142631A - Chip-type semiconductor device and manufacturing method therefor - Google Patents
Chip-type semiconductor device and manufacturing method thereforInfo
- Publication number
- JP2003142631A JP2003142631A JP2001334009A JP2001334009A JP2003142631A JP 2003142631 A JP2003142631 A JP 2003142631A JP 2001334009 A JP2001334009 A JP 2001334009A JP 2001334009 A JP2001334009 A JP 2001334009A JP 2003142631 A JP2003142631 A JP 2003142631A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- semiconductor device
- chip
- protective film
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Landscapes
- Bipolar Transistors (AREA)
- Dicing (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、小型面実装タイプ
の半導体装置とその製造方法に係り、特にチップ型半導
体装置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a small surface mounting type semiconductor device and a manufacturing method thereof, and more particularly to a chip type semiconductor device and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】従来、装置の外形寸法及び実装面積を低
減するため、リードフレームを用いない構造の小型面実
装半導体装置が知られている（特開平５−３２６６１８
号公報）。2. Description of the Related Art Conventionally, a small surface mount semiconductor device having a structure not using a lead frame has been known in order to reduce the external dimensions and the mounting area of the device (Japanese Patent Laid-Open No. 5-326618).
Issue).
【０００３】図６に、従来のリードフレームを用いない
小型半導体装置としてダイオードの構造例を示す。FIG. 6 shows an example of the structure of a diode as a conventional small semiconductor device which does not use a lead frame.
【０００４】すなわち図６において、（ａ）は従来のリ
ードフレームを用いない小型面実装型ダイオード２０の
平面図で、電極２１、及び２２が形成されており、各々
と電気的導通する側面電極２３及び２４が形成され、２
５は樹脂等で形成された保護膜である。（ｂ）は（ａ）
のＡ−Ａ線断面図で、セラミック基板２６上にダイオー
ドチップ２７を搭載して、バンプ２８、２９にそれぞれ
接続して形成したものである。（ｃ）は、ダイオードの
底面図で、正面及び背面は保護膜２５とセラミック基板
２６となっており、側面は側面電極２３、２４に被覆さ
れている。That is, in FIG. 6, (a) is a plan view of a small-sized surface-mount type diode 20 which does not use a conventional lead frame, in which electrodes 21 and 22 are formed, and a side electrode 23 which is electrically connected to each of them. And 24 are formed, 2
Reference numeral 5 is a protective film made of resin or the like. (B) is (a)
2 is a cross-sectional view taken along line AA of FIG. 3B, in which the diode chip 27 is mounted on the ceramic substrate 26 and connected to the bumps 28 and 29, respectively. (C) is a bottom view of the diode. The front surface and the back surface are the protective film 25 and the ceramic substrate 26, and the side surfaces are covered with the side electrodes 23 and 24.
【０００５】図７（ａ）〜（ｆ）に，従来のリードフレ
ームを用いない小型半導体装置としてダイオードの製造
方法例を示す。ここで説明する工程は、拡散工程が終了
後バンプの形成がなされてからの工程である。（ａ）で
は、拡散工程が終了しアルミニウム等の電極Ａ１、Ｋ１
上にバンプ２８及び２９が形成されたウェハ３０を、セ
ラミック基板２６に接着する。（ｂ）では、ダイシング
ブレードにてウェハ３０を切断するが、このときセラミ
ック基板２６も多少切断する。またこのとき各チップの
側部をある程度の幅以上の厚みの保護膜によって被覆出
来るように、例えば１００μｍ幅のダイシング用ブレー
ドにより切り込み溝の幅をある程度以上確保しておく。
（ｃ）では、例えばシリコーン等の絶縁性樹脂をウェハ
３０及びバンプ２８、２９を覆うように全体にスピンコ
ートし、硬化させ、保護膜２５を設ける。（ｄ）で、バ
ンプ２８、２９の表面が現れるまで、保護膜２５の研削
もしくは研磨を行う。（ｅ）では、電極２１及び２２を
バンプ２８及び２９と電気的に導通するように保護膜２
５上に設ける。上記電極は、例えば半田ペースト等を印
刷、硬化して生成することが出来る。（ｆ）では、ウェ
ハ３０及びセラミック基板２６を上記（ｂ）で用いたダ
イシングブレードよりも狭いスクライブ溝の幅でダイシ
ング可能なダイシングブレードを用いて、上記（ｂ）で
設けたスクライブ溝の中央部を切断する。即ち、保護膜
２５が両側にコートされた状態にカットする。その後、
側面にも電極を形成すれば、図６に示したダイオード２
０が得られる。但しこの場合は側面電極２３、２４を設
けているが必ずしも設置する必要はない。7 (a) to 7 (f) show an example of a method of manufacturing a diode as a small semiconductor device without using a conventional lead frame. The process described here is a process after the bumps are formed after the diffusion process is completed. In (a), the diffusion process is completed and the electrodes A1, K1 made of aluminum or the like
The wafer 30 having the bumps 28 and 29 formed thereon is adhered to the ceramic substrate 26. In (b), the wafer 30 is cut with a dicing blade, but the ceramic substrate 26 is also cut to some extent at this time. At this time, the width of the cut groove is secured to a certain extent by a dicing blade having a width of, for example, 100 μm so that the side portions of each chip can be covered with a protective film having a thickness equal to or greater than a certain width.
In (c), an insulating resin such as silicone is spin-coated on the entire surface so as to cover the wafer 30 and the bumps 28 and 29, and cured to form the protective film 25. In (d), the protective film 25 is ground or polished until the surfaces of the bumps 28 and 29 appear. In (e), the protective film 2 is formed so that the electrodes 21 and 22 are electrically connected to the bumps 28 and 29.
Provide on top of 5. The electrodes can be produced by printing and curing solder paste, for example. In (f), a dicing blade capable of dicing the wafer 30 and the ceramic substrate 26 with a width of the scribe groove narrower than that of the dicing blade used in (b) above is used, and the central portion of the scribe groove provided in (b) above is used. Disconnect. That is, the protective film 25 is cut so that both sides are coated. afterwards,
If electrodes are formed on the side surfaces, the diode 2 shown in FIG.
0 is obtained. However, in this case, the side electrodes 23 and 24 are provided, but they are not necessarily provided.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら上記従来
の小型面実装型半導体装置では、旧来のリードタイプの
小型面実装型半導体装置と比べると外形寸法と実装面積
ともに削減できているが、その構造上、製造方法に次に
述べる課題を有している。However, in the conventional small surface mounting type semiconductor device described above, both the external dimensions and the mounting area can be reduced as compared with the conventional lead type small surface mounting type semiconductor device. The manufacturing method has the following problems.
【０００７】まず、図７（ｃ）の保護膜２５を形成する
工程において、シリコーン等の絶縁性樹脂をウェハ３０
上全体にスピンコートし硬化させて形成するが、ウェハ
３０上には、すでに形成されているバンプ２８、２９及
び、チップの側面部に保護膜を形成させるためにダイシ
ングにより設けられた切り込み溝等があるため、段差部
分での保護膜のカバー性が悪く、最悪の場合、段差の高
低差がきつい部分にて、保護膜が形成されないといった
箇所が発生する。First, in the step of forming the protective film 25 of FIG. 7C, an insulating resin such as silicone is used for the wafer 30.
It is formed by spin-coating and curing on the entire surface, but the bumps 28, 29 already formed on the wafer 30 and notch grooves provided by dicing to form a protective film on the side surface of the chip. Therefore, the covering property of the protective film in the step portion is poor, and in the worst case, there is a portion in which the protective film is not formed in the portion where the height difference of the step is large.
【０００８】さらに、図７（ｆ）のダイシングによる、
ウェハ状態から個々のチップに切断する工程において、
図７（ｂ）で用いたダイシングブレードより狭いスクラ
イブ溝の幅を例えば、２０μｍ幅のダイシング用ブレー
ドにて切断するため、より高いダイシング精度が要求さ
れる。このためチップ側面部の保護膜２５を均等な厚さ
で、個々のチップを切断することが困難である。Further, according to the dicing of FIG. 7 (f),
In the process of cutting from the wafer state into individual chips,
Since the width of the scribe groove narrower than that of the dicing blade used in FIG. 7B is cut by a dicing blade having a width of 20 μm, for example, higher dicing accuracy is required. For this reason, it is difficult to cut each chip with a uniform thickness of the protective film 25 on the side surface of the chip.
【０００９】また、従来の小型面実装型半導体装置で
は、絶縁基板にセラミックを用いていたため、低コスト
の半導体装置を得ることが困難であった。Further, in the conventional small surface mount type semiconductor device, since the insulating substrate is made of ceramic, it is difficult to obtain a low cost semiconductor device.
【００１０】本発明は上記従来の課題を解決するもの
で、超小型外形と低コスト、寄生インダクタンスの低減
および信頼性に優れたチップ型半導体装置及び１枚の半
導体ウェーハでより多くの半導体装置を生産できる製造
方法を提供することを目的とする。The present invention solves the above-mentioned problems of the prior art by providing a chip-type semiconductor device having an ultra-small outline, low cost, reduced parasitic inductance and excellent reliability, and a larger number of semiconductor devices with one semiconductor wafer. It is an object of the present invention to provide a manufacturing method capable of producing.
【００１１】[0011]
【課題を解決するための手段】この課題を解決するため
に本発明のチップ型半導体装置は、半導体基板と、この
半導体基板の裏面に設けられ直接半導体装置の外部電極
となる複数の電極と、前記電極周辺の半導体基板裏面お
よび前記半導体基板の側面を被覆するＣＶＤ法による薄
膜の絶縁性保護膜とよりなる構成としたものである。In order to solve this problem, a chip type semiconductor device of the present invention comprises a semiconductor substrate, a plurality of electrodes provided directly on the back surface of the semiconductor substrate and serving as external electrodes of the semiconductor device, A thin insulating protective film formed by a CVD method for covering the back surface of the semiconductor substrate around the electrodes and the side surface of the semiconductor substrate.
【００１２】したがって、絶縁性保護膜にシリコーン等
の樹脂系保護膜を用いないため、切り込み溝等の段差部
分での保護膜のカバー性を向上させることができる。さ
らに側面を被覆した構造により外部からの影響を受け難
くしているので、ベアチップでの課題である検査、実装
時の取り扱いにおけるチッピングを防止でき、外部環境
からの影響を受け難くなり信頼性が向上するという作用
を有する。Therefore, since the resin-based protective film such as silicone is not used as the insulating protective film, the cover property of the protective film at the step portion such as the cut groove can be improved. Furthermore, since the structure that covers the side surface makes it less susceptible to external influences, it is possible to prevent chipping, which is a problem with bare chips during inspection and handling during mounting, and is less susceptible to the external environment, improving reliability. Has the effect of
【００１３】また本発明は、半導体ウェーハの片面に複
数の半導体素子を形成する工程と、複数の半導体素子が
形成された半導体ウェーハの裏面（電極面側）をダイシ
ング用ブレードで隣り合う半導体素子間に切り込み溝を
形成する工程と、前記半導体素子表面および切り込み溝
表面にＣＶＤ法による薄膜の絶縁性保護膜を形成する工
程と、前記複数の半導体素子にメタルバンプ等の電極を
形成する工程と、前記半導体ウェーハの表面を前記切り
込み溝まで研削して半導体チップを切り出す工程とより
なるチップ型半導体装置の製造方法としたものである。Further, according to the present invention, a step of forming a plurality of semiconductor elements on one surface of a semiconductor wafer and a step of dicing the back surface (electrode surface side) of the semiconductor wafer having the plurality of semiconductor elements between adjacent semiconductor elements with a dicing blade. A step of forming a notch groove on the surface, a step of forming a thin insulating protective film by a CVD method on the semiconductor element surface and the notch surface, a step of forming electrodes such as metal bumps on the plurality of semiconductor elements, A method of manufacturing a chip-type semiconductor device comprising a step of cutting a semiconductor chip by grinding the surface of the semiconductor wafer to the cut groove.
【００１４】したがって、ダイシングブレードによる切
削工程回数が１回となり工程数の削減がなされたこと
と、より高いダイシング精度を必要としなくなったこと
と、幅の狭い例えば２０μｍ幅のダイシングブレードに
よる切り込み溝形成で切りしろが小さくなることで、１
枚の半導体ウェーハでより多くの半導体装置を生産でき
るといったようなことの作用を有する。Therefore, the number of cutting steps by the dicing blade is reduced to one, the number of steps is reduced, higher dicing accuracy is not required, and the cut groove is formed by a narrow dicing blade having a width of, for example, 20 μm. With the smaller cutting margin, 1
It has an effect such that more semiconductor devices can be produced with one semiconductor wafer.
【００１５】また、半導体ウェーハの表面を前記切り込
み溝まで研削して半導体チップを切り出す工程となるこ
とで、セラミック基板を用いることがなくなり、コスト
と工程数の削減がなされた、チップ型半導体装置の製造
方法としたものである。Further, the step of grinding the surface of the semiconductor wafer to the cut groove to cut out the semiconductor chip eliminates the use of the ceramic substrate, and the cost and the number of steps of the chip type semiconductor device are reduced. This is a manufacturing method.
【００１６】[0016]
【発明の実施の形態】以下、本発明の一実施の形態につ
いて図面を参照しながら説明する。BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings.
【００１７】図１は本発明の実施の形態に係わるチップ
型半導体装置を示し、図１（ａ）はチップ型半導体装置
の透視平面図、（ｂ）は（ａ）のＢ−Ｂ線断面図、
（ｃ）は（ａ）のＣ−Ｃ線断面図である。具体的には２
ヶのコレクタ電極１ａ，１ｂ、ベース電極２、エミッタ
電極３を備えた４端子チップ型トランジスタである。FIG. 1 shows a chip type semiconductor device according to an embodiment of the present invention, FIG. 1A is a perspective plan view of the chip type semiconductor device, and FIG. 1B is a sectional view taken along line BB of FIG. ,
(C) is the CC sectional view taken on the line (a). Specifically 2
This is a four-terminal chip type transistor provided with collector electrodes 1a and 1b, a base electrode 2 and an emitter electrode 3.
【００１８】図示したように、本発明によるチップ型半
導体装置は半導体基板４と絶縁性保護膜５、電極１ａ，
１ｂ，２，３を備えている。As shown in the figure, the chip type semiconductor device according to the present invention includes a semiconductor substrate 4, an insulating protective film 5, electrodes 1a,
1b, 2, 3 are provided.
【００１９】半導体基板４の厚みは例えば２５０μｍで
ある。この半導体基板４の裏面は、絶縁膜６，７および
８、配線金属層９を含めて絶縁性保護膜５で被覆されて
おり、裏面のみの所定箇所に絶縁性保護膜５に窓を開け
半導体基板４のコレクタ，ベース，エミッタにそれぞれ
接続する直径が例えばφ０．１ｍｍの電極１ａ，１ｂ，
２，３が設けられている。The thickness of the semiconductor substrate 4 is 250 μm, for example. The back surface of the semiconductor substrate 4 is covered with an insulating protective film 5 including the insulating films 6, 7 and 8 and the wiring metal layer 9, and a window is opened in the insulating protective film 5 at a predetermined position only on the rear surface of the semiconductor substrate 4. Electrodes 1a, 1b having a diameter of, for example, φ0.1 mm, which are connected to the collector, base, and emitter of the substrate 4, respectively.
2 and 3 are provided.
【００２０】また半導体基板４の裏面側（電極面側）と
側面は、例えば厚み０．３〜２．０μｍの絶縁性保護膜
５で被覆されている。この絶縁性保護膜５はプラズマＣ
ＶＤ法による窒化珪素の薄膜で形成されたものである。The back surface side (electrode surface side) and side surfaces of the semiconductor substrate 4 are covered with an insulating protective film 5 having a thickness of 0.3 to 2.0 μm, for example. This insulating protective film 5 is plasma C
It is formed of a silicon nitride thin film by the VD method.
【００２１】上記構成により、旧来の構成で必要であっ
た絶縁基板および絶縁基板上に配設された配線パターン
を電気的に接続する金属ワイヤーを用いないため、寄生
インダクタンスの低減が達成でき、また超小型のチップ
型半導体装置が実現できる。さらに側面を絶縁被覆した
構造により外部からの影響を受け難くしているので、ベ
アチップでの課題である検査、実装時の取り扱いにおけ
るチッピングを防止できる。With the above structure, since the insulating substrate and the metal wire for electrically connecting the wiring pattern disposed on the insulating substrate, which are required in the conventional structure, are not used, the parasitic inductance can be reduced, and An ultra-small chip type semiconductor device can be realized. Further, since the side surface is made to have an insulating coating structure, it is less susceptible to external influences, so that it is possible to prevent chipping in handling at the time of inspection and mounting, which is a problem with bare chips.
【００２２】次に、本発明のチップ型半導体装置の製造
方法について説明する。Next, a method of manufacturing the chip type semiconductor device of the present invention will be described.
【００２３】図２に示すように、まず半導体ウェーハ１
０の一面に複数の半導体素子１１ならびに絶縁膜（図示
しない）、配線金属層９を形成する。つぎにこの複数の
半導体素子１１ならびに絶縁膜（図示しない）、配線金
属層９が形成された半導体ウェーハ１０の電極面側とな
る裏面を、例えば２０μｍ幅のダイシング用ブレード１
２で所望の厚みまで隣り合う半導体素子間に切り込み溝
１３を形成する。ついで図３に示すように、半導体ウェ
ーハ１０の電極面側と上記した溝１３に絶縁性保護膜５
を被覆する。As shown in FIG. 2, first, the semiconductor wafer 1
A plurality of semiconductor elements 11, an insulating film (not shown), and a wiring metal layer 9 are formed on one surface of 0. Next, the back surface of the semiconductor wafer 10 on which the plurality of semiconductor elements 11 and the insulating film (not shown) and the wiring metal layer 9 are to be the electrode surface side is, for example, a dicing blade 1 having a width of 20 μm.
In step 2, a cut groove 13 is formed between adjacent semiconductor elements to a desired thickness. Then, as shown in FIG. 3, the insulating protective film 5 is formed on the electrode surface side of the semiconductor wafer 10 and on the groove 13 described above.
To cover.
【００２４】この絶縁性保護膜５は、モノシラン（Ｓｉ
Ｈ4），アンモニア（ＮＨ3），窒素（Ｎ2）の混合ガス
を用い、４００℃程度の温度でプラズマＣＶＤ法による
０．３〜２.０μｍの膜厚の窒化珪素被覆層で形成され
ている。This insulating protective film 5 is made of monosilane (Si
H 4 ), ammonia (NH 3 ) and nitrogen (N 2 ) mixed gas is used to form a silicon nitride coating layer having a thickness of 0.3 to 2.0 μm by plasma CVD at a temperature of about 400 ° C. There is.
【００２５】さらに図４に示すように、半導体ウェーハ
１０に形成された複数の半導体素子１１表面の絶縁性保
護膜５に窓を開けメタルバンプ等の電極２，３を接続す
る。Further, as shown in FIG. 4, a window is opened in the insulating protective film 5 on the surface of the plurality of semiconductor elements 11 formed on the semiconductor wafer 10 to connect the electrodes 2 and 3 such as metal bumps.
【００２６】メタルバンプはハンダバンプを印刷または
メッキで形成するか金ワイヤによるボールバンプ法にて
形成するが、他の方法で形成しても良い。The metal bumps are formed by printing or plating solder bumps or by a ball bump method using gold wires, but they may be formed by other methods.
【００２７】その後、図５（ａ）に示すように半導体ウ
ェーハ１０の電極面側とは反対側の表面を矢印のごとく
切り込み溝１３まで研磨あるいは研削して半導体素子を
切り離し、図５（ｂ）に示すように半導体チップを切り
出して個々のチップ型半導体装置を得る。Thereafter, as shown in FIG. 5A, the surface of the semiconductor wafer 10 opposite to the electrode surface side is polished or ground up to the cut groove 13 as shown by an arrow to separate the semiconductor element, and FIG. Semiconductor chips are cut out to obtain individual chip-type semiconductor devices as shown in FIG.
【００２８】したがって、半導体基板側面の絶縁性保護
膜は薄膜で形成できるため、隣り合う半導体素子間の切
り込み溝は幅の狭い例えば２０μｍ幅のダイシングブレ
ードにて切りしろを小さくでき、１枚の半導体ウェーハ
でより多くの半導体装置を生産することができる。Therefore, since the insulating protective film on the side surface of the semiconductor substrate can be formed of a thin film, the cut groove between the adjacent semiconductor elements can be made small by using a dicing blade having a narrow width, for example, a width of 20 μm, so that one semiconductor can be cut. More semiconductor devices can be produced on a wafer.
【００２９】なお、本発明の実施の形態においてトラン
ジスタの例を用いたがダイオード等他の半導体装置につ
いても応用できる。Although the example of the transistor is used in the embodiment of the present invention, it can be applied to other semiconductor devices such as a diode.
【００３０】[0030]
【発明の効果】以上詳述しましたように本発明のチップ
型半導体装置によれば、セラミック基板を用いず、また
ＣＶＤ法による絶縁性保護膜の形成であるため、半導体
素子間の切り込み溝部分等の段差部での保護膜カバー性
の向上を図り、また半導体素子間の切り込みダイシング
工程数の削減により、より高いダイシング精度を必要と
しないといったメリットを有した、低コストの小型面実
装タイプのチップ型半導体装置を得ることができる。As described above in detail, according to the chip type semiconductor device of the present invention, since the ceramic substrate is not used and the insulating protective film is formed by the CVD method, the cut groove portion between the semiconductor elements is formed. It is a low-cost small surface-mount type that has the advantage of not requiring higher dicing accuracy by improving the protective film covering property at steps such as, and by reducing the number of dicing steps between semiconductor elements. A chip type semiconductor device can be obtained.
【００３１】また、側面全面に絶縁性保護膜が設けられ
ているのでベアチップのフリップチップ実装よりも実装
時のはんだ回り込みからの絶縁性・信頼性の向上が図れ
たり、ベアチップでの課題である検査や実装時の取り扱
いにおけるチッピングが防止でき、プリント基板への高
速実装が可能となる。したがって、外部環境からの影響
を受け難くなり品質・信頼性の確保が達成されたチップ
型半導体装置を得ることができる。Further, since the insulating protective film is provided on the entire side surface, it is possible to improve the insulating property and reliability from the solder wraparound at the time of mounting as compared with the flip chip mounting of the bare chip, and the inspection for the bare chip is a problem. Also, chipping during handling during mounting and mounting can be prevented, and high-speed mounting on a printed circuit board becomes possible. Therefore, it is possible to obtain a chip-type semiconductor device which is less likely to be affected by the external environment and whose quality and reliability are ensured.
【００３２】さらに、半導体基板側面の絶縁性保護膜は
薄膜で形成できるため隣り合う半導体素子間の切り込み
溝は、幅の広い例えば１００μｍ幅のダイシングブレー
ドを用いなくとも幅の狭い例えば２０μｍ幅のダイシン
グブレードにて切りしろを小さくできるため、１枚の半
導体ウェーハでより多くの半導体装置が生産できるとい
ったような多くの効果が得られる。Furthermore, since the insulating protective film on the side surface of the semiconductor substrate can be formed of a thin film, the dicing groove between adjacent semiconductor elements has a narrow dicing width of, for example, 20 μm without using a dicing blade having a wide width of, for example, 100 μm. Since the cutting margin can be reduced by the blade, many effects such that more semiconductor devices can be produced with one semiconductor wafer can be obtained.
【図１】（ａ）は本発明の第一の実施形態によるチップ
型半導体装置の透視平面図
（ｂ）はそのＢ−Ｂ線断面図
（ｃ）はそのＣ−Ｃ線断面図FIG. 1A is a perspective plan view of a chip-type semiconductor device according to a first embodiment of the present invention, FIG. 1B is a sectional view taken along line BB thereof, and FIG. 1C is a sectional view taken along line CC thereof.
【図２】本発明のチップ型半導体装置の製作過程を示す
断面構造図FIG. 2 is a sectional structural view showing a manufacturing process of a chip type semiconductor device of the present invention.
【図３】本発明のチップ型半導体装置の製作過程を示す
断面構造図FIG. 3 is a sectional structural view showing a manufacturing process of the chip type semiconductor device of the present invention.
【図４】本発明のチップ型半導体装置の製作過程を示す
断面構造図FIG. 4 is a sectional structural view showing a manufacturing process of the chip type semiconductor device of the present invention.
【図５】本発明のチップ型半導体装置の製作過程を示す
断面構造図FIG. 5 is a sectional structural view showing a manufacturing process of the chip type semiconductor device of the present invention.
【図６】（ａ）は従来のリードフレームを用いない小型
面実装型ダイオードの平面図
（ｂ）は（ａ）のＡ−Ａ線断面図
（ｃ）は（ａ）の底面図6A is a plan view of a small-sized surface-mount type diode without using a conventional lead frame, FIG. 6B is a sectional view taken along the line AA of FIG. 6A, and FIG. 6C is a bottom view of FIG.
【図７】（ａ）〜（ｆ）は従来の小型面実装型ダイオー
ドの製造方法を示す図7A to 7F are views showing a conventional method for manufacturing a small surface-mount type diode.
１ａ 第１コレクタ電極 １ｂ 第２コレクタ電極 ２ ベース電極 ３ エミッタ電極 ４ 半導体基板 ５ 絶縁性保護膜 ６〜８ 絶縁膜 ９ 配線金属層 １０ 半導体ウェーハ １１ 半導体素子 １２ ブレード １３ 切り込み溝 ２０ ダイオード ２１〜２４ 電極 ２５ 保護膜 ２６ セラミック基板 ２７ ダイオードチップ ２８、２９ バンプ ３０ ウェハ 1a first collector electrode 1b Second collector electrode 2 Base electrode 3 Emitter electrode 4 Semiconductor substrate 5 Insulating protective film 6-8 insulating film 9 Wiring metal layer 10 Semiconductor wafer 11 Semiconductor element 12 blades 13 Notch groove 20 diodes 21-24 electrodes 25 Protective film 26 Ceramic substrate 27 diode chips 28, 29 bumps 30 wafers
Claims (2)
けられ直接半導体装置の外部電極となる複数の電極と、
前記電極周辺の半導体基板裏面および前記半導体基板の
側面を被覆するＣＶＤ法による薄膜の絶縁性保護膜とよ
りなることを特徴とする小型面実装タイプのチップ型半
導体装置。1. A semiconductor substrate, and a plurality of electrodes provided on the back surface of the semiconductor substrate and directly serving as external electrodes of a semiconductor device,
A small surface mounting type chip-type semiconductor device comprising a thin insulating protective film formed by a CVD method for covering the back surface of the semiconductor substrate around the electrodes and the side surface of the semiconductor substrate.
を形成する工程と、複数の半導体素子が形成された半導
体ウェーハの裏面（電極面側）をダイシング用ブレード
で隣り合う半導体素子間に切り込み溝を形成する工程
と、前記半導体素子表面および切り込み溝表面にＣＶＤ
法による薄膜の絶縁性保護膜を形成する工程と、前記複
数の半導体素子にメタルバンプ等の電極を形成する工程
と、前記半導体ウェーハの表面を前記切り込み溝まで研
削して半導体チップを切り出す工程とよりなることを特
徴とするチップ型半導体装置の製造方法。2. A step of forming a plurality of semiconductor elements on one surface of a semiconductor wafer, and a groove for cutting a back surface (electrode surface side) of the semiconductor wafer having the plurality of semiconductor elements formed between adjacent semiconductor elements with a dicing blade. And a CVD process on the surface of the semiconductor element and the surface of the cut groove.
A step of forming a thin insulating protective film by a method, a step of forming electrodes such as metal bumps on the plurality of semiconductor elements, and a step of cutting a semiconductor chip by grinding the surface of the semiconductor wafer to the cut groove. A method for manufacturing a chip-type semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001334009A JP2003142631A (en) | 2001-10-31 | 2001-10-31 | Chip-type semiconductor device and manufacturing method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001334009A JP2003142631A (en) | 2001-10-31 | 2001-10-31 | Chip-type semiconductor device and manufacturing method therefor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003142631A true JP2003142631A (en) | 2003-05-16 |
Family
ID=19149202
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001334009A Pending JP2003142631A (en) | 2001-10-31 | 2001-10-31 | Chip-type semiconductor device and manufacturing method therefor |
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| Country | Link |
|---|---|
| JP (1) | JP2003142631A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006156863A (en) * | 2004-12-01 | 2006-06-15 | Hitachi Ltd | Semiconductor device and manufacturing method therefor |
| JP2007123756A (en) * | 2005-10-31 | 2007-05-17 | Technology Alliance Group Inc | Manufacturing method for semiconductor device and semiconductor device |
| JP2009088341A (en) * | 2007-10-01 | 2009-04-23 | Denso Corp | Method of processing chip and wafer |
| JP2009147108A (en) * | 2007-12-14 | 2009-07-02 | Denso Corp | Semiconductor chip and manufacturing method thereof |
-
2001
- 2001-10-31 JP JP2001334009A patent/JP2003142631A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006156863A (en) * | 2004-12-01 | 2006-06-15 | Hitachi Ltd | Semiconductor device and manufacturing method therefor |
| JP2007123756A (en) * | 2005-10-31 | 2007-05-17 | Technology Alliance Group Inc | Manufacturing method for semiconductor device and semiconductor device |
| JP2009088341A (en) * | 2007-10-01 | 2009-04-23 | Denso Corp | Method of processing chip and wafer |
| JP2009147108A (en) * | 2007-12-14 | 2009-07-02 | Denso Corp | Semiconductor chip and manufacturing method thereof |
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