JPS6156879B2 - - Google Patents
Info
- Publication number
- JPS6156879B2 JPS6156879B2 JP11385078A JP11385078A JPS6156879B2 JP S6156879 B2 JPS6156879 B2 JP S6156879B2 JP 11385078 A JP11385078 A JP 11385078A JP 11385078 A JP11385078 A JP 11385078A JP S6156879 B2 JPS6156879 B2 JP S6156879B2
- Authority
- JP
- Japan
- Prior art keywords
- photosensitive resist
- metal film
- pattern
- forming
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 16
- 239000010931 gold Substances 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 13
- 238000007747 plating Methods 0.000 claims description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 8
- 229910052737 gold Inorganic materials 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 238000007740 vapor deposition Methods 0.000 claims description 4
- 239000004020 conductor Substances 0.000 description 12
- 238000005530 etching Methods 0.000 description 12
- YMWUJEATGCHHMB-UHFFFAOYSA-N Dichloromethane Chemical compound ClCCl YMWUJEATGCHHMB-UHFFFAOYSA-N 0.000 description 3
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 239000010953 base metal Substances 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 2
- 229910001220 stainless steel Inorganic materials 0.000 description 2
- 239000010935 stainless steel Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000001680 brushing effect Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000010970 precious metal Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Description
【発明の詳細な説明】
本発明は多層回路基板の製造方法コンピユータ
等に用いるLSI実装用の高密度多層回路基板の製
造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a multilayer circuit board and a method for manufacturing a high-density multilayer circuit board for LSI mounting used in computers and the like.
従来、この種の多層回路基板の一つの構造では
貴金属の導体ペーストをシルクまたはステンレス
メツシユを通してスクリーン印刷し、高温焼成に
より導体ペーストを焼結させて導体パターンを形
成して、その上に絶縁層を形成して多層化してい
る。しかしながら、前記の方法ではシルクまたは
ステンレスメツシユを通してスクリーン印刷する
ため導体パターン線幅がせいぜい100〜120μ位が
限度であり、100μ以下の線幅を必要とする導体
パターンの形成は実際上困難であるという欠点が
ある。 Conventionally, one structure of this type of multilayer circuit board is to screen print a conductive paste of precious metal through silk or stainless steel mesh, sinter the conductive paste by high temperature firing to form a conductive pattern, and then apply an insulating layer on top of it. It forms a multi-layer structure. However, in the above method, the conductor pattern line width is limited to about 100 to 120μ at most because it is screen printed through silk or stainless steel mesh, and it is practically difficult to form a conductor pattern that requires a line width of 100μ or less. There is a drawback.
さらに、従来の他の構造は耐熱性絶縁基板の表
面にスパツタあるいは蒸着により金属膜を形成
し、その上に感光性レジストを塗布し、露光、現
像により回路パターンを形成し、この感光性レジ
ストの除去された部分に金メツキ等で部分メツキ
を施し、感光性レジストを剥離した後、金属膜を
エツチングすることにより導体パターンを形成し
ている。しかしながら、この方法では、耐熱性絶
縁基板の表面に換言すると平らな面に金属膜を形
成するので、金属層のエツチングのとき金メツキ
部の下層の部分までエツチングされてしまい、サ
イドエツチングが顕著におこる。実際上30μ以下
の導体パターンの形成はサイドエツチによる密着
性の劣化などから非常に困難であるという欠点が
ある。本発明の目的は上記欠点を除去した有効な
多層回路基板を提供することである。 Furthermore, in other conventional structures, a metal film is formed on the surface of a heat-resistant insulating substrate by sputtering or vapor deposition, a photosensitive resist is applied on top of the metal film, and a circuit pattern is formed by exposure and development. After partially plating the removed portion with gold plating or the like and peeling off the photosensitive resist, a conductor pattern is formed by etching the metal film. However, in this method, the metal film is formed on the flat surface of the heat-resistant insulating substrate, so when etching the metal layer, the lower layer of the gold-plated part is etched, resulting in noticeable side etching. It happens. In practice, forming a conductor pattern with a thickness of 30 μm or less is extremely difficult due to deterioration of adhesion due to side etching. An object of the present invention is to provide an effective multilayer circuit board that eliminates the above-mentioned drawbacks.
本発明の特徴は耐熱性絶縁基板の表面に予め感
光性レジストを塗布し、露光および現像をして回
路パターンを形成しておき、その上に金属膜を形
成した高密度の多層回路基板の製造方法である。 The feature of the present invention is to manufacture a high-density multilayer circuit board by coating the surface of a heat-resistant insulating substrate with a photosensitive resist in advance, exposing and developing it to form a circuit pattern, and then forming a metal film thereon. It's a method.
すなわちこの発明の多層基板は耐熱性絶縁基板
の表面に感光性レジストを塗布し露光および現像
により予め定められた回路パターンを形成する第
１の工程と、前記現像により感光性レジストが除
去された耐熱性絶縁基板の表面と除去されずに残
つた感光性レジストの表面にスパツタリングある
いは蒸着により金属膜を形成する第２の工程と、
前記金属膜の表面に感光性レジストを塗布し、露
光および現像により予め定められた回路パターン
を形成する第３の工程と、前記回路パターンの表
面だけを部分メツキする第４の工程と、前記第３
の工程で形成した感光性レジストを剥離する第５
の工程と、前記第２の工程で形成した金属膜をエ
ツチングする第６の工程と、前記第１の工程で形
成した感光性レジストを剥離して導体パターンを
形成する第７の工程と、前記耐熱性絶縁基板の前
記導体パターン形成部分を除く部分および前記導
体パターンの上に予め定められた位置にヴイアホ
ールが形成できるように絶縁層を形成する第８の
工程とを少なくとも１回以上繰り返して多層化す
ることを特徴とする。 That is, the multilayer substrate of the present invention includes a first step of applying a photosensitive resist on the surface of a heat-resistant insulating substrate, forming a predetermined circuit pattern by exposure and development, and a heat-resistant insulating substrate from which the photosensitive resist is removed by the development. a second step of forming a metal film by sputtering or vapor deposition on the surface of the photosensitive resist and the surface of the photosensitive resist that remains without being removed;
a third step of applying a photosensitive resist to the surface of the metal film and forming a predetermined circuit pattern by exposure and development; a fourth step of partially plating only the surface of the circuit pattern; and a fourth step of partially plating only the surface of the circuit pattern. 3
The fifth step is to peel off the photosensitive resist formed in step
a sixth step of etching the metal film formed in the second step; a seventh step of peeling off the photosensitive resist formed in the first step to form a conductor pattern; The eighth step of forming an insulating layer so that a via hole can be formed in a predetermined position on a portion of the heat-resistant insulating substrate excluding the conductor pattern forming portion and on the conductor pattern is repeated at least once to form a multilayer It is characterized by becoming
次に本発明の実施例について図面を参照して詳
細に説明する。第１図から第８図は本発明の高密
度多層回路基板の工程断面図を示す。第１図は耐
熱性絶縁基板１の表面に感光性レジスト２を全面
に塗布し、図示されていないガラスマスクを通し
て露光し、現像することにより所望の回路パター
ンを形成した状態を示す。解像度の点からみると
感光性レジストの膜厚は薄いほどより微細なパタ
ーンが得られるが、後工程のメツキ厚の厚さ（こ
れは導体抵抗値に関連する。）を考えて決定す
る。本実施例ではレジスト厚５μ〜15μでパター
ン線幅20μ〜30μが得られている。第２図は第１
図で形成した基板の表面にスパツタリングあるい
は蒸着により、Ti（チタン）、Cr（クロム）、Pd
（パラジウム）、Cu（銅）、Al（アルミニウム）等
の金属膜３を付着させた状態を示す。金属膜層は
通常１種あるいはこれらの組合せにより、１種あ
たり500Å〜2000Åの厚さを有する。第３図は前
記金属膜の表面に感光性レジスト４を全面に塗布
し図示されていないガラスマスクを通して露光、
および現像をして、所望の回路パターンを形成し
た状態を示す。この工程は第１図の工程と全く同
様である。すなわち、第１図の工程で形成した感
光性レジスト（現像されずに残つたもの）の真上
に金属膜をはさんで形成するものである。第４図
は前記感光性レジスト４をメツキレジストとし
て、その他の表面にAu（金）５を部分メツキし
た状態を示す。回路パターンは下地金属層で導通
しているので電解メツキ等で同時にメツキが可能
である。第５図は前記感光性レジスト４を塩化メ
チレンあるいは水酸化ナトリウム等の剥離液を用
い、ブラツシング機能を有する自動剥離装置等で
剥離した状態を示す。第６図は前記金属膜３をメ
ツキ形成されたAu（金）膜をレジストとして
FeCl3（塩化第二鉄）あるいはHF（フツ化水酸
素）＋HNO3（硝酸）等のエツチング液を用いて
エツチングした状態を示す。このとき、ウエツト
エツチングに顕著に生じるサイドエツチングが問
題になるが、前記第１図の工程で形成した感光性
レジスト膜のためにAu（金）の側面部の金属膜
がサイドエツチングされるだけでAu（金）の下
面の金属膜は何ら影響されないから、基板との密
着性は劣化しない。又、エツチングの際多少エツ
チング残りがあつても、次工程の感光性レジスト
の剥離のとき、同時に除去されるのでエツチング
時間の短縮が可能であり、このことはサイドエツ
チング防止の最も重要な項目の一つである。第７
図は前記第１図で形成した感光性レジスト２を第
５図の工程と同様にして剥離し導体パターンを形
成した状態を示す。ここで前記第６図の工程で金
属膜のエツチング残りがあれば同時に除去が可能
である。又、導体パターンの焼結が必要であれ
ば、900℃〜930℃の高温で焼成することにより、
導体パターンの焼結と同時に感光性レジストを焼
却することもできる。第８図は前記形成された導
体パターンの上に予め定められた位置にヴイアホ
ールが形成されるように絶縁層６を形成した状態
を示す。 Next, embodiments of the present invention will be described in detail with reference to the drawings. 1 to 8 show process cross-sectional views of the high-density multilayer circuit board of the present invention. FIG. 1 shows a state in which a photosensitive resist 2 is applied to the entire surface of a heat-resistant insulating substrate 1, exposed to light through a glass mask (not shown), and developed to form a desired circuit pattern. From the point of view of resolution, the thinner the photosensitive resist film is, the finer the pattern can be obtained, but this is determined by considering the plating thickness in the subsequent process (this is related to the conductor resistance value). In this example, a pattern line width of 20 to 30 microns is obtained with a resist thickness of 5 to 15 microns. Figure 2 is the first
Ti (titanium), Cr (chromium), and Pd are deposited on the surface of the substrate formed as shown in the figure by sputtering or vapor deposition.
The state in which a metal film 3 of (palladium), Cu (copper), Al (aluminum), etc. is attached is shown. The metal film layer is usually made of one type or a combination thereof and has a thickness of 500 Å to 2000 Å per type. FIG. 3 shows that a photosensitive resist 4 is applied to the entire surface of the metal film and exposed through a glass mask (not shown).
The image is then developed to form a desired circuit pattern. This process is completely similar to the process shown in FIG. That is, a metal film is formed directly on top of the photosensitive resist (remaining without being developed) formed in the process shown in FIG. 1. FIG. 4 shows a state in which the photosensitive resist 4 is used as a plating resist, and other surfaces are partially plated with Au (gold) 5. Since the circuit pattern is conductive through the underlying metal layer, it can be plated at the same time using electrolytic plating or the like. FIG. 5 shows a state in which the photosensitive resist 4 is peeled off using a stripping liquid such as methylene chloride or sodium hydroxide using an automatic stripping device having a brushing function. Figure 6 shows the Au (gold) film formed by plating the metal film 3 as a resist.
The state shown is etched using an etching solution such as FeCl 3 (ferric chloride) or HF (hydrogen fluoride) + HNO 3 (nitric acid). At this time, side etching, which occurs noticeably during wet etching, becomes a problem, but because of the photosensitive resist film formed in the process shown in Figure 1, only the metal film on the sides of the Au (gold) is side etched. Since the metal film on the bottom surface of Au (gold) is not affected in any way, the adhesion to the substrate does not deteriorate. Furthermore, even if there is some etching residue during etching, it will be removed at the same time when the photosensitive resist is removed in the next step, so the etching time can be shortened, which is the most important aspect of preventing side etching. There is one. 7th
The figure shows a state in which the photosensitive resist 2 formed in FIG. 1 is peeled off in the same manner as in the process shown in FIG. 5 to form a conductive pattern. Here, if there is any remaining metal film etched in the process shown in FIG. 6, it can be removed at the same time. Also, if it is necessary to sinter the conductor pattern, it can be fired at a high temperature of 900°C to 930°C.
It is also possible to incinerate the photosensitive resist at the same time as sintering the conductor pattern. FIG. 8 shows a state in which an insulating layer 6 is formed so that via holes are formed at predetermined positions on the formed conductor pattern.
本発明には、以上説明したように、回路パター
ンが形成されている感光性レジストの表面に、
Au（金）メツキ膜形成用の下地金属膜を形成
し、この金属膜をエツチングすることにより導体
パターン形成するため従来ウエツトエツチング方
法では不可能である30μ以下のパターン線幅を有
する微細なしかもエツジ切れのよいパターンを持
つ高密度多層回路基板が得られるということであ
る。 As explained above, in the present invention, on the surface of a photosensitive resist on which a circuit pattern is formed,
A conductor pattern is formed by forming a base metal film for forming the Au (gold) plating film and etching this metal film, so it may be possible to form a fine pattern with a pattern line width of 30μ or less, which is impossible with conventional wet etching methods. This means that a high-density multilayer circuit board with a pattern with good edge cutting can be obtained.
第１図乃至第８図は本発明の一実施例を工程順
に示す断面図である。
尚、図において、１……耐熱性絶縁基板、２…
…感光性レジスト、３……Auメツキ用下地金属
膜、４……感光性レジスト、５……Au（金）
膜、６……絶縁層である。
FIGS. 1 to 8 are cross-sectional views showing an embodiment of the present invention in the order of steps. In the figure, 1... heat-resistant insulating substrate, 2...
...Photosensitive resist, 3... Base metal film for Au plating, 4... Photosensitive resist, 5... Au (gold)
Film, 6... is an insulating layer.
Claims (1)
トによる回路パターンを形成する第１の工程と、
前記第１の感光性レジストが設けられていない耐
熱性絶縁基板の表面および前記第１の感光性レジ
ストの表面にスパツタリングあるいは蒸着により
金金属層を形成する第２の工程と、前記金属膜の
表面の前記回路パターン上に第２の感光性レジス
トを形成する第３の工程と、露出せる前記金属膜
の表面上に部分メツキをほどこす第４の工程と、
前記第２の感光性レジストを除去する第５の工程
と、露出せる前記金属膜を除去する第６の工程
と、露出せる前記第１の感光性レジストを除去す
る第７の工程とを含むことを特徴とする多層回路
基板の製造方法。1. A first step of forming a circuit pattern using a first photosensitive resist on the surface of a heat-resistant insulating substrate;
a second step of forming a gold metal layer by sputtering or vapor deposition on the surface of the heat-resistant insulating substrate on which the first photosensitive resist is not provided and on the surface of the first photosensitive resist; and the surface of the metal film. a third step of forming a second photosensitive resist on the circuit pattern; a fourth step of partially plating the exposed surface of the metal film;
The method includes a fifth step of removing the second photosensitive resist, a sixth step of removing the exposed metal film, and a seventh step of removing the exposed first photosensitive resist. A method for manufacturing a multilayer circuit board characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11385078A JPS5541708A (en) | 1978-09-16 | 1978-09-16 | Method of fabricating multilayer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11385078A JPS5541708A (en) | 1978-09-16 | 1978-09-16 | Method of fabricating multilayer circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5541708A JPS5541708A (en) | 1980-03-24 |
| JPS6156879B2 true JPS6156879B2 (en) | 1986-12-04 |
Family
ID=14622621
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11385078A Granted JPS5541708A (en) | 1978-09-16 | 1978-09-16 | Method of fabricating multilayer circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5541708A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0236984U (en) * | 1988-09-06 | 1990-03-12 |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3371592D1 (en) * | 1983-06-01 | 1987-06-19 | Ibm Deutschland | Production method of printed circuits with one conductive layer |
| JPH0812720B2 (en) * | 1992-05-29 | 1996-02-07 | 東邦瓦斯株式会社 | Gas shutoff device |
-
1978
- 1978-09-16 JP JP11385078A patent/JPS5541708A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0236984U (en) * | 1988-09-06 | 1990-03-12 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5541708A (en) | 1980-03-24 |
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