JPH0563340A - Manufacture of wiring board provided with functional element - Google Patents

Manufacture of wiring board provided with functional element

Info

Publication number
JPH0563340A
JPH0563340A JP3219852A JP21985291A JPH0563340A JP H0563340 A JPH0563340 A JP H0563340A JP 3219852 A JP3219852 A JP 3219852A JP 21985291 A JP21985291 A JP 21985291A JP H0563340 A JPH0563340 A JP H0563340A
Authority
JP
Japan
Prior art keywords
resist
layer
conductor pattern
pattern
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3219852A
Other languages
Japanese (ja)
Inventor
Yoshihiro Takahashi
佳弘 高橋
Yoshiaki Tsubomatsu
良明 坪松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Showa Denko Materials Co Ltd
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP3219852A priority Critical patent/JPH0563340A/en
Publication of JPH0563340A publication Critical patent/JPH0563340A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain the manufacturing method of a wiring board provided with a functional element wherein a functional element of high density and high precision can be easily and simply formed. CONSTITUTION:A tantalum nitride layer 12 formed on a stainless plate 11 is etched, a specified pattern is formed, a copper layer 13 is formed, plating resist is formed, and a conductor pattern 14 is formed. Until the cooper layer 13 except the conductor pattern part is completely eliminated, copper is etched. The above plate is stacked on a glass polyimide board 15, interposing polyimide prepreg, in the manner in which the the surface on which the conductor pattern 14 is formed faces the inner side. From the laminate obtained by pressing, the stainless plate 11 is peeled and removed, thereby obtaining a wiring board having a resistance element.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、抵抗素子または磁性素
子等の機能素子を有する配線板の製造法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a wiring board having a functional element such as a resistance element or a magnetic element.

【0002】[0002]

【従来の技術】抵抗素子または磁性素子等の機能素子
は、抵抗体または磁性体等と一対の電極とよりなるもの
で、配線板には必須の部品となっている。従来、抵抗素
子に代表される機能素子を有する配線板としては、直接
機能素子を搭載したもの、耐熱性の良い基板上にスクリ
ーン印刷法で各種ペーストを印刷した後、加熱処理を施
したものなどがある。電子機器の小型・高密度化が進む
につれて、機能素子に対する高密度化、高精度化の強い
要求があり、アルミナ基板や耐熱性ポリイミドフィルム
などに真空蒸着やスパッタリング等の薄膜技術により各
種機能層、導体層を形成後、フォトリソグラフィー技術
を用いて、導体層、機能層の順でパターニングを行い機
能素子を形成したものがある。
2. Description of the Related Art A functional element such as a resistance element or a magnetic element comprises a resistance element or a magnetic element and a pair of electrodes, and is an essential component for a wiring board. Conventionally, a wiring board having a functional element typified by a resistance element is one in which the functional element is directly mounted, one in which various pastes are printed by a screen printing method on a substrate having good heat resistance, and then subjected to heat treatment, etc. There is. As electronic devices become smaller and higher in density, there is a strong demand for higher density and higher precision in functional elements. Various functional layers are formed on alumina substrates and heat resistant polyimide films by thin film technology such as vacuum deposition and sputtering. There is one in which a functional element is formed by patterning a conductor layer and a functional layer in this order by using a photolithography technique after forming the conductor layer.

【0003】また、抵抗素子に関しては、銅箔上にめっ
きや真空蒸着により抵抗層を形成後、抵抗層を内側にし
て絶縁基板と積層し、銅箔パターン、抵抗パターンの順
でパターニングを行い、抵抗素子を形成したものが提案
されている(特開昭 62-257702号公報)。
Regarding the resistance element, after forming a resistance layer on a copper foil by plating or vacuum deposition, the resistance layer is placed inside and laminated on an insulating substrate, and patterning is performed in the order of a copper foil pattern and a resistance pattern. A resistance element is proposed (Japanese Patent Laid-Open No. 62-257702).

【0004】さらに、特願平1−343352号には、
「a.仮基板上に、真空成膜法により配線部となるパタ
ーンを構成する銅層を形成後、銅層上に銅層とは別の機
能を有するパターンを構成する一層以上の金属薄層を形
成する工程と、b.金属薄層を内側にして絶縁基板材料
と積層一体化した後仮基板を剥離し銅層及び金属薄層を
絶縁基板に転写する工程と、c.転写された銅層の表面
に第一のレジストパターンを形成し、銅めっきを施した
後、第一のレジストパターンを剥離する工程と、d.表
面に露出している銅層のうち所望する量をエッチング除
去した後、第二のレジストパターンを形成し、エッチン
グにより一層以上の金属薄層を所定のパターンに加工す
る工程とからなることを特徴とする配線板の製造法。」
が記載されている。
Further, Japanese Patent Application No. 1-343352 describes
"A. After forming a copper layer forming a pattern to be a wiring portion on a temporary substrate by a vacuum film forming method, one or more thin metal layers forming a pattern having a function different from that of the copper layer on the copper layer B. Forming a thin metal layer inside and laminating and integrating with the insulating substrate material, peeling the temporary substrate and transferring the copper layer and the metal thin layer to the insulating substrate, and c. Forming a first resist pattern on the surface of the layer, performing copper plating, and then peeling off the first resist pattern, and d. Etching a desired amount of the copper layer exposed on the surface. Then, a second resist pattern is formed, and a step of etching one or more thin metal layers into a predetermined pattern by etching is performed.
Is listed.

【0005】[0005]

【発明が解決しようとする課題】ガラスエポキシ基材や
ガラスポリイミド基材等の汎用の配線板用有機基材をベ
ースの絶縁基板とした場合、有機基材の耐熱性が低いた
めスクリーン印刷法および薄膜法の適用は困難であり、
部品搭載法が一般的であり、配線板の高密度化は望めな
い。
When a general-purpose wiring board organic material such as a glass epoxy material or a glass polyimide material is used as the insulating substrate, the heat resistance of the organic material is low and the screen printing method and It is difficult to apply the thin film method,
Since the component mounting method is common, high density wiring boards cannot be expected.

【0006】一方、銅箔上に抵抗層を形成後有機基材と
積層する方法は、部品搭載法に比べれば高密度化に適し
た方法であるが、(1)使用する銅箔の厚さが18〜35μ
mと厚いため、配線形成時にサイドエッチングが問題と
なり微細化に限界があること、(2)主に銅箔の粗化面
に抵抗層を形成するためプリプレグ等と積層する場合、
特にガラス布の交点部分で抵抗層にクラックが生じるこ
と、(3)積層時に、最外層となる銅箔表面の”焼け”
のため、レジスト形成用に銅箔の表面処理が必要なこと
などの問題があり、真に高密度な抵抗素子を安定に形成
することは困難である。
On the other hand, a method of forming a resistance layer on a copper foil and then laminating it with an organic base material is a method suitable for higher density than the component mounting method. (1) Thickness of copper foil to be used Is 18-35μ
Since it is thick as m, side etching becomes a problem during wiring formation and there is a limit to miniaturization. (2) When laminating with a prepreg or the like mainly to form a resistance layer on a roughened surface of a copper foil,
In particular, cracks occur in the resistance layer at the intersections of the glass cloth. (3) "Burn" on the outermost copper foil surface during lamination.
Therefore, there is a problem that the surface treatment of the copper foil is required for resist formation, and it is difficult to stably form a truly high-density resistance element.

【0007】さらに、特願平1−343352号に記載
の方法では、導体パターン(抵抗素子の電極を含む)を
形成した後、抵抗パターンを形成するために、導体パタ
ーンの厚みが5〜35μmと厚い場合、抵抗パターン形成
のためのエッチングレジストを精度良く形成することが
難しく、抵抗素子の高密度化は困難である。本発明は、
高密度、高精度な機能素子の容易かつ簡便な製造を可能
にする機能素子を有する配線板の製造法を提供するもの
である。
Further, according to the method described in Japanese Patent Application No. 1-343352, after forming a conductor pattern (including an electrode of a resistance element), the conductor pattern has a thickness of 5 to 35 μm in order to form the resistance pattern. If it is thick, it is difficult to accurately form an etching resist for forming a resistance pattern, and it is difficult to increase the density of resistance elements. The present invention is
It is intended to provide a method of manufacturing a wiring board having a functional element that enables easy and simple manufacture of a functional element with high density and high accuracy.

【0008】[0008]

【課題を解決するための手段】本願の第一の発明は、
(A1)仮基板上に、導通とは異なる機能を有する所定
パターンの薄層を形成し、(B1)めっきレジストを形
成し、めっきにより所定の導体パターンを形成し、めっ
きレジストを除去し、(C1)仮基板を、導体パターン
が形成された面が内側にくるようにして絶縁基材と重ね
合せ一体化した後、仮基板を除去することを含む機能素
子を有する配線板の製造法である。
The first invention of the present application is
(A1) A thin layer having a predetermined pattern having a function different from conduction is formed on the temporary substrate, (B1) a plating resist is formed, a predetermined conductor pattern is formed by plating, and the plating resist is removed. C1) A method of manufacturing a wiring board having a functional element, which comprises removing a temporary substrate after superimposing and integrating the temporary substrate with an insulating base material so that a surface on which a conductor pattern is formed faces inward. ..

【0009】本願の第二の発明は、(A2)仮基板上に
めっきレジストを形成し、めっきにより所定の導体パタ
ーンを形成し、めっきレジストを除去し、(B2)導通
とは異なる機能を有する薄層を形成し、(C2)仮基板
を、導通とは異なる機能を有する薄層が形成された面が
内側にくるようにして絶縁基材と重ね合せ一体化した
後、仮基板を除去し、(D2)露出した導体パターンお
よび導通とは異なる機能を有する薄層の上にエッチング
レジストを形成し、エッチングにより機能素子を構成す
る箇所以外の薄層を除去し、エッチングレジストを除去
することを含む機能素子を有する配線板の製造法であ
る。
A second invention of the present application has (A2) a plating resist is formed on a temporary substrate, a predetermined conductor pattern is formed by plating, the plating resist is removed, and (B2) has a function different from conduction. A thin layer is formed, and (C2) the temporary substrate is laminated and integrated with an insulating base material so that the surface on which the thin layer having a function different from conduction is formed is inward, and then the temporary substrate is removed. , (D2) forming an etching resist on the exposed conductive pattern and a thin layer having a function different from the conduction, and removing the thin layer other than the portion constituting the functional element by etching to remove the etching resist. It is a method of manufacturing a wiring board having a functional element including the same.

【0010】本願の第三の発明は、(A3)仮基板上
に、導通とは別の機能を有する薄層を形成し、(B3)
めっきレジストを形成し、めっきにより所定の導体パタ
ーンを形成し、めっきレジストを除去し、(C3)仮基
板を、導体パターンの形成された面が内側にくるように
して絶縁基板と重ね合せ一体化した後、仮基板を除去
し、(D3)露出した導通とは別の機能を有する薄層上
にエッチングレジストを形成し、エッチングにより機能
素子を構成する箇所以外の薄層を除去し、エッチングレ
ジストを除去することを含む機能素子を有する配線板の
製造法である。
According to a third aspect of the present invention, (A3) a thin layer having a function different from conduction is formed on the temporary substrate, and (B3).
A plating resist is formed, a predetermined conductor pattern is formed by plating, the plating resist is removed, and the (C3) temporary substrate is integrated with the insulating substrate so that the surface on which the conductor pattern is formed faces inside. After that, the temporary substrate is removed, (D3) an etching resist is formed on the exposed thin layer having a function different from that of the conduction, and the thin layer other than the portion constituting the functional element is removed by etching to obtain an etching resist. Is a method for manufacturing a wiring board having a functional element including removing.

【0011】本願の第四の発明は、(A4)仮基板上に
導体薄層を形成し、(B4)導通とは異なる機能を有す
る所定パターンの薄層を形成し、(C4)仮基板を、導
通とは異なる機能を有する所定パターンの薄層が形成さ
れた面が内側にくるようにして絶縁基板と重ね合せ一体
化した後、仮基板を除去し、(D4)めっきレジストを
形成し、めっきにより所定の導体パターンを形成し、め
っきレジストを除去し、(E4)導体パターンが形成さ
れている箇所以外の導体薄層を除去することを含む機能
素子を有する配線板の製造法である。
According to a fourth aspect of the present invention, (A4) a thin conductor layer is formed on a temporary substrate, (B4) a thin layer having a predetermined pattern having a function different from conduction is formed, and (C4) a temporary substrate is formed. , The surface on which the thin layer having a predetermined pattern having a function different from the conduction is formed is inward, the insulating substrate is superposed and integrated, and then the temporary substrate is removed to form a (D4) plating resist, This is a method for producing a wiring board having a functional element, which comprises forming a predetermined conductor pattern by plating, removing the plating resist, and (E4) removing the conductor thin layer other than the portion where the conductor pattern is formed.

【0012】図1は第一の発明の一実施例を示すもので
ある。ステンレス板11をアセトンにより洗浄した後、
ステンレス板11の片面にスパッタリング装置(日本真
空製、MLH−6315D型)を用いて窒素ガスを流し
ながらタンタルをスパッタリングし、窒化タンタル層1
2(厚さ:500Å)を形成した。この窒化タンタル層1
2上に、ホットロールラミネーターでレジスト(日立化
成製、フォテックPHT−887)をラミネートし、フ
ォトマスクを当て、露光機により露光した。次に、炭酸
ナトリウム水溶液をスプレー現像機により吹きつけてレ
ジストを現像した。その後、ステンレス板11をフッ化
水素酸中に浸漬し、レジストパターンで覆われていない
部分の窒化タンタル層12をエッチングし、所定のパタ
ーンを形成した。エッチング後、ステンレス板11を水
酸化ナトリウム水溶液中に浸漬してレジストパターンを
剥離し、さらに希硫酸で洗浄した。このステンレス板1
1の窒化タンタル層12のパターンが形成された面に、
真空蒸着装置(日本真空製、EBV−6DA型)を用い
て銅層13(厚さ:1000Å)を形成した。この銅層13
上に、ホットロールラミネーターでレジスト(日立化成
製、フォテックPHT−887)をラミネートし、フォ
トマスクを位置合わせして当て、露光機により露光し
た。その後、炭酸ナトリウム水溶液をスプレー現像機に
より吹きつけてレジストを現像した。現像により得られ
たレジストパターンをめっきレジストとして、硫酸銅浴
により銅をめっきして導体パターン14(厚さ:40μ
m)を形成した。導体パターンは、図1に示すような抵
抗素子の一対の電極を含むものである。めっき後、ステ
ンレス板11を水酸化ナトリウム水溶液中に浸漬し、レ
ジストを剥離した(図1(a))。さらに、ステンレス
板11を過硫酸アンモニウム水溶液中に浸漬して、導体
パターン部分以外の銅層13が完全に除去されるまで銅
のエッチングを行った(図1(b))。このステンレス
板11を、希硫酸により洗浄した後、導体パターン14
の形成された面が内側にくるようにポリイミドプリプレ
グをはさんでガラスポリイミド基板15と重ね、プレス
した(図1(c))。得られた積層体からステンレス板
11を剥し取り(図1(d))、抵抗素子を有する配線
板を得た。
FIG. 1 shows an embodiment of the first invention. After washing the stainless steel plate 11 with acetone,
Tantalum is sputtered on one surface of the stainless steel plate 11 using a sputtering device (MLH-6315D manufactured by Nippon Vacuum Co., Ltd.) while flowing a nitrogen gas, and the tantalum nitride layer 1 is formed.
2 (thickness: 500Å) was formed. This tantalum nitride layer 1
A resist (Photech PHT-887, manufactured by Hitachi Chemical Co., Ltd.) was laminated on 2 with a hot roll laminator, a photomask was applied, and an exposure device was used for exposure. Next, an aqueous sodium carbonate solution was sprayed with a spray developing machine to develop the resist. Then, the stainless steel plate 11 was dipped in hydrofluoric acid, and the tantalum nitride layer 12 in the portion not covered with the resist pattern was etched to form a predetermined pattern. After etching, the stainless steel plate 11 was dipped in an aqueous solution of sodium hydroxide to remove the resist pattern, and further washed with dilute sulfuric acid. This stainless steel plate 1
On the surface on which the pattern of the tantalum nitride layer 12 of No. 1 is formed,
A copper layer 13 (thickness: 1000Å) was formed using a vacuum vapor deposition apparatus (EBV-6DA type manufactured by Nippon Vacuum). This copper layer 13
A resist (Photech PHT-887, manufactured by Hitachi Chemical Co., Ltd.) was laminated on the top with a hot roll laminator, a photomask was aligned and applied, and an exposure machine was used for exposure. Then, an aqueous solution of sodium carbonate was sprayed with a spray developing machine to develop the resist. Using the resist pattern obtained by development as a plating resist, copper is plated in a copper sulfate bath to form a conductor pattern 14 (thickness: 40 μm
m) was formed. The conductor pattern includes a pair of electrodes of the resistance element as shown in FIG. After plating, the stainless steel plate 11 was dipped in an aqueous sodium hydroxide solution to remove the resist (FIG. 1 (a)). Further, the stainless steel plate 11 was immersed in an aqueous solution of ammonium persulfate, and copper was etched until the copper layer 13 other than the conductor pattern portion was completely removed (FIG. 1 (b)). After cleaning the stainless steel plate 11 with dilute sulfuric acid, the conductor pattern 14 is formed.
The polyimide prepreg was sandwiched so that the surface on which was formed was inward, and the glass polyimide substrate 15 was stacked and pressed (FIG. 1 (c)). The stainless steel plate 11 was peeled off from the obtained laminate (FIG. 1 (d)) to obtain a wiring board having a resistance element.

【0013】図2は第二の発明の一実施例を示すもので
ある。ステンレス板21を希硫酸により洗浄した後、ス
テンレス板21の片面にホットロールラミネーターでレ
ジスト(日立化成製、フォッテックPHT−887)を
ラミネートし、フォトマスクを当て、露光機により露光
した。露光後、炭酸ナトリウム水溶液をスプレー現像機
により吹きつけてレジストを現像した。得られたレジス
トパターンをめっきレジストとして、硫酸銅浴により銅
をめっきし、導体パターン22(厚さ:40μm)を形成
した。導体パターンは、図2に示すような抵抗素子の一
対の電極を含むものである。めっき後、ステンレス板2
1を水酸化ナトリウム水溶液中に浸漬して、レジストを
剥離した。このステンレス板21を希硫酸により洗浄し
た後、導体パターン22が形成された面に、ニッケル−
リン合金めっき浴によりニッケル−リン層23(厚さ:
500Å)を形成した(図2(a))。めっき後、ステン
レス板21を、導体パターン22の形成された面が内側
にくるようにポリテトラフルオロエチレンプリプレグを
はさんでガラス−ポリテトラフルオロエチレン基板24
と重ね、プレスした(図2(b))。得られた積層体か
らステンレス板21を剥し取り(図2(c))、露出し
た導体パターン22およびニッケル−リン層23表面を
希硫酸で洗浄した。この導体パターン22およびニッケ
ル−リン層23上に、ホットロールラミネーターでレジ
スト(日立化成製、フォッテックPHT−887)をラ
ミネートし、フォトマスクを位置合わせして当て、露光
機により露光した。露光後、炭酸ナトリウム水溶液をス
プレー現像機により吹きつけてレジストを現像した。得
られたレジストパターンをエッチングレジストとして、
過硫酸アンモニウム水溶液を用いて、エッチングマシー
ンによりエッチングレジストで覆われていない部分の導
体パターン22およびニッケル−リン層23をエッチン
グした。その後、積層体を水酸化ナトリウム水溶液中に
浸漬して、レジストを剥離し、さらに希硫酸で洗浄した
(図2(d))。このようにして、抵抗素子を有する配
線板を得た。
FIG. 2 shows an embodiment of the second invention. After the stainless steel plate 21 was washed with dilute sulfuric acid, a resist (Fottec PHT-887 manufactured by Hitachi Chemical Co., Ltd.) was laminated on one surface of the stainless steel plate 21 with a hot roll laminator, a photomask was applied, and an exposure machine was used for exposure. After the exposure, an aqueous sodium carbonate solution was sprayed with a spray developing machine to develop the resist. Using the obtained resist pattern as a plating resist, copper was plated in a copper sulfate bath to form a conductor pattern 22 (thickness: 40 μm). The conductor pattern includes a pair of electrodes of a resistance element as shown in FIG. After plating, stainless plate 2
1 was immersed in an aqueous solution of sodium hydroxide to remove the resist. After this stainless steel plate 21 was washed with dilute sulfuric acid, nickel-plated on the surface on which the conductor pattern 22 was formed.
The nickel-phosphorus layer 23 (thickness:
500 Å) was formed (Fig. 2 (a)). After plating, the glass plate-polytetrafluoroethylene substrate 24 is sandwiched between the stainless steel plate 21 and the polytetrafluoroethylene prepreg so that the surface on which the conductor pattern 22 is formed faces inward.
Was stacked and pressed (Fig. 2 (b)). The stainless steel plate 21 was peeled off from the obtained laminated body (FIG. 2C), and the exposed conductor pattern 22 and the surface of the nickel-phosphorus layer 23 were washed with dilute sulfuric acid. A resist (Fottec PHT-887, manufactured by Hitachi Chemical Co., Ltd.) was laminated on the conductor pattern 22 and the nickel-phosphorus layer 23 with a hot roll laminator, a photomask was aligned and applied, and exposed by an exposure device. After the exposure, an aqueous sodium carbonate solution was sprayed with a spray developing machine to develop the resist. The obtained resist pattern as an etching resist,
The conductive pattern 22 and the nickel-phosphorus layer 23, which are not covered with the etching resist, were etched by an etching machine using an ammonium persulfate aqueous solution. After that, the laminated body was immersed in an aqueous sodium hydroxide solution to remove the resist, and further washed with dilute sulfuric acid (FIG. 2 (d)). In this way, a wiring board having a resistance element was obtained.

【0014】図3は第三の発明の一実施例を示すもので
ある。ステンレス板31をアセトンにより洗浄した後、
ステンレス板31の片面に真空蒸着装置(日本真空製、
EBV−6DA型)を用いてニクロム層32(厚さ:50
0Å、Ni:Cr=4:1)を形成し、さらに、ニクロム層3
2上に銅層33(厚さ:1000Å)を形成した。この銅層
33上に、ホットロールラミネーターでレジスト(日立
化成製、フォテックPHT−887)をラミネートし、
フォトマスクを当て、露光機により露光した。その後、
炭酸ナトリウム水溶液をスプレー現像機により吹きつけ
てレジストを現像した。現像により得られたレジストパ
ターンをめっきレジストとして、硫酸銅浴により銅のパ
ターンめっき(厚さ:40μm)を行い、導体パターン3
4を形成した。導体パターンは、図3に示すような抵抗
素子の一対の電極を含むものである。めっき後、ステン
レス板31を水酸化ナトリウム水溶液中に浸漬して、レ
ジストパターンを剥離した(図3(a))。次に、ステ
ンレス板31をアルカリエッチング液(メルテックス
製、エープロセス建浴液)中に浸漬して、導体パターン
34部分以外のニクロム層32上の銅層33が完全に除
去されるまで銅のエッチングを行った(図3(b))。
このステンレス板31を、希硫酸により洗浄した後、導
体パターン34の形成された面が内側にくるようにエポ
キシプリプレグをはさんでガラスエポキシ基板35と重
ね、プレスした(図3(c))。得られた積層体からス
テンレス板31を剥し取り(図3(d))、露出したニ
クロム層32の表面を希硫酸で洗浄した。このニクロム
層32上に、ホットロールラミネーターでレジスト(日
立化成製、フォテックPHT−887)をラミネート
し、フォトマスクを位置合わせして当て、露光機により
露光した。露光後、炭酸ナトリウム水溶液をスプレー現
像機により吹きつけて現像し、エッチングレジストを形
成した。次に、過硫酸アンモニウム水溶液を用いて、エ
ッチングマシーンによりレジストパターンで覆われてい
ない部分のニクロム層32をエッチング除去した。その
後、積層体を水酸化ナトリウム水溶液中に浸漬して、エ
ッチングレジストを剥離し、さらに希硫酸で洗浄した
(図3(e))。このようにして、抵抗素子を有する配
線板を得た。
FIG. 3 shows an embodiment of the third invention. After washing the stainless steel plate 31 with acetone,
A vacuum deposition device (made by Nippon Vacuum Co., Ltd.
Using EBV-6DA type, nichrome layer 32 (thickness: 50
0Å, Ni: Cr = 4: 1), and further nichrome layer 3
A copper layer 33 (thickness: 1000Å) was formed on 2. A resist (Photech PHT-887, manufactured by Hitachi Chemical Co., Ltd.) is laminated on the copper layer 33 with a hot roll laminator,
A photomask was applied and exposure was performed by an exposure device. afterwards,
The resist was developed by spraying an aqueous sodium carbonate solution with a spray developing machine. Using the resist pattern obtained by development as a plating resist, copper pattern plating (thickness: 40 μm) is performed in a copper sulfate bath to form a conductor pattern 3
4 was formed. The conductor pattern includes a pair of electrodes of a resistance element as shown in FIG. After plating, the stainless steel plate 31 was dipped in an aqueous solution of sodium hydroxide to remove the resist pattern (FIG. 3 (a)). Next, the stainless steel plate 31 is dipped in an alkaline etching solution (Meltex, A process building bath solution) to remove copper until the copper layer 33 on the nichrome layer 32 other than the conductor pattern 34 is completely removed. Etching was performed (FIG. 3 (b)).
After this stainless steel plate 31 was washed with dilute sulfuric acid, it was stacked and pressed with a glass epoxy substrate 35 with an epoxy prepreg sandwiched so that the surface on which the conductor pattern 34 was formed faces inward (FIG. 3 (c)). The stainless steel plate 31 was peeled off from the obtained laminate (FIG. 3D), and the exposed surface of the nichrome layer 32 was washed with dilute sulfuric acid. A resist (Photech PHT-887, manufactured by Hitachi Chemical Co., Ltd.) was laminated on the nichrome layer 32 with a hot roll laminator, a photomask was aligned and applied, and an exposure device was used for exposure. After the exposure, an aqueous solution of sodium carbonate was sprayed with a spray developing machine to develop the solution, thereby forming an etching resist. Next, an aqueous solution of ammonium persulfate was used to etch away the portion of the nichrome layer 32 not covered with the resist pattern by an etching machine. Then, the laminate was immersed in an aqueous sodium hydroxide solution to remove the etching resist, and further washed with dilute sulfuric acid (FIG. 3 (e)). In this way, a wiring board having a resistance element was obtained.

【0015】図4は本発明の一実施例を示すものであ
る。ガラス板41をアセトンにより洗浄した後、ガラス
板41の片面に真空蒸着装置(日本真空製、EBV−6
DA型)を用いて銅層2(厚さ:3000Å)を形成した。
この銅層42上に、スピンコーターでレジスト(シップ
レイ製、TF−20)を10μmの厚さにコートし、プリ
ベーク後、フォトマスクを当て露光機により露光した。
露光後、レジストをTF−20専用現像液を用いてスプ
レー現像機により現像し、さらにポストベークした。こ
のガラス板のレジストパターンが形成された面に、真空
蒸着装置(日本真空製、EBV−6DA型)を用いてク
ロム−二酸化ケイ素層43(厚さ:2000Å、Cr:SiO2=
1:1)を形成し、その後、ガラス板41をアセトン中に
浸漬し、レジストパターンを溶解除去した。この際、レ
ジストパターン上に蒸着されたクロム−二酸化ケイ素層
43は同時に除去され、クロム−二酸化ケイ素層のパタ
ーンが形成される(図4(a))。このガラス板41
を、クロム−二酸化ケイ素層43のパターンが形成され
た面が内側にくるようにエポキシプリプレグをはさんで
ガラスエポキシ基板44と重ね、プレスした(図4
(b))。得られた積層体からガラス板41を剥し取り
(図4(c))、露出した銅層42の表面を希硫酸で洗
浄した。この銅層42上に、ホットロールラミネーター
でレジスト(日立化成製、フォッテックPHT−88
7)をラミネートし、フォトマスクを位置合わせして当
て、露光機により露光した。露光後、炭酸ナトリウム水
溶液をスプレー現像機により吹きつけてレジストを現像
した。得られたレジストパターンをめっきレジストとし
て、硫酸銅浴により銅をめっきし、導体パターン45
(厚さ:40μm)を形成した。導体パターンは、図4に
示すような抵抗素子の一対の電極を含むものである。め
っき後、積層体を水酸化ナトリウム水溶液中に浸漬し、
レジストを剥離した(図4(d))。次に、積層体を過
硫酸アンモニウム水溶液中に浸漬して、導体パターン部
分以外の銅層42が完全に除去されるまで銅のエッチン
グを行った(図4(e))。このようにして、抵抗素子
を有する配線板を得た。
FIG. 4 shows an embodiment of the present invention. After cleaning the glass plate 41 with acetone, a vacuum vapor deposition device (manufactured by Nippon Vacuum Co., Ltd., EBV-6
A copper layer 2 (thickness: 3000Å) was formed using DA type).
A resist (made by Shipley, TF-20) having a thickness of 10 μm was coated on the copper layer 42 with a spin coater, prebaked, and then exposed with a photomask by applying a photomask.
After the exposure, the resist was developed with a spray developing machine using a developer exclusively for TF-20, and then post-baked. On the surface of the glass plate on which the resist pattern was formed, a chromium-silicon dioxide layer 43 (thickness: 2000Å, Cr: SiO2 =) was formed by using a vacuum vapor deposition device (manufactured by Nippon Vacuum Co., Ltd., EBV-6DA type).
1: 1) was formed, and then the glass plate 41 was immersed in acetone to dissolve and remove the resist pattern. At this time, the chromium-silicon dioxide layer 43 deposited on the resist pattern is removed at the same time, and a pattern of the chromium-silicon dioxide layer is formed (FIG. 4 (a)). This glass plate 41
Was laminated and pressed with a glass epoxy substrate 44 with an epoxy prepreg so that the surface on which the pattern of the chrome-silicon dioxide layer 43 was formed was inward (FIG. 4).
(B)). The glass plate 41 was peeled off from the obtained laminate (FIG. 4C), and the exposed surface of the copper layer 42 was washed with dilute sulfuric acid. On this copper layer 42, a resist (Fottec PHT-88, manufactured by Hitachi Chemical Co., Ltd.) was used with a hot roll laminator.
7) was laminated, a photomask was aligned and applied, and exposed by an exposure device. After the exposure, an aqueous sodium carbonate solution was sprayed with a spray developing machine to develop the resist. Using the obtained resist pattern as a plating resist, copper is plated in a copper sulfate bath to form a conductor pattern 45.
(Thickness: 40 μm) was formed. The conductor pattern includes a pair of electrodes of a resistance element as shown in FIG. After plating, soak the laminate in an aqueous sodium hydroxide solution,
The resist was peeled off (FIG. 4 (d)). Next, the laminate was immersed in an aqueous solution of ammonium persulfate, and copper was etched until the copper layer 42 other than the conductor pattern portion was completely removed (FIG. 4 (e)). In this way, a wiring board having a resistance element was obtained.

【0016】仮基板としては、ステンレス板以外に銅
板、銅箔、ガラス板、セラミック板、樹脂板、樹脂フィ
ルム等が使用される。導通とは別の機能を有する薄層と
して、抵抗素子が得たい場合は、ニクロム、窒化タンタ
ル、クロム−二酸化ケイ素、ニッケル−リン等の抵抗層
を、磁性素子が得たい場合は、鉄、ニッケル、コバル
ト、あるいはパーマロイ等のそれらの合金の磁性層を形
成する。この薄層の厚さは、0.01〜10μmが好ましい。
また、薄層は蒸着、スパッタリング、プラズマCVD等
の真空成膜法、または電気めっき、無電解めっき等で形
成され、所定のパターンを得るためには、エッチング、
リフトオフ等の適当な手法を用いることができる。
As the temporary substrate, a copper plate, a copper foil, a glass plate, a ceramic plate, a resin plate, a resin film or the like is used in addition to the stainless plate. As a thin layer having a function different from conduction, if a resistance element is desired, a resistance layer such as nichrome, tantalum nitride, chromium-silicon dioxide, or nickel-phosphorus is used.If a magnetic element is desired, iron or nickel is used. A magnetic layer of cobalt, cobalt, or an alloy thereof such as permalloy. The thickness of this thin layer is preferably 0.01 to 10 μm.
Further, the thin layer is formed by a vacuum film forming method such as vapor deposition, sputtering, plasma CVD, or electroplating, electroless plating, etc. In order to obtain a predetermined pattern, etching,
A suitable technique such as lift-off can be used.

【0017】導体としては、銅が好ましいが、金、銀、
ニッケル、クロム等も使用し得、電気めっき、無電解め
っき等で導体パターンが形成される。導体パターンの厚
さは1〜100μmが好ましい。導体パターンには抵抗素子
の一対の電極が含まれている。絶縁基材としては、フェ
ノール、エポキシ、ポリイミド、ポリテトラフルオロエ
チレン等の積層板以外に、ポリエチレンテレフタレー
ト、ポリイミド、ポリテトラフルオロエチレン等のフィ
ルム、接着剤付きセラミック板等が使用し得る。めっき
レジスト、エッチングレジストはポジあるいはネガ型の
液状またはフィルム状感光性レジストが好ましい。
Copper is preferred as the conductor, but gold, silver,
Nickel, chrome, etc. can also be used, and the conductor pattern is formed by electroplating, electroless plating or the like. The thickness of the conductor pattern is preferably 1 to 100 μm. The conductor pattern includes a pair of electrodes of the resistance element. As the insulating base material, a film of polyethylene terephthalate, polyimide, polytetrafluoroethylene, or the like, a ceramic plate with an adhesive, or the like can be used in addition to the laminated plate of phenol, epoxy, polyimide, polytetrafluoroethylene, or the like. The plating resist or etching resist is preferably a positive or negative type liquid or film type photosensitive resist.

【0018】[0018]

【発明の効果】本発明では、抵抗素子、磁性素子等の機
能素子の高密度化、高精度化を、仮基板を使用して絶縁
基板に転写するという手法をとることにより、容易かつ
簡便に達成することができる。
According to the present invention, the high density and high precision of the functional elements such as the resistance element and the magnetic element are transferred to the insulating substrate using the temporary substrate. Can be achieved.

【図面の簡単な説明】[Brief description of drawings]

【図1】第一の発明の製造工程を示す断面図である。FIG. 1 is a cross-sectional view showing the manufacturing process of the first invention.

【図2】第二の発明の製造工程を示す断面図である。FIG. 2 is a cross-sectional view showing the manufacturing process of the second invention.

【図3】第三の発明の製造工程を示す断面図である。FIG. 3 is a cross-sectional view showing the manufacturing process of the third invention.

【図4】第四の発明の製造工程を示す断面図である。FIG. 4 is a cross-sectional view showing the manufacturing process of the fourth invention.

【符号の説明】[Explanation of symbols]

11 ステンレス板 12 窒化タンタル層 13 銅層 14 導体パターン 15 ガラスポリイミド基板 21 ステンレス板 22 導体パターン 23 ニッケル−リン層 23 銅層 24 ガラス−ポリテトラフルオロエチレン基板 31 ステンレス板 32 ニクロム層 33 銅層 34 導体パターン 35 ガラスエポキシ基板 41 ガラス板 42 銅層 43 クロム−二酸化ケイ素層 44 ガラスエポキシ基板 45 導体パターン 11 Stainless Steel Plate 12 Tantalum Nitride Layer 13 Copper Layer 14 Conductor Pattern 15 Glass Polyimide Substrate 21 Stainless Steel Plate 22 Conductor Pattern 23 Nickel-Phosphorus Layer 23 Copper Layer 24 Glass-Polytetrafluoroethylene Substrate 31 Stainless Steel Plate 32 Nichrome Layer 33 Copper Layer 34 Conductor Pattern 35 Glass epoxy substrate 41 Glass plate 42 Copper layer 43 Chrome-silicon dioxide layer 44 Glass epoxy substrate 45 Conductor pattern

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】(A1)仮基板上に、導通とは異なる機能
を有する所定パターンの薄層を形成し、 (B1)めっきレジストを形成し、めっきにより所定の
導体パターンを形成し、めっきレジストを除去し、 (C1)仮基板を、導体パターンが形成された面が内側
にくるようにして絶縁基材と重ね合せ一体化した後、仮
基板を除去することを含む機能素子を有する配線板の製
造法。
(A1) A thin layer having a predetermined pattern having a function different from conduction is formed on a temporary substrate, (B1) a plating resist is formed, and a predetermined conductor pattern is formed by plating, and the plating resist is formed. (C1) A wiring board having a functional element including removing the temporary substrate after superimposing and integrating the temporary substrate with the insulating base material so that the surface on which the conductor pattern is formed faces the inside. Manufacturing method.
【請求項2】(A2)仮基板上にめっきレジストを形成
し、めっきにより所定の導体パターンを形成し、めっき
レジストを除去し、 (B2)導通とは異なる機能を有する薄層を形成し、 (C2)仮基板を、導通とは異なる機能を有する薄層が
形成された面が内側にくるようにして絶縁基材と重ね合
せ一体化した後、仮基板を除去し、 (D2)露出した導体パターンおよび導通とは異なる機
能を有する薄層の上にエッチングレジストを形成し、エ
ッチングにより機能素子を構成する箇所以外の薄層を除
去し、エッチングレジストを除去することを含む機能素
子を有する配線板の製造法。
2. (A2) A plating resist is formed on a temporary substrate, a predetermined conductor pattern is formed by plating, the plating resist is removed, and (B2) a thin layer having a function different from conduction is formed. (C2) The temporary substrate was laminated and integrated with the insulating base material so that the surface on which the thin layer having a function different from conduction was formed was inward, and then the temporary substrate was removed to expose (D2). Wiring having a functional element including forming an etching resist on a thin layer having a function different from that of the conductor pattern and conduction, removing the thin layer other than the portion constituting the functional element by etching, and removing the etching resist Board manufacturing method.
【請求項3】(A3)仮基板上に、導通とは別の機能を
有する薄層を形成し、 (B3)めっきレジストを形成し、めっきにより所定の
導体パターンを形成し、めっきレジストを除去し、 (C3)仮基板を、導体パターンの形成された面が内側
にくるようにして絶縁基板と重ね合せ一体化した後、仮
基板を除去し、 (D3)露出した導通とは別の機能を有する薄層上にエ
ッチングレジストを形成し、エッチングにより機能素子
を構成する箇所以外の薄層を除去し、エッチングレジス
トを除去することを含む機能素子を有する配線板の製造
法。
(A3) A thin layer having a function different from conduction is formed on a temporary substrate, (B3) a plating resist is formed, a predetermined conductor pattern is formed by plating, and the plating resist is removed. Then, (C3) the temporary substrate is superposed and integrated with the insulating substrate so that the surface on which the conductor pattern is formed faces inward, and then the temporary substrate is removed, and (D3) a function different from the exposed conduction. A method for manufacturing a wiring board having a functional element, comprising: forming an etching resist on the thin layer having the functional element; removing the thin layer other than a portion constituting the functional element by etching; and removing the etching resist.
【請求項4】(A4)仮基板上に導体薄層を形成し、 (B4)導通とは異なる機能を有する所定パターンの薄
層を形成し、 (C4)仮基板を、導通とは異なる機能を有する所定パ
ターンの薄層が形成された面が内側にくるようにして絶
縁基板と重ね合せ一体化した後、仮基板を除去し、 (D4)めっきレジストを形成し、めっきにより所定の
導体パターンを形成し、めっきレジストを除去し、 (E4)導体パターンが形成されている箇所以外の導体
薄層を除去することを含む機能素子を有する配線板の製
造法。
4. (A4) forming a thin conductor layer on a temporary substrate, (B4) forming a thin layer having a predetermined pattern having a function different from conduction, and (C4) forming a temporary substrate having a function different from conduction. After the superposed and integrated with the insulating substrate so that the surface on which the thin layer having the predetermined pattern is formed is on the inside, the temporary substrate is removed, (D4) a plating resist is formed, and the predetermined conductive pattern is formed by plating. And removing the plating resist, and (E4) removing a thin conductor layer other than the portion where the conductor pattern is formed.
JP3219852A 1991-08-30 1991-08-30 Manufacture of wiring board provided with functional element Pending JPH0563340A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3219852A JPH0563340A (en) 1991-08-30 1991-08-30 Manufacture of wiring board provided with functional element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3219852A JPH0563340A (en) 1991-08-30 1991-08-30 Manufacture of wiring board provided with functional element

Publications (1)

Publication Number Publication Date
JPH0563340A true JPH0563340A (en) 1993-03-12

Family

ID=16742075

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3219852A Pending JPH0563340A (en) 1991-08-30 1991-08-30 Manufacture of wiring board provided with functional element

Country Status (1)

Country Link
JP (1) JPH0563340A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030090383A (en) * 2002-05-23 2003-11-28 한국과학기술원 Manufacturing method of PCB and PCB using of thereof
KR20040017478A (en) * 2002-08-21 2004-02-27 한국과학기술원 Manufacturing Method for Printed Circuit Board and Multiple PCB
JP2006253710A (en) * 2006-05-08 2006-09-21 Matsushita Electric Works Ltd Printed wiring board and method for manufacturing the same
KR101437988B1 (en) * 2008-04-24 2014-09-05 엘지전자 주식회사 Printed circuit board and method for manufacturing the same
EP3553800A4 (en) * 2016-12-07 2020-05-06 Nitto Denko Corporation Method for producing module

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030090383A (en) * 2002-05-23 2003-11-28 한국과학기술원 Manufacturing method of PCB and PCB using of thereof
KR20040017478A (en) * 2002-08-21 2004-02-27 한국과학기술원 Manufacturing Method for Printed Circuit Board and Multiple PCB
JP2006253710A (en) * 2006-05-08 2006-09-21 Matsushita Electric Works Ltd Printed wiring board and method for manufacturing the same
KR101437988B1 (en) * 2008-04-24 2014-09-05 엘지전자 주식회사 Printed circuit board and method for manufacturing the same
EP3553800A4 (en) * 2016-12-07 2020-05-06 Nitto Denko Corporation Method for producing module
US11387040B2 (en) 2016-12-07 2022-07-12 Nitto Denko Corporation Producing method of module

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