JP2002124765A - Manufacturing method for printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method for printed wiring board with which the connection reliability of a via hole based on a build-up method is improved. SOLUTION: After a semi-through hole 4 is formed on an insulating layer 3 built up on a core substrate 50, a base metal layer 5 of Cu or the like is covered by sputtering or electroless plating. On the surface of such a base metal layer 5, a water-repellent film 6 is formed by first plasma gas treatment using fluorine gases. Next, after the water-repellent film 6 is removed except for the semi-through hole by second plasma gas treatment using oxygen gases or the like by a dry mask 8, a plating resist pattern 9a is patterned. Next, after the water-repellent film 6 of the semi-through hole is removed, the printed wiring board is produced by forming the via hole and a conductive circuit by plating and etching. The inflow of the plating resist to the semi-through hole 4 can be prevented by the water-repellent film 6, the resist is prevented from being remained in the semi-through hole 4, and plating depositing property can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a printed wiring board, and more particularly to a method for manufacturing a printed wiring board having via holes on its surface.

[0002]

2. Description of the Related Art A semi-through hole is formed in an insulating layer built up on a core base material such as a double-sided copper-clad substrate, a conductive layer is formed in the semi-through hole, and a via hole is formed. 2. Description of the Related Art A method of manufacturing a printed wiring board by a so-called build-up method for forming a multilayer circuit by connecting to a core circuit formed on a base material has been widely used.
In the build-up method, there is no need to previously bond a copper foil to the surface of the insulating layer as in the related art, and etching is performed in an etching step for forming a conductive circuit in order to directly form a conductive layer on the insulating layer surface by plating or the like. This is because a conductive circuit can be formed with high accuracy because the thickness of the conductive layer is small.

A technique for manufacturing a printed wiring board by this build-up method is disclosed in Japanese Patent Application Laid-Open No. 7-15139. A method of manufacturing a printed wiring board according to this technique will be described with reference to FIGS. 4 and 5 are cross-sectional views of the main parts of the substrate for explaining the order of the manufacturing process of the printed wiring board. First, a core circuit 2 is formed by etching a core substrate 1 of a double-sided copper clad board. Next, after building up the insulating layer 3 on the core substrate 1, a semi-through hole 4 reaching the core circuit 2 is formed (FIG. 4A).

Next, as shown in FIG. 4B, a base metal layer 5 is formed on the surface of the insulating layer including the semi-through hole 4. Next, a plating resist 9 is applied (FIG. 4C). At this time, the plating resist 9 flows into the inside of the semi-through hole 4 in which the base metal layer 5 is formed. Subsequently, exposure and development are performed.
As shown in (d), a plating resist pattern 9a is formed.

Next, as shown in FIG. 5E, plated copper 10 is formed on the underlying metal layer 5 not covered with the plating resist pattern 9a by electrolytic copper plating or the like. continue,
After the plating resist pattern 9a is peeled off as shown in FIG. 5F, the exposed underlying metal layer 5 is removed by quick etching as shown in FIG.
A printed wiring board having a zero and a conductive circuit 20 is manufactured.

[0006]

The printed wiring board by the above build-up method has the following problems. (1) In the developing step of forming the plating resist pattern 9a in FIG. 4D, the plating resist tends to remain in the semi-through hole. Symbol 11 indicates a resist residue remaining in the semi-through hole 4 during development. (2) Due to the resist residue 11, when the next plated copper 10 of FIG. 5E is formed, the throwing power of the plated copper 10 in the semi-through hole 4 is reduced. Therefore, FIG.
In the quick etching step (g), the via holes 30
Disconnection and voids are likely to occur. Reference numeral 12 indicates a broken portion generated in the via hole 30 by the quick etching. In particular, the smaller the via hole, the more likely it is for the via hole to break. (3) On the other hand, if too much emphasis is placed on the developability of the resist in the semi-through hole 4, the plating resist pattern 9a on the surface becomes excessively developed, and the plating resist is peeled off or the resist is thinned, so that stable patterning cannot be performed. There are drawbacks.

Accordingly, it is an object of the present invention to provide a method for manufacturing a printed wiring board by a build-up method, which solves the above-mentioned problems of the prior art.

[0008]

According to the method of manufacturing a printed wiring board of the present invention, a first conductive film is formed on a surface of an insulating substrate having at least a half-through hole formed on the surface thereof, including the inside of the hole. Forming a water-repellent film on the surface of the first conductive film by a first plasma gas treatment;
The hole is masked with a first photoresist film, and the water-repellent film on the first conductive film other than the hole is formed on the second conductive film.
Removing the first photoresist film, forming an inverse resist film pattern of a second photoresist film on the substrate after removing the first photoresist film, and performing the second plasma gas treatment. Removing the water-repellent film in the holes, forming a second conductive film on the exposed surface of the first conductive film on the substrate including the holes, and removing the second conductive film on the substrate. Removing the reverse resist film pattern of the photoresist film, etching the first conductive film that is not covered with the second conductive film on the substrate, and removing the first conductive film on the substrate including the holes. Forming a conductive circuit having the first conductive film and the second conductive film.

As the insulating substrate, an epoxy resin substrate or a polyimide resin substrate is used, and the first conductive film is formed by vapor deposition (sputtering) or electroless plating.

The first plasma gas treatment includes C
Fluorine-based plasma gases such as F ₄ , C ₂ F ₆ , C ₃ F ₈ and CHF ₃ are used. By this processing, the water-repellent film is formed on the surface of the first conductive film. In the step of forming an inverse resist film pattern of a second photoresist film on the substrate, a liquid plating resist is repelled from the semi-through hole, and a residue of development of the second photoresist film into the semi-through hole. Occurrence can be prevented.

According to the present invention, it is possible to overcome the problem of the development residue in the via hole at the time of development, remarkably improve the plating coverage in the semi-through hole, and form a via hole with extremely high connection reliability.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a method for manufacturing a printed wiring board according to the present invention will be described in detail with reference to the drawings. 1 to 3 are cross-sectional views of a main part of a substrate shown in the order of steps for explaining a method of manufacturing a printed wiring board according to the present invention. First, as shown in FIG. 1A, a double-sided or single-sided copper-clad board is etched to prepare a core substrate 50 having a core circuit 2. For example, the core circuit 2 is formed by laminating a dry film on a double-sided or single-sided copper-clad board, exposing and developing a desired circuit forming portion using a light-shielded mask, and etching with a cupric chloride aqueous solution or the like. Is done. In the drawings, reference numeral 1 denotes a core substrate made of an epoxy resin or a polyimide resin and reinforced with glass fibers or the like.

A thermosetting or photosensitive insulating layer 3 made of an epoxy resin or a polyimide resin is coated on both surfaces or one surface of the core substrate 50 with a curtain coater, screen printing, spin coater, slot coater, etc. After the coating, the semi-through hole 4 is formed in the insulating layer 3 by photolithography (in the case of a photosensitive insulating layer) or laser processing (in the case of a thermosetting insulating layer). For example, in the case of a photosensitive insulating layer, the photosensitive insulating layer 3 is dried at 400 mJ / c after touch drying.
Exposure at m ^2, development with a developer containing diethanolamine (liquid temperature: 30 ° C.), and thermosetting at 160 ° C. for 60 minutes to form the semi-through hole 4.

Next, a base metal layer 5 is further formed on the surface of the insulating layer 3 (FIG. 1B). For example, the degree of vacuum is 1.6 × 10
A titanium (base film) / copper sputtered thin film is formed to a thickness of about 300 nm at a current value of 4 A at ^-4 Pa. The base metal layer 5 can be formed by electroless plating such as electroless copper plating or electroless nickel plating. In this case, the surface of the insulating layer 3 can be roughened with an aqueous alkaline permanganate solution to improve the adhesion of electroless plating.

Next, a plasma treatment is performed using a fluorine-based gas to impart water repellency to the surface of the base metal layer 5. Reference numeral 6 denotes a water-repellent film 6 (FIG. 1C). The water-repellent film 6 is C
It is a film containing u, C, and F.

As the fluorine-based gas, CF ₄ , C ₂ F ₆ ,
Gases such as C ₃ F ₈ and CHF ₃ can be used. For example, using CF ₄ gas, output 500 W, processing time 10 minutes, gas pressure 9
Plasma treatment is performed at 00 mTorr.

Next, after laminating the photosensitive dry film 7 (FIG. 1 (d)), it is exposed and developed to form a dry film mask 8 in the semi-through hole 4 (FIG. 2).
(E)).

Next, a plasma treatment using a gas other than fluorine, such as oxygen or argon, is performed to remove the water-repellent film 6 other than the semi-through hole 4 (FIG. 2 (f)). For example, plasma processing is performed using oxygen gas at an output of 500 W, a processing time of 5 minutes, and a gas pressure of 900 mTorr.

After the dry film mask 8 is further removed, a plating resist 9 for electroplating is applied. The plating resist 9 is a curtain coater, screen printing,
A film having a thickness of 20 μm is applied by a spin coater, a slot coater or the like, for example, and a touch drying is performed at 90 ° C. for 30 minutes (FIG. 2 (g)). At this time, the plating resist inside the semi-through hole having the water-repellent film is repelled (FIG. 2).
(G)).

Next, after exposing using a desired mask,
Development is performed to form a reverse-plate-shaped plating resist pattern 9a (FIG. 2 (h)). Note that the plating resist 9 can also be formed by an electrodeposition method. In this case, the plating resist is not electrodeposited because the water-repellent film 6 exists on the surface of the base metal layer 5 in the semi-through hole.

Next, using a gas other than a fluorine-based gas, for example, oxygen gas, output 500 W, processing time 5 minutes, gas pressure 90
Plasma treatment using plasma treatment is performed at 0 mTorr to remove the water-repellent film 6 in the semi-through hole. The surface of the semi-through hole becomes hydrophilic because the underlying metal layer 5 is exposed (FIG. 3 (i)).

Next, the plated copper 10 is patterned by electroplating or electroless plating (FIG. 3).
(J)). For example, when using electrolytic copper plating,
A plating solution having a copper concentration of 75 g / L and a brightener concentration of 2 mL / L, and plating copper 10 at a current density of 2 A / dm ² for 10 to 20
Coat to a thickness of μm.

Next, the plating resist is peeled off (FIG. 3).
(K)), the underlying metal layer 5 that is exposed without being covered with the plated copper 10 is removed by etching, and the via hole 3 is removed.
0 and the conductive circuit 20 are formed to manufacture a printed wiring board (FIG. 3 (l)). For example, when the base metal layer is formed by sputtering titanium and copper, first, the film hydrogen peroxide is formed.
It is immersed in a solution of 3 g / L and sulfuric acid of 80 g / L for 20 seconds to etch copper. Further, 4 g of a sulfate compound at 50 g / L
Immerse for 5 seconds and etch titanium.

In the above embodiment of the present invention, the case where one insulating layer is built up on the core substrate 50 has been described, but the surface of the substrate on which the via holes 30 and the conductive circuits 20 are formed is formed as described above. It goes without saying that the insulating layer can be further built up by the method to form via holes and conductive circuits.

[0025]

As described above, according to the present invention, the following effects can be obtained. (1) The surface of the underlying metal layer on the insulating layer including the semi-through hole is subjected to plasma treatment with a fluorine-based gas to form a water-repellent film, and the water-repellent film is selectively left in the semi-through hole. Thus, it is possible to prevent the plating resist from flowing into the semi-through hole and the occurrence of the undeveloped portion. (2) As a result, the electroplating property of the semi-through hole is improved, and the connection reliability of the via hole is improved. The effect is particularly remarkable in a via hole having a very small diameter, a via hole connecting two layers of high aspect ratio, and a through hole substrate having a very small diameter.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a main part of a substrate shown in the order of steps for describing an embodiment of a method of manufacturing a printed wiring board according to the present invention.

FIG. 2 is a cross-sectional view of the essential part of the substrate, following FIG. 1 (d), for explaining the embodiment of the method of manufacturing a printed wiring board according to the present invention in the order of steps;

FIG. 3 is a cross-sectional view of the essential parts of the substrate, following FIG. 2 (h), for explaining the embodiment of the method of manufacturing a printed wiring board according to the present invention in the order of steps;

FIG. 4 is a cross-sectional view of a main part of a substrate shown in the order of steps for describing an embodiment of a conventional method of manufacturing a printed wiring board.

FIG. 5 is a cross-sectional view of the essential part of the substrate, following FIG. 4 (d), for explaining the embodiment of the method of manufacturing a printed wiring board according to the present invention in the order of steps;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 core base material 2 core circuit 3 insulating layer 4 semi-through hole 5 base metal layer 6 water repellent film 7 dry film 8 dry film mask 9 plating resist 9a plating resist pattern 10 plated copper 11 resist residue 12 disconnection part 20 conductive circuit 30 via hole

Claims (15)

[Claims] A step of forming a first conductive film on a surface of the insulating substrate having at least a half-through hole formed in the surface thereof, the first conductive film being formed by a first plasma gas treatment; Forming a water-repellent film on the conductive film surface;
The hole is masked with a first photoresist film, and the water-repellent film on the first conductive film other than the hole is formed on the second conductive film.
Removing the first photoresist film, forming an inverse resist film pattern of a second photoresist film on the substrate after removing the first photoresist film, and performing the second plasma gas treatment. Removing the water-repellent film in the hole, forming a second conductive film on an exposed surface of the first conductive film on the substrate including the hole, and removing the second conductive film on the substrate. Removing the reverse resist film pattern of the photoresist film, etching the first conductive film that is not covered with the second conductive film on the substrate, and removing the first conductive film on the substrate including the holes. Forming a conductive circuit having the first conductive film and the second conductive film. 2. The method for manufacturing a printed wiring board according to claim 1, wherein said water-repellent film contains Cu, C and F. 3. The method according to claim 1, wherein the insulating substrate is an organic resin substrate. 4. The method according to claim 3, wherein the organic resin substrate is an epoxy resin substrate or a polyimide resin substrate. 5. The method for manufacturing a printed wiring board according to claim 1, wherein said first conductive film is formed by vapor deposition or electroless plating. 6. The method according to claim 1, wherein the first plasma gas treatment is performed using a fluorine-based plasma gas. 7. The fluorine-based plasma gas as C
_{F 4, C 2 F 6,} C 3 F 8, a manufacturing method of the printed wiring board according to claim 6, wherein the use of a gas selected from the CHF _3. 8. The method for manufacturing a printed wiring board according to claim 1, wherein a dry film type photoresist film is used as said first photoresist film. 9. The method according to claim 1, wherein the second plasma gas treatment and the third plasma gas treatment are performed using oxygen or argon gas. 10. The method according to claim 1, wherein the second photoresist film is formed by an electrodeposition method, a curtain method, or a spin coating method. 11. The method for manufacturing a printed wiring board according to claim 1, wherein said second conductive film is formed by electroless plating or electroplating. 12. The method according to claim 12, further comprising:
2. The method according to claim 1, wherein a conductive circuit is formed by the conductive film. 13. The method according to claim 1, wherein the first conductive film is made of Cu or Ni. 14. The method for manufacturing a printed wiring board according to claim 1, wherein said second conductive film is Cu. 15. A method for manufacturing a printed wiring board, wherein the first conductive film formed by the vapor deposition according to claim 5 is a multilayer film of a Ti base film and Cu.