JPH08204339A - Manufacture of printed wiring board - Google Patents
Manufacture of printed wiring boardInfo
- Publication number
- JPH08204339A JPH08204339A JP1315095A JP1315095A JPH08204339A JP H08204339 A JPH08204339 A JP H08204339A JP 1315095 A JP1315095 A JP 1315095A JP 1315095 A JP1315095 A JP 1315095A JP H08204339 A JPH08204339 A JP H08204339A
- Authority
- JP
- Japan
- Prior art keywords
- copper
- hole
- forming
- insulating layer
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は印刷配線板の製造方法に
関し、特に高密度配線パターンを形成する為のブライン
ドビアホールを有するビルドアップ工法による印刷配線
板の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board, and more particularly to a method for manufacturing a printed wiring board by a build-up method having blind via holes for forming a high density wiring pattern.
【０００２】[0002]
【従来の技術】一般にスルーホールを形成する印刷配線
板（以下、Ｔ／Ｈ ＰＷＢと称す）の製造方法には、テ
ンティング工法，パターンめっき工法及びアディティブ
工法，ビルドアップ工法があり、既に公知である特開平
３−２７５８７号公報には、ビルドアップ工法によるブ
ラインドビアホール形成に無電解銅を使用しないダイレ
クトめっき法とその技術が公開されている。これは、ま
ず図５（ａ）に示す様に、銅張り多層絶縁基板１に所望
の配線回路形成を行った後、図５（ｂ）に示す様に、絶
縁層形成の為の感光性硬化型エポキシ樹脂２を塗布し、
続いて、図５（ｃ）に示す様に、現像，露光を経て所望
の位置の感光性エポキシ樹脂２を除去し絶縁層３を形成
する。次に、図５（ｄ）に示す様に、クロム酸−硫酸混
液からなる酸性エッチング液でめっき皮膜から成る導体
層との密着性を向上させる為絶縁層５の粗化を行う。続
いて、図５（ｅ）に示す様に、銅張り多層基板１の表裏
導通を得るためのスルーホール用の貫通穴の穴開けを所
望の位置に行った後、図６（ａ）に示すように、銅張り
多層基板１の表裏全体に陽イオンあるいは陰イオン性の
高分子電解質溶液に浸漬処理し、続いて貴金属コロイド
あるいは非貴金属コロイド溶液に浸漬し高分子導電性金
属皮膜１７を形成しスルーホール６，ブラインドビアホ
ール１４を得る。ここで用いられる高分子電解質には、
アクリルアミド及β−メタクリルオキシエチルトリメチ
ル硫酸メチルアンモニウム共重合体あるいは、過フッ化
アクリルスルホン酸カリウム等で又、金属コロイド溶液
は、貴金属コロイドとして白金，パラジウム，ロジウム
溶液等、非貴金属コロイドとしては銅コロイド溶液があ
る。2. Description of the Related Art Generally, there are a tenting method, a pattern plating method, an additive method, and a build-up method as a method of manufacturing a printed wiring board (hereinafter referred to as T / H PWB) which forms through holes. JP-A-3-27587 discloses a direct plating method that does not use electroless copper for forming a blind via hole by a build-up method and its technique. First, as shown in FIG. 5 (a), a desired wiring circuit is formed on the copper-clad multilayer insulating substrate 1, and then, as shown in FIG. 5 (b), photosensitive curing for forming an insulating layer is performed. Type epoxy resin 2 is applied,
Subsequently, as shown in FIG. 5C, the photosensitive epoxy resin 2 at a desired position is removed through development and exposure to form an insulating layer 3. Next, as shown in FIG. 5D, the insulating layer 5 is roughened with an acidic etching solution containing a chromic acid-sulfuric acid mixed solution in order to improve the adhesion to the conductor layer formed of the plating film. Subsequently, as shown in FIG. 5 (e), through holes for through holes for obtaining front / back conduction of the copper-clad multilayer substrate 1 are drilled at desired positions, and then shown in FIG. 6 (a). As described above, the entire surface of the copper-clad multilayer substrate 1 is immersed in a cationic or anionic polyelectrolyte solution, and then immersed in a noble metal colloid or a non-noble metal colloid solution to form a polymer conductive metal film 17. Through holes 6 and blind via holes 14 are obtained. The polymer electrolyte used here includes
Acrylamide and β-methacryloxyethyl trimethyl methylsulfate copolymer or potassium perfluorinated acrylic sulfonate, etc. Also, metal colloid solutions are platinum, palladium, rhodium solutions etc. as noble metal colloids, copper colloids as non-noble metal colloid There is a solution.
【０００３】更に、図６（ｂ）に示す様に、めっきレジ
スト形成用の３５〜５０μｍ厚の耐めっき性アルカリ可
溶型ドライフィルム８を銅張り多層基板１の表裏全体に
ラミネートし、配線回路形成部とスルーホール６とブラ
インドビアホール１２とそのランド形成部及び表面実装
用パッド形成部のめっきレジスト形成用マスクフィルム
９を介して露光し、図６（ｃ）に示す様に、めっきレジ
スト１０となる部分のドライフィルムを硬化させ続いて
未露光部分のドライフィルムをＮａ2 ＣＯ3 の現像液で
除去し、全ての配線回路形成部とスルーホール６とブラ
インドビアホール１２とそのランド形成部及び表面実装
用パッド形成部以外の箇所にめっきレジスト１０を形成
する。その後、図６（ｄ）に示す様に、硫酸溶液でスル
ーホール６内の内層銅箔部５上の高分子導電性金属皮膜
１７を除去し、酸性電解銅めっき液で銅張多層基板１表
裏，スルーホール６とブラインドビアホール１２に銅め
っき１４を施し、表裏導通及び表裏面の導体層１５を形
成する。続いて、図７に示す様に、露出しためっきレジ
スト１０を剥離除去してＴ／ＨＰＷＢを得るものであ
る。Further, as shown in FIG. 6B, a plating resistant alkali-soluble dry film 8 having a thickness of 35 to 50 μm for forming a plating resist is laminated on the entire front and back surfaces of the copper-clad multilayer substrate 1 to form a wiring circuit. The formation portion, the through hole 6, the blind via hole 12, and the land forming portion and the surface mounting pad forming portion are exposed through the plating resist forming mask film 9, and as shown in FIG. Then, the dry film in the unexposed portion is cured, and then the dry film in the unexposed portion is removed with a developer of Na 2 CO 3 , and all wiring circuit forming portions, through holes 6, blind via holes 12, their land forming portions, and surface mounting. The plating resist 10 is formed in a place other than the pad forming portion. Thereafter, as shown in FIG. 6 (d), the polymer conductive metal film 17 on the inner layer copper foil portion 5 in the through hole 6 is removed with a sulfuric acid solution, and the copper-clad multilayer substrate 1 front and back surfaces with an acidic electrolytic copper plating solution. Copper plating 14 is applied to the through holes 6 and the blind via holes 12 to form front and back conduction and front and back conductor layers 15. Subsequently, as shown in FIG. 7, the exposed plating resist 10 is peeled and removed to obtain T / HPWB.
【０００４】[0004]
【発明が解決しようとする課題】しかし、高密度回路基
板の場合、従来工法では銅張り多層基板全面の導体化を
図るために用いられる高分子導電性金属皮膜が導電性金
属皮膜であり、回路形成後にめっきレジスト下の高分子
導電性金属皮膜を除去しない為、絶縁抵抗値による不良
率は３０％以上と大きく高密度回路での回路間絶縁性を
維持することが困難であるという問題があった。However, in the case of a high-density circuit board, in the conventional method, the polymer conductive metal film used to make the entire surface of the copper-clad multilayer board a conductor is a conductive metal film, Since the polymer conductive metal film under the plating resist is not removed after the formation, there is a problem that the defective rate due to the insulation resistance value is as large as 30% or more and it is difficult to maintain the inter-circuit insulation property in the high density circuit. It was
【０００５】また、従来工法では、スルーホール内外の
導体化を図る為高分子導電性金属皮膜を穴内に施すが銅
張り多層基板の場合、内層接続部銅上の密着性を向上さ
せるために硫酸で高分子導電性金属皮膜を除去するが、
この時、内層銅箔部も同時にエッチングされるので後の
電気銅めっきを行っても、スルーホールに欠陥が生じる
という問題があった。Further, in the conventional method, a polymer conductive metal film is applied to the inside of the through hole in order to make the inside and outside of the through hole a conductor, but in the case of a copper-clad multilayer substrate, sulfuric acid is used to improve the adhesion on the inner layer connecting portion copper. Remove the polymer conductive metal film with
At this time, since the inner layer copper foil portion is also etched at the same time, there is a problem that a defect occurs in the through hole even if the subsequent electrolytic copper plating is performed.
【０００６】さらに貴金属類のコロイド溶液あるいは非
貴金属の錯体を使用する高分子導電性金属皮膜である
為、ランニングコストが高いという問題もあった。Further, since the polymer conductive metal film uses a colloidal solution of noble metals or a complex of non-noble metals, there is a problem that running cost is high.
【０００７】本発明の目的は、歩留りが高く安価なブラ
インドビアホールを有する高密度回路印刷配線板の製造
方法を提供することにある。An object of the present invention is to provide a method for manufacturing a high density circuit printed wiring board having a blind via hole which has a high yield and is inexpensive.
【０００８】[0008]
【課題を解決するための手段】本発明の印刷配線板の製
造方法は、銅張り多層絶縁基板の表裏両面に所定の配線
回路を形成する工程と、この配線回路が形成された前記
銅張り多層絶縁基板の表裏両面のブラインドビアホール
を形成する部分を残して感光性硬化型エポキシ樹脂また
は紫外線硬化型接着剤フィルムにより構成された絶縁層
を形成する工程と、前記銅張り多層絶縁基板の所定の位
置にスルーホール用の貫通穴を穴開けする工程と、アル
カリ性溶液を用いて前記絶縁層表面を粗化する工程と、
前記銅張り多層絶縁基板表面と前記貫通穴壁面に金属を
含有しない導電性皮膜を形成しスルーホールとブライン
ドビアホールを形成する工程と、前記銅張り多層絶縁基
板の表裏両面に耐めっき性アルカリ可溶ドライフィルム
をラミネートし露光，現像して前記配線回路，前記スル
ーホールと前記ブラインドビアホール及びそのランド，
表面実装用パッド以外の部分にめっきレジストを形成す
る工程と、前記配線回路，前記スルーホールと前記ブラ
インドビアホール及びそのランド，前記表面実装用パッ
ドの部分に電気銅めっきを施し銅めっき層を形成する工
程と、前記めっきレジストを溶解除去する工程と、露出
した前記絶縁層上の前記導電性皮膜を酸性エッチング液
で除去する工程とを有する。A method for manufacturing a printed wiring board according to the present invention comprises a step of forming predetermined wiring circuits on both front and back surfaces of a copper-clad multilayer insulating substrate, and the copper-clad multilayer board having the wiring circuits formed thereon. A step of forming an insulating layer composed of a photosensitive curable epoxy resin or an ultraviolet curable adhesive film, leaving portions for forming blind via holes on both sides of the insulating substrate, and a predetermined position of the copper-clad multilayer insulating substrate A step of forming a through hole for a through hole, a step of roughening the insulating layer surface using an alkaline solution,
A step of forming a through hole and a blind via hole by forming a conductive film containing no metal on the surface of the copper-clad multilayer insulating substrate and the wall surface of the through hole; and plating resistance alkali-soluble on both front and back surfaces of the copper-clad multilayer insulating substrate. The dry film is laminated, exposed, and developed to form the wiring circuit, the through hole, the blind via hole and the land thereof,
A step of forming a plating resist on a portion other than the surface mounting pad, and electrolytic copper plating is performed on the wiring circuit, the through hole, the blind via hole and its land, and the surface mounting pad to form a copper plating layer. The method includes a step, a step of dissolving and removing the plating resist, and a step of removing the exposed conductive film on the insulating layer with an acidic etching solution.
【０００９】[0009]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。Embodiments of the present invention will now be described with reference to the drawings.
【００１０】図１（ａ）〜（ｅ），図２（ａ）〜
（ｄ），図３（ａ）〜（ｂ）は本発明の第１の実施例を
説明する工程順に示した断面図である。本発明の第１の
実施例は、まず、図１（ａ）に示す様に、０．６〜３．
２ｍｍの銅張り多層絶縁基板１の表裏面に公知のテンテ
ィング工法にて所定の回路形成を行った後、図１（ｂ）
に示す様に感光性硬化型エポキシ樹脂２を塗布し、続い
て、図１（ｃ）に示す様にブラインドビアホール形成用
マスクフィルム４を介して露光，現像して、図１（ｄ）
に示す様に、ブラインドビアホールを形成する所定の位
置の感光性硬化型エポキシ樹脂２を除去し絶縁層３を形
成する。更に、図１（ｅ）に示す様に、銅張り多層絶縁
基板１の表裏導通を得るためのスルーホール穴開けを所
定の位置に行った後、１０〜３０ｇ／Ｌの過マンガン酸
カリウム及び１０〜２０ｇ／Ｌの水酸化ナトリウムから
なるアルカリ性溶液を用いて６０〜８０℃で３〜５分間
の処理を行い絶縁層３表面を粗化し銅めっき皮膜から成
る導電性皮膜との密着性を向上させると共に穴内及び絶
縁層３表面上に二酸化マンガンを形成した後、図２
（ａ）に示す様に、３０〜５０モル％のピロール溶液に
浸漬し、二酸化マンガンの酸化力を用いピロールをポリ
マー化させポリピロール誘導体からなる０．０５〜０．
５μｍの金属を含有しない導電性皮膜７を形成する。
尚、皮膜形成用導電性高分子モノマーとしては、ピロー
ル系化合物，アニリン系化合物，チオフェン系化合物，
フラン系化合物が使用できる。1 (a) to 1 (e) and 2 (a) to
3D and FIG. 3A to FIG. 3B are sectional views showing the first embodiment of the present invention in the order of steps. In the first embodiment of the present invention, first, as shown in FIG.
After forming a predetermined circuit on the front and back surfaces of the 2-mm copper-clad multilayer insulating substrate 1 by a known tenting method, FIG.
As shown in FIG. 1C, a photosensitive curable epoxy resin 2 is applied, and subsequently, as shown in FIG. 1C, it is exposed and developed through a blind via-hole forming mask film 4, and FIG.
As shown in FIG. 3, the photosensitive curing type epoxy resin 2 at a predetermined position where the blind via hole is formed is removed to form the insulating layer 3. Further, as shown in FIG. 1 (e), through holes were drilled at predetermined positions for obtaining conduction between the front and back of the copper-clad multilayer insulating substrate 1, and then 10 to 30 g / L of potassium permanganate and 10 were used. Treatment with an alkaline solution consisting of ˜20 g / L sodium hydroxide at 60 to 80 ° C. for 3 to 5 minutes to roughen the surface of the insulating layer 3 and improve the adhesion with the conductive coating composed of a copper plating coating. After forming manganese dioxide in the hole and on the surface of the insulating layer 3 together with FIG.
As shown in (a), it is immersed in a pyrrole solution of 30 to 50 mol% and the pyrrole is polymerized using the oxidizing power of manganese dioxide to form a polypyrrole derivative of 0.05 to 0.
A conductive film 7 of 5 μm containing no metal is formed.
As the conductive polymer monomer for forming a film, pyrrole compounds, aniline compounds, thiophene compounds,
Furan compounds can be used.
【００１１】さらに、図２（ｂ）に示す様に、銅張り多
層絶縁基板１表面全体に２５〜５０μｍ厚のめっきレジ
スト形成用の耐めっき性アルカリ可溶型ドライフィルム
８をラミネートし、ライン／スペース＝５０μｍ／５０
μｍの配線回路と直径０．２ｍｍ〜２．０ｍｍのスルー
ホール６と直径０．１ｍｍ〜０．４ｍｍブラインドビア
ホール１２とそのランド部及び表面実装用パッド部のめ
っきレジスト形成用マスクフィルム９を介して露光し、
図２（ｃ）に示す様に、めっきレジスト１０となる部分
の耐めっき性アルカリ可溶型ドライフィルムを硬化さ
せ、続いて、未露光部分の耐めっき性アルカリ可溶型ド
ライフィルムを１〜３ｗｔ％のＮａ2 ＣＯ3 等の現像液
で除去し、全ての配線回路部とスルーホール６とブライ
ンドビアホール１２とそのランド部及び表面実装用パッ
ド部以外の箇所にめっきレジスト１０を形成する。続い
て、図２（ｄ）に示す様に、硫酸銅６５〜８５ｇ／Ｌ，
硫酸１５０〜２００ｇ／Ｌ，塩素３０〜５０ｐｐｍから
なる電解銅めっき液で配線回路１１とスルーホール６，
ブライドビアホール１２とそのランド部及び表面実装用
パッド１３に１５〜３５μｍの銅めっきを施して銅めっ
き層１４を形成し、表裏導通及び表裏面の導体化を行
う。その後、図３（ａ）に示す様に、配線回路１１間の
絶縁を得る為にめっきレジスト１０を２〜５％ＮａＯＨ
等の溶液で除去した後、更に、図３（ｂ）に示す様に、
露出した絶縁層３表面上の導電性皮膜７をクロム酸−硫
酸混液で溶解除去し、第１の実施例による所定の配線回
路１１を有するＴ／Ｈ ＰＷＢが得られる。Further, as shown in FIG. 2 (b), a plating resistant alkali-soluble dry film 8 for forming a plating resist having a thickness of 25 to 50 μm is laminated on the entire surface of the copper-clad multilayer insulating substrate 1, and the line / Space = 50μm / 50
Via a wiring circuit of μm, a through hole 6 having a diameter of 0.2 mm to 2.0 mm, a blind via hole 12 having a diameter of 0.1 mm to 0.4 mm, and a plating resist forming mask film 9 of the land portion and the surface mounting pad portion. Exposed,
As shown in FIG. 2C, the plating-resistant alkali-soluble dry film in the portion to be the plating resist 10 is cured, and then 1 to 3 wt% of the plating-resistant alkali-soluble dry film in the unexposed portion is cured. % Of Na 2 CO 3 or the like, and the plating resist 10 is formed on all the wiring circuit parts, the through holes 6, the blind via holes 12, the land parts thereof, and the surface mounting pad parts. Subsequently, as shown in FIG. 2D, copper sulfate 65 to 85 g / L,
The wiring circuit 11 and the through holes 6 are formed by an electrolytic copper plating solution containing sulfuric acid 150 to 200 g / L and chlorine 30 to 50 ppm.
Bride via hole 12 and its land portion and surface mounting pad 13 are plated with copper having a thickness of 15 to 35 μm to form a copper plating layer 14, and conduction on the front and back surfaces and a conductor on the front and back surfaces are performed. After that, as shown in FIG. 3A, the plating resist 10 is coated with 2 to 5% NaOH to obtain insulation between the wiring circuits 11.
After removing with a solution such as, as shown in FIG.
The exposed conductive film 7 on the surface of the insulating layer 3 is dissolved and removed with a chromic acid-sulfuric acid mixed solution to obtain a T / H PWB having a predetermined wiring circuit 11 according to the first embodiment.
【００１２】図４は本発明の第２の実施例のブラインド
ビアホールを形成する方法を説明する断面図である。本
発明の第２の実施例は図４に示す様に、ブラインドビア
ホール形成の為の絶縁層形成方法が異なるのみでその他
の工程は第１の実施例と同じである。第２の実施例は、
第１の実施例において、図４に示す様に、図１（ａ）の
銅張り多層基板１の表裏両面に回路構成した後、予め所
定のブラインドビアホールとなる位置に直径０．１ｍｍ
〜０．４ｍｍの穴開けを行った２０μｍ〜３５μｍ厚の
紫外線硬化型接着剤フィルム１６をラミネートし、図１
（ｄ）に示す様に、絶縁層３を形成する。その後第１の
実施例と同様図１（ｅ）以降の工法を経て第２の実施に
よるＴ／Ｈ ＰＷＢを得る。第２の実施例は絶縁層形成
に紫外線硬化型接着剤フィルムを採用することにより第
１の実施例に比べ２０〜３０％の時間短縮が出来る。FIG. 4 is a sectional view for explaining a method of forming a blind via hole according to the second embodiment of the present invention. As shown in FIG. 4, the second embodiment of the present invention is the same as the first embodiment except for the insulating layer forming method for forming blind via holes. The second embodiment is
In the first embodiment, as shown in FIG. 4, after the circuits are formed on both front and back surfaces of the copper-clad multilayer substrate 1 of FIG. 1 (a), a diameter of 0.1 mm is provided in advance at a predetermined blind via hole position.
The UV curable adhesive film 16 having a thickness of 20 μm to 35 μm and having a hole of up to 0.4 mm is laminated, and FIG.
As shown in (d), the insulating layer 3 is formed. Then, similar to the first embodiment, the T / H PWB according to the second embodiment is obtained through the construction method shown in FIG. In the second embodiment, the time can be shortened by 20 to 30% compared with the first embodiment by using the ultraviolet curing adhesive film for forming the insulating layer.
【００１３】[0013]
【発明の効果】前述した様に本発明によれば、従来工法
に対して下記に列挙する効果がある。As described above, according to the present invention, the following effects can be obtained with respect to the conventional method.
【００１４】（１）導電性皮膜は、金属を含まない高分
子皮膜を用い、且つ導体層形成後に皮膜を完全に除去す
る工程を有するため、回路幅／間隙＝５０μｍ／５０μ
ｍのような高密度回路であっても回路間絶縁性は絶縁抵
抗＝１×１０12Ω以上を維持し絶縁抵抗に伴う不良率は
１％未満に抑えることが出来る。(1) Since the conductive film is a polymer film containing no metal and has a step of completely removing the film after forming the conductor layer, circuit width / gap = 50 μm / 50 μ
Even in a high-density circuit such as m, the insulation between circuits can maintain the insulation resistance of 1 × 10 12 Ω or more, and the defect rate due to the insulation resistance can be suppressed to less than 1%.
【００１５】（２）スルーホール内外の導体化を図る為
の導電性皮膜は金属上に付着形成されない為、内層銅箔
上の導電性皮膜の除去が不要であり、後の電気銅めっき
を行っても、スルーホール内に欠陥が生じるという問題
を回避できる。(2) Since the conductive film for forming a conductor inside and outside the through hole is not adhered and formed on the metal, it is not necessary to remove the conductive film on the inner copper foil, and the subsequent electrolytic copper plating is performed. However, it is possible to avoid the problem that defects occur in the through holes.
【００１６】（３）導電性皮膜は金属を用いない導電性
ポリマー皮膜である為、ランニングコストを２０〜５０
％低減することが可能である。(3) Since the conductive film is a conductive polymer film that does not use metal, the running cost is 20 to 50.
% Can be reduced.
【図１】（ａ）〜（ｅ）は本発明の第１の実施例を説明
する工程順に示した断面図である。FIGS. 1A to 1E are cross-sectional views illustrating a first embodiment of the present invention in the order of steps for explaining the same.
【図２】（ａ）〜（ｄ）は本発明の第１の実施例を説明
する工程順に示した断面図である。2 (a) to 2 (d) are sectional views showing the first embodiment of the present invention in process order.
【図３】（ａ）〜（ｂ）は本発明の第１の実施例を説明
する工程順に示した断面図である。3 (a) and 3 (b) are sectional views showing the first embodiment of the present invention in the order of steps.
【図４】本発明の第２の実施例の絶縁層形成方法を説明
する断面図である。FIG. 4 is a cross-sectional view illustrating a method of forming an insulating layer according to a second embodiment of the present invention.
【図５】（ａ）〜（ｅ）は従来の印刷配線板の製造方法
の一例を説明する工程順に示した断面図である。5A to 5E are cross-sectional views showing the order of steps for explaining an example of a conventional method for manufacturing a printed wiring board.
【図６】（ａ）〜（ｄ）は従来の印刷配線板の製造方法
の一例を説明する工程順に示した断面図である。6A to 6D are cross-sectional views showing the order of steps for explaining an example of a conventional method for manufacturing a printed wiring board.
【図７】従来の印刷配線板の製造方法の一例を説明する
断面図である。FIG. 7 is a cross-sectional view illustrating an example of a conventional method for manufacturing a printed wiring board.
１ 銅張り多層絶縁基板 ２ 感光性硬化型エポキシ樹脂 ３ 絶縁層 ４ ブラインドビアホール形成用マスクフィルム ５ 内層接続部 ６ スルーホール ７ 導電性皮膜 ８ 耐めっき性アルカリ可溶型ドライフィルム ９ めっきレジスト形成用マスクフィルム １０ めっきレジスト １１ 配線回路 １２ ブラインドビアホール １３ 表面実装用パッド １４ 銅めっき層 １５ 導体層 １６ 紫外線硬化型接着剤フィルム １７ 高分子導電性金属皮膜 1 Copper-clad Multilayer Insulation Board 2 Photosensitive Curing Epoxy Resin 3 Insulating Layer 4 Blind Via Hole Forming Mask Film 5 Inner Layer Connection 6 Through Hole 7 Conductive Film 8 Plating Resistant Alkali-Soluble Dry Film 9 Plating Resist Forming Mask Film 10 Plating resist 11 Wiring circuit 12 Blind via hole 13 Surface mounting pad 14 Copper plating layer 15 Conductor layer 16 UV curable adhesive film 17 Polymer conductive metal film
Claims (3)
配線回路を形成する工程と、この配線回路が形成された
前記銅張り多層絶縁基板の表裏両面のブラインドビアホ
ールを形成する部分を残して絶縁層を形成する工程と、
前記銅張り多層絶縁基板の所定の位置にスルーホール用
の貫通穴を穴開けする工程と、アルカリ性溶液を用いて
前記絶縁層表面を粗化する工程と、前記銅張り多層絶縁
基板表面と前記貫通穴壁面に金属を含有しない導電性皮
膜を形成しスルーホールとブラインドビアホールを形成
する工程と、前記銅張り多層絶縁基板の表裏両面に耐め
っき性アルカリ可溶ドライフィルムをラミネートし露
光，現像して前記配線回路，前記スルーホールと前記ブ
ラインドビアホール及びそのランド，表面実装用パッド
以外の部分にめっきレジストを形成する工程と、前記配
線回路，前記スルーホールと前記ブラインドビアホール
及びそのランド，前記表面実装用パッドの部分に電気銅
めっきを施し銅めっき層を形成する工程と、前記めっき
レジストを溶解除去する工程と、露出した前記絶縁層上
の前記導電性皮膜を酸性エッチング液で除去する工程と
を有することを特徴とする印刷配線板の製造方法。1. A step of forming a predetermined wiring circuit on both front and back surfaces of a copper-clad multilayer insulating substrate, and a portion for forming blind via holes on both front and back surfaces of the copper-clad multilayer insulating substrate on which the wiring circuit is formed are left. A step of forming an insulating layer,
A step of forming a through hole for a through hole at a predetermined position of the copper-clad multilayer insulating substrate, a step of roughening the insulating layer surface using an alkaline solution, the copper-clad multilayer insulating substrate surface and the through hole A process of forming a conductive film containing no metal on the hole wall surface to form a through hole and a blind via hole, and laminating a plating resistant alkali-soluble dry film on both sides of the copper-clad multilayer insulating substrate, exposing and developing A step of forming a plating resist on a portion other than the wiring circuit, the through hole, the blind via hole and the land thereof, and a surface mounting pad; and the wiring circuit, the through hole and the blind via hole and the land thereof, and the surface mounting The step of applying copper electroplating to the pad part to form a copper plating layer, and dissolving and removing the plating resist That step a method for producing a printed wiring board, characterized in that the conductive coating on the exposed the insulating layer and a step of removing by acid etching solution.
により構成されていることを特徴とする請求項１記載の
印刷配線板の製造方法。2. The method for manufacturing a printed wiring board according to claim 1, wherein the insulating layer is made of a photosensitive curable epoxy resin.
ムにより構成されていることを特徴とする請求項１記載
の印刷配線板の製造方法。3. The method for manufacturing a printed wiring board according to claim 1, wherein the insulating layer is composed of an ultraviolet curable adhesive film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1315095A JPH08204339A (en) | 1995-01-30 | 1995-01-30 | Manufacture of printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1315095A JPH08204339A (en) | 1995-01-30 | 1995-01-30 | Manufacture of printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08204339A true JPH08204339A (en) | 1996-08-09 |
Family
ID=11825146
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1315095A Pending JPH08204339A (en) | 1995-01-30 | 1995-01-30 | Manufacture of printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08204339A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6120670A (en) * | 1997-01-30 | 2000-09-19 | Nec Corporation | Method of fabricating a multi-layered printed wiring board |
| KR100797669B1 (en) * | 2006-06-16 | 2008-01-23 | 삼성전기주식회사 | Printed Circuit Board and Fabricating Method of the same |
| CN102548225A (en) * | 2012-02-13 | 2012-07-04 | 东莞森玛仕格里菲电路有限公司 | Manufacturing method for printed circuit board (PCB) |
| CN114286530A (en) * | 2022-01-05 | 2022-04-05 | 江西景旺精密电路有限公司 | HDI board layer increasing method and circuit board |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0327587A (en) * | 1989-05-08 | 1991-02-05 | Internatl Business Mach Corp <Ibm> | Direct electro-plating on wall surface of through hole and printed circuit board |
| JPH05287582A (en) * | 1992-04-13 | 1993-11-02 | Okuno Chem Ind Co Ltd | Method for directly forming electroplating layer on non-conductive material surface |
-
1995
- 1995-01-30 JP JP1315095A patent/JPH08204339A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0327587A (en) * | 1989-05-08 | 1991-02-05 | Internatl Business Mach Corp <Ibm> | Direct electro-plating on wall surface of through hole and printed circuit board |
| JPH05287582A (en) * | 1992-04-13 | 1993-11-02 | Okuno Chem Ind Co Ltd | Method for directly forming electroplating layer on non-conductive material surface |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6120670A (en) * | 1997-01-30 | 2000-09-19 | Nec Corporation | Method of fabricating a multi-layered printed wiring board |
| KR100797669B1 (en) * | 2006-06-16 | 2008-01-23 | 삼성전기주식회사 | Printed Circuit Board and Fabricating Method of the same |
| CN102548225A (en) * | 2012-02-13 | 2012-07-04 | 东莞森玛仕格里菲电路有限公司 | Manufacturing method for printed circuit board (PCB) |
| CN114286530A (en) * | 2022-01-05 | 2022-04-05 | 江西景旺精密电路有限公司 | HDI board layer increasing method and circuit board |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6638690B1 (en) | Method for producing multi-layer circuits | |
| JP3012590B2 (en) | Method for manufacturing multilayer printed wiring board | |
| JPH08204339A (en) | Manufacture of printed wiring board | |
| JPH1187865A (en) | Printed circuit board and its manufacture | |
| JPH10215072A (en) | Manufacture of multilayer printed wiring board | |
| JP3500977B2 (en) | Manufacturing method of double-sided circuit board | |
| JPH036880A (en) | Printed wiring board and manufacture thereof | |
| JP2003204138A (en) | Manufacturing method for printed wiring board | |
| JPH08186373A (en) | Manufacture of printed wiring board | |
| JPH077264A (en) | Manufacture of printed wiring board | |
| JPH07321461A (en) | Method for manufacturing printed wiring method | |
| JPH0964543A (en) | Production of multilayered flexible printed wiring board | |
| JPH06120640A (en) | Production of flexible printed wiring board | |
| KR20030073919A (en) | The fabrication method of multi-layer printed circuit board using single etching semi-additive process | |
| JPH1168308A (en) | Manufacture of wiring board | |
| JPH118465A (en) | Manufacture of printed wiring board through additive method | |
| JP2016127251A (en) | Printed-circuit board and method for manufacturing the same | |
| JP2000138443A (en) | Manufacture of conductor pattern | |
| JPS62156898A (en) | Manufacture of through-hole printed wiring board | |
| JPH09181422A (en) | Printed circuit board manufacturing method | |
| JPH05308194A (en) | Manufacture of multilayer printed wiring board | |
| JPS59155994A (en) | Method of producing printed circuit board | |
| JPH10224036A (en) | Build-up printed wiring board and its manufacturing method | |
| JPH10107447A (en) | Manufacture of multi-layered printed wiring board | |
| JPS6159891A (en) | Method of producing printed circuit board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19970513 |