JP2006049642A - Method of manufacturing double-sided interconnection tape carrier and tape carrier manufactured thereby - Google Patents
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Abstract
Description
本発明は、半導体チップを搭載するためのテープキャリアに関し、特にポリイミドテープの両面に銅配線層が形成されている両面配線テープキャリアの製造方法に関する。 The present invention relates to a tape carrier for mounting a semiconductor chip, and more particularly to a method for manufacturing a double-sided wiring tape carrier in which a copper wiring layer is formed on both sides of a polyimide tape.
近年の電子機器は、ますます小型化・軽量化・薄型化の傾向が進み、これに用いられる部品の高集積化が厳しく要求されている。従来から、ファインピッチに対応できる半導体パッケージとして、銅ポリイミドテープを使用したTCP(テープキャリアパッケージ)などが知られているが、昨今のパッケージの小型化とともに、ICの高周波化が加速され、これに伴い半導体を搭載する周辺部品にも高周波化が求められるようになってきた。こうした小型化・高周波化の要求によって、TCPにおいても配線密度向上と高周波特性の向上が必須となり、これらの要求をみたすものとして両面配線テープキャリアが望まれている。 In recent years, electronic devices have been increasingly reduced in size, weight, and thickness, and there is a strict demand for higher integration of components used in the electronic devices. Conventionally, TCP (tape carrier package) using copper polyimide tape is known as a semiconductor package that can cope with fine pitch, but with the recent miniaturization of packages, the higher frequency of ICs has been accelerated. Along with this, higher frequency has been demanded for peripheral components on which semiconductors are mounted. Due to such demands for miniaturization and high frequency, it is essential to improve wiring density and high frequency characteristics in TCP, and a double-sided wiring tape carrier is desired to meet these demands.
従来の両面配線テープキャリアの製造方法を図2に示す。従来の製造方法では、両面銅層付ポリイミドテープ101の片面に、フォトレジストを用いてビアマスク用の銅パターン102を形成したのち、該ビアマスクを用いて、炭酸ガスレーザーやArレーザーなど、あるいはポリイミドエッチングによって、ブラインドビア103を開孔する。その後、両面の電気的接続のための電気銅めっきの前処理として、ブラインドビア内面にPdやCなどの電気伝導物質による導電化層104を形成し、導電化処理を行う。次いで、電気銅めっきで導電化層の上に、銅めっき105を析出させ、層間接続を得る。最後にフォトレジストを用いた銅エッチングにより配線106を形成する。 A conventional method for manufacturing a double-sided wiring tape carrier is shown in FIG. In the conventional manufacturing method, a copper pattern 102 for a via mask is formed on one side of a polyimide tape 101 with a double-sided copper layer using a photoresist, and then a carbon dioxide gas laser, an Ar laser, or the like is etched using the via mask. As a result, the blind via 103 is opened. Thereafter, as a pretreatment of the copper electroplating for electrical connection on both sides, a conductive layer 104 made of an electrically conductive material such as Pd or C is formed on the inner surface of the blind via, and a conductive treatment is performed. Next, copper plating 105 is deposited on the conductive layer by electrolytic copper plating to obtain an interlayer connection. Finally, the wiring 106 is formed by copper etching using a photoresist.
しかしながら、上記従来の製造方法においては、導電化層104を形成した後に電気銅めっきで全面にめっきを析出させるため、出発材料の表面銅層の上にも銅めっきが析出し、表面銅層全体の膜厚が厚くなり、ファインパターンのエッチングが困難であるという問題があった。この問題を解消するために、出発材料の表面銅層の厚みを薄くするという方法もあるが、40μmピッチなどのファインパターンに対しては、表面銅層の厚みが8μm程度のものが要求されており、従来の製造方法では、層間接続めっきにおいて10μm以上の厚付けを必要とするため、ファインピッチに適した銅厚にすることが出来なかった。また、層間接続めっきの厚さを10μm以下に薄くすると、信頼性試験において、層間接続部にクラックが生じ信頼性が低下するという問題があった。 However, in the conventional manufacturing method, since the plating is deposited on the entire surface by electrolytic copper plating after the formation of the conductive layer 104, the copper plating is deposited on the surface copper layer of the starting material. As a result, there is a problem that it is difficult to etch a fine pattern. In order to solve this problem, there is a method of reducing the thickness of the surface copper layer as a starting material, but for a fine pattern such as a 40 μm pitch, a surface copper layer having a thickness of about 8 μm is required. In the conventional manufacturing method, the thickness of 10 μm or more is required in the interlayer connection plating, and thus it has been impossible to obtain a copper thickness suitable for a fine pitch. Further, when the thickness of the interlayer connection plating is reduced to 10 μm or less, there has been a problem that in the reliability test, a crack is generated in the interlayer connection portion and the reliability is lowered.
本発明は、上記の如き従来技術の問題点に鑑みてなされたものであり、その目的とするところは、ファインピッチパターンの形成に好適な両面配線テープキャリアの製造方法を提供することにある。 The present invention has been made in view of the problems of the prior art as described above, and an object of the present invention is to provide a method for manufacturing a double-sided wiring tape carrier suitable for forming a fine pitch pattern.
上記目的を達成するため、本発明による両面配線テープキャリアの製造方法は、接着剤を用いないで接合された銅層を両面に有するポリイミドフィルムの片面側あるいは両面側の銅層にフォトエッチングによりビア開孔用パターンを形成し、該パターンをマスクとしてアルカリ溶液によるポリイミドエッチングによりブラインドビアホールおよびスルーホールを形成した後、該ビアホールおよびスルーホールの内面を含む全面に導電化処理を施し、さらに銅めっきによる層間接続を行う前に前記ビアホールおよびスルーホール以外をレジストでマスキングすることを特徴とする。 In order to achieve the above object, a method for manufacturing a double-sided wiring tape carrier according to the present invention includes a via layer formed by photoetching on one or both sides of a polyimide film having a copper layer bonded on both sides without using an adhesive. After forming a pattern for opening and forming a blind via hole and a through hole by polyimide etching with an alkaline solution using the pattern as a mask, the entire surface including the inner surface of the via hole and the through hole is subjected to a conductive treatment, and further by copper plating Before the interlayer connection is performed, the portions other than the via hole and the through hole are masked with a resist.
また、本発明による両面配線テープキャリアの製造方法は、接着剤を用いないで接合された銅層を両面に有するポリイミドフィルムの片面あるいは両面の銅層にフォトエッチングによりビア開孔用パターンを形成し、該パターンをマスクとしてレーザーによりブラインドビアホールおよびスルーホールを形成した後、該ビアホールおよびスルーホールの内面を含む全面に導電化処理を施し、さらに銅めっきによる層間接続を行う前に前記ビアホールおよびスルーホール以外をレジストでマスキングすることを特徴とする。 Also, the method for manufacturing a double-sided wiring tape carrier according to the present invention includes forming a via opening pattern by photoetching on one or both sides of a polyimide film having a copper layer bonded on both sides without using an adhesive. After forming blind via holes and through holes by laser using the pattern as a mask, the entire surface including the inner surfaces of the via holes and through holes is subjected to conductive treatment, and before the interlayer connection by copper plating, the via holes and through holes are formed. Other than the above, the resist is masked with a resist.
本発明によれば、好ましくは、前記レーザーは、炭酸ガスレーザーあるいはアルゴンレーザーである。 According to the invention, preferably, the laser is a carbon dioxide laser or an argon laser.
本発明によるテープキャリアは、上記何れかの製造方法により製造される。 The tape carrier according to the present invention is manufactured by any one of the above manufacturing methods.
本発明の製造方法によれば、銅めっき工程において配線形成領域は、レジストでマスキングされているため銅厚が厚くならず、もとの銅厚のままであり、ファインピッチ形成に適した銅厚が保持されたまま層間接続が可能となる。また、層間接続のめっき厚さに影響されず、任意のファインピッチに適した表面銅層の厚さを維持することが可能であり、ファインパターンを容易に形成することができる。
また、本発明の製造方法によれば、銅めっき後にマスキング用レジストを剥離し、あらためて配線形成のためのレジスト形成・露光・現像・エッチング工程を経るようにしたから、ファインピッチ形成が可能となる。
According to the manufacturing method of the present invention, in the copper plating step, the wiring formation region is masked with a resist, so that the copper thickness is not increased, and the original copper thickness is maintained, and the copper thickness suitable for fine pitch formation. Interlayer connection is possible while maintaining. In addition, the thickness of the surface copper layer suitable for any fine pitch can be maintained without being affected by the plating thickness of the interlayer connection, and a fine pattern can be easily formed.
In addition, according to the manufacturing method of the present invention, the masking resist is peeled off after copper plating, and the resist formation / exposure / development / etching process for wiring formation is performed again, so that a fine pitch can be formed. .
以下、本発明を図1に基づいて説明する。まず、出発材料としてポリイミドテープ201の両面にNi-Cr合金などの金属をスパッタリングし、ポリイミド表面に金属層202を形成する。次いで、該ポリイミドテープに対し、前記金属層202を給電層に用いて銅めっき203を施し、両面を所定の銅めっき厚さに調整した両面銅層付きポリイミドテープ204を用意する。次に、該ポリイミドテープ204の両面にアルカリ現像型感光性レジストフィルム205をラミネートし、ビアマスク用パターンを露光した後、炭酸ナトリウム水溶液で現像を行う。次いで、現像によりパターニングされたレジストに対し、塩化銅エッチング液によりエッチングを行い、ビア開孔部の銅と下地金属層であるNi-Cr層を除去し、ビア開孔パターン206を形成する。次いで、両面のレジストを水酸化ナトリウム溶液によって剥離して、ビア開孔部のみポリイミドが露出したテープ207にする。次に、該ポリイミドテープ207をアルカリポリイミドエッチング液に浸し、ポリイミド層をエッチングして、ブラインドビア208を形成する。次いで、ブラインドビアホール内面を含む基板全面に、PdやCなどを用いて導電化処理を施す。この処理工程により後の電気銅めっきによる給電が可能となる。 Hereinafter, the present invention will be described with reference to FIG. First, a metal such as a Ni—Cr alloy is sputtered on both surfaces of the polyimide tape 201 as a starting material, and a metal layer 202 is formed on the polyimide surface. Next, a copper tape 203 is applied to the polyimide tape using the metal layer 202 as a power supply layer, and a double-sided copper tape with a double-sided copper layer 204 having a predetermined copper plating thickness is prepared. Next, an alkali development type photosensitive resist film 205 is laminated on both surfaces of the polyimide tape 204, the via mask pattern is exposed, and then developed with an aqueous sodium carbonate solution. Next, the resist patterned by development is etched with a copper chloride etchant to remove the copper in the via opening and the Ni—Cr layer as the underlying metal layer, thereby forming a via opening pattern 206. Next, the resist on both sides is peeled off with a sodium hydroxide solution to form a tape 207 in which polyimide is exposed only at the via opening. Next, the polyimide tape 207 is immersed in an alkali polyimide etching solution, and the polyimide layer is etched to form the blind via 208. Next, the entire surface of the substrate including the inner surface of the blind via hole is subjected to a conductive treatment using Pd, C, or the like. This processing step enables power supply by later electrolytic copper plating.
この導電化処理後、両面にアルカリ現像型感光性レジストをラミネートし、ビアホールパターンを露光したのち、炭酸ナトリウム溶液で現像し、ビアホールのみを開口し、それ以外をレジストでマスキングする。次いで、電気銅めっきにより、ビアホール内面のみに銅めっきを析出させ、両面の銅箔を電気的に接続する。該銅めっき工程では、配線形成領域はレジストでマスキングされているため、銅めっきが析出せず、銅厚はもとのままである。
次いで、該マスキング用レジストをアルカリで剥離し、再度両面にアルカリ現像型感光性レジストをラミネートし、所定の配線パターンを露光したのち、炭酸ナトリウム溶液で現像し、塩化銅エッチング液によりエッチングを行い、銅層203とNi-Cr金属層202を除去し、配線212の形成を完了させる。この際に銅厚はもとのままであるため、所望のピッチに適した銅厚のままであり、ファインピッチ対応を容易に行うことができる。
最後にレジストを除去し、両面配線テープキャリア213を得る。なお、必要に応じて該両面配線テープキャリアにNi/Auめっきや、ソルダーレジスト形成を行ってもよい。
After this conductive treatment, an alkali developing type photosensitive resist is laminated on both surfaces, and the via hole pattern is exposed, and then developed with a sodium carbonate solution, only the via hole is opened, and the others are masked with the resist. Next, copper plating is deposited only on the inner surface of the via hole by electrolytic copper plating, and the copper foils on both sides are electrically connected. In the copper plating process, since the wiring formation region is masked with a resist, copper plating does not deposit and the copper thickness remains unchanged.
Next, the masking resist is stripped with an alkali, and an alkali development type photosensitive resist is laminated on both sides again, after exposing a predetermined wiring pattern, developed with a sodium carbonate solution, etched with a copper chloride etchant, The copper layer 203 and the Ni—Cr metal layer 202 are removed, and the formation of the wiring 212 is completed. At this time, since the copper thickness remains unchanged, the copper thickness suitable for the desired pitch remains unchanged, and fine pitch correspondence can be easily performed.
Finally, the resist is removed to obtain a double-sided wiring tape carrier 213. If necessary, Ni / Au plating or solder resist formation may be performed on the double-sided wiring tape carrier.
以下、図1を参照して実施例を説明する。図1は本発明の一実施例であり、両面配線テープキャリアの各工程ごとの断面図を示すものである。まず、出発材料として50μm厚のポリイミドテープ201の両面にNi-Cr合金を約500Åの厚さにスパッタし、金属層202を形成した。さらに両面に銅めっきにより厚さ8μmの銅めっき層203を形成し、両面銅層付ポリイミドテープ204を用意した。次にこのポリイミドテープ204の両面にアルカリ現像型感光性レジストフィルム205(旭化成製:AQ-1558)をラミネートした後、150μmφのビアを開孔するマスクパターンを露光した後、1wt%炭酸ナトリウム水溶液を用い40℃で30秒間現像を行った。次いで、現像によりパターニングされたレジストに対し、10wt%塩化銅エッチング液により45℃×30秒間エッチングを行い、ビア開孔部上面の銅と下地のNi-Cr金属層を除去し、150μmφのビアマスク206を形成した。次に、両面のレジストを2wt%水酸化ナトリウム溶液により30℃×3分間処理してレジストの剥離を行ない、ビア開孔部のみポリイミドが露出したテープ207にした。このポリイミドテープ207を70℃のアルカリポリイミドエッチング液に2分間浸し、ポリイミド層をエッチングしブラインドビア208を形成した。 Hereinafter, an embodiment will be described with reference to FIG. FIG. 1 shows an embodiment of the present invention and shows a cross-sectional view of each process of a double-sided wiring tape carrier. First, a Ni—Cr alloy was sputtered to a thickness of about 500 mm on both surfaces of a 50 μm-thick polyimide tape 201 as a starting material to form a metal layer 202. Further, a copper plating layer 203 having a thickness of 8 μm was formed on both sides by copper plating, and a polyimide tape 204 with a double-sided copper layer was prepared. Next, after laminating an alkali-developable photosensitive resist film 205 (AQ-1558 manufactured by Asahi Kasei Co., Ltd.) on both surfaces of the polyimide tape 204, a mask pattern for opening a 150 μmφ via is exposed, and then a 1 wt% sodium carbonate aqueous solution is added. Development was performed at 40 ° C. for 30 seconds. Next, the resist patterned by development is etched with a 10 wt% copper chloride etchant at 45 ° C. for 30 seconds to remove the copper on the upper surface of the via opening and the underlying Ni—Cr metal layer, and the 150 μmφ via mask 206. Formed. Next, the resist on both sides was treated with a 2 wt% sodium hydroxide solution at 30 ° C. for 3 minutes to remove the resist, thereby forming a tape 207 in which polyimide was exposed only at the via opening. This polyimide tape 207 was immersed in an alkali polyimide etching solution at 70 ° C. for 2 minutes, and the polyimide layer was etched to form a blind via 208.
次いで、ブラインドビアホール側面および全面に導電化処理を施すため、アルカリ性脱脂液40℃×5分浸漬したのち、Sn-Pd溶液60℃×5分浸漬し、10%硫酸溶液にて酸洗して、導電化のためのPd吸着層を形成した。その後、両面にアルカリ現像型感光性レジスト(旭化成AQ-1558)をラミネートし、ビアホールのみ開口するようにパターン露光し、1%Na2CO3溶液30℃×30秒で現像した。
次いで、硫酸銅めっきによって層間接続を行うために、まず脱脂を40℃で1分間行った後、化学研磨(硫酸―過酸化水素水系)で室温で30秒間処理した。さらに、10%硫酸で酸洗を行い、前処理を完了させた。次いで、硫酸銅めっきを用いて、電気銅めっきを行い、Pd導電層の上に約10μmの銅めっきを析出させ、上下の導箔との接続を得た。該銅めっき工程では、層間接続部以外はレジストでマスキングされているため、後の配線形成面は銅めっきが析出せず、銅厚はもとのままである。次いで、マスキング用レジスト217を除去し、両面の接続がなされたテープ213を得た。
さらに、配線形成を行うため、再度両面にアルカリ現像型感光性レジスト(旭化成SPG-102)をラミネートし、40μmピッチのファインな配線用パターンを露光したのち、1wt%炭酸ナトリウム溶液で現像した。次に、10wt%塩化銅エッチング液によりエッチングを行い、銅層とNi-Cr金属層を除去し、配線212のパターン形成を完了した。最後に、レジストを2%NaOH溶液40℃×1分で剥離し、両面配線テープキャリアを得た。
Next, in order to conduct the conductive treatment on the side surface and the entire surface of the blind via hole, after immersion in an alkaline degreasing solution at 40 ° C. for 5 minutes, immersion in a Sn-Pd solution at 60 ° C. for 5 minutes, pickling with a 10% sulfuric acid solution, A Pd adsorption layer for electrical conduction was formed. Thereafter, an alkali-developable photosensitive resist (Asahi Kasei AQ-1558) was laminated on both sides, pattern exposure was performed so that only via holes were opened, and development was carried out at 30 ° C. for 30 seconds with a 1% Na 2 CO 3 solution.
Next, in order to perform interlayer connection by copper sulfate plating, first, degreasing was performed at 40 ° C. for 1 minute, and then chemical polishing (sulfuric acid-hydrogen peroxide system) was performed at room temperature for 30 seconds. Further, pickling with 10% sulfuric acid was performed to complete the pretreatment. Next, electrolytic copper plating was performed using copper sulfate plating to deposit about 10 μm of copper plating on the Pd conductive layer, and connection with the upper and lower conductive foils was obtained. In the copper plating step, since portions other than the interlayer connection portions are masked with resist, copper plating does not deposit on the subsequent wiring formation surface, and the copper thickness remains unchanged. Next, the masking resist 217 was removed to obtain a tape 213 with both sides connected.
Further, in order to form a wiring, an alkali development type photosensitive resist (Asahi Kasei SPG-102) was laminated again on both surfaces, and a fine wiring pattern with a pitch of 40 μm was exposed, and then developed with a 1 wt% sodium carbonate solution. Next, etching was performed with a 10 wt% copper chloride etching solution to remove the copper layer and the Ni—Cr metal layer, and the pattern formation of the wiring 212 was completed. Finally, the resist was peeled off at 2 ° C. for 1 minute at 40 ° C. to obtain a double-sided wiring tape carrier.
このようにして得た両面配線テープキャリアのファインパターン配線部の外観を観察した結果、配線間のショートもなく、配線形成は良好であった。また、層間接続部の断面観察からも、クラックや内部のボイド発生は見られず、得られたテープキャリアを260℃と室温のシリコーンオイルに交互に100サイクル浸漬させ、試験前後の抵抗値の変化率を測定した結果、試験前後の変化率は3%以内であり、十分な信頼性が確保された。 As a result of observing the appearance of the fine pattern wiring part of the double-sided wiring tape carrier thus obtained, there was no short circuit between the wirings, and the wiring formation was good. Also, from the cross-sectional observation of the interlayer connection, no cracks or internal voids were observed, and the obtained tape carrier was alternately immersed in silicone oil at 260 ° C. and room temperature for 100 cycles, and the resistance value before and after the test was changed. As a result of measuring the rate, the rate of change before and after the test was within 3%, and sufficient reliability was ensured.
201 ポリイミドフィルム
202 シード層
203 銅層
204 両面銅層付ポリイミドテープ
205 レジスト
206 ビアマスク
207 ビアマスクを形成したテープ
208 ポリイミドエッチングによるブラインドビア
212 配線
213 本発明の両面配線テープキャリア
201 Polyimide film
202 seed layer
203 copper layer
204 Polyimide tape with double-sided copper layer
205 resist
206 Via Mask
207 Tape with via mask
208 Blind via by polyimide etching
212 Wiring
213 Double-sided wiring tape carrier of the present invention
Claims (5)
A tape carrier manufactured by the manufacturing method according to claim 2.
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008270411A (en) * | 2007-04-18 | 2008-11-06 | Sumitomo Metal Mining Package Materials Co Ltd | Method of manufacturing double-sided wiring tape carrier and tape carrier manufactured thereby |
CN102403200A (en) * | 2011-11-29 | 2012-04-04 | 无锡中微晶园电子有限公司 | Method for realizing pattern with line width of 0.18[mu]m by double photoetching method for I line photoetching machine |
US20140313683A1 (en) * | 2011-11-09 | 2014-10-23 | Lg Innotek Co., Ltd. | Tape carrier package and method of manufacturing the same |
-
2004
- 2004-08-05 JP JP2004229781A patent/JP2006049642A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008270411A (en) * | 2007-04-18 | 2008-11-06 | Sumitomo Metal Mining Package Materials Co Ltd | Method of manufacturing double-sided wiring tape carrier and tape carrier manufactured thereby |
US20140313683A1 (en) * | 2011-11-09 | 2014-10-23 | Lg Innotek Co., Ltd. | Tape carrier package and method of manufacturing the same |
US9674955B2 (en) * | 2011-11-09 | 2017-06-06 | Lg Innotek Co., Ltd. | Tape carrier package, method of manufacturing the same and chip package |
CN102403200A (en) * | 2011-11-29 | 2012-04-04 | 无锡中微晶园电子有限公司 | Method for realizing pattern with line width of 0.18[mu]m by double photoetching method for I line photoetching machine |
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