JPS6285496A - Manufacture of printed circuit board - Google Patents
Manufacture of printed circuit boardInfo
- Publication number
- JPS6285496A JPS6285496A JP22650285A JP22650285A JPS6285496A JP S6285496 A JPS6285496 A JP S6285496A JP 22650285 A JP22650285 A JP 22650285A JP 22650285 A JP22650285 A JP 22650285A JP S6285496 A JPS6285496 A JP S6285496A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- resistor
- conductor layer
- conductor
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は回路基板の製造方法、特に抵抗体を備え、多
層、高密度な回路基板の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a circuit board, and particularly to a method for manufacturing a multilayer, high-density circuit board equipped with a resistor.
従来、この種の回路基板としては、アルミナセラミック
基板などの絶縁性＃４熱基板上に、厚膜導体ペース】・
、厚膜抵抗ペーストを印刷、焼成する厚膜形成技術を用
いて形成される厚膜混成集積回路基板、蒸着、スパッタ
リングなどの薄膜形成技術を用いて形成される薄膜混成
集積回路基板、厚膜、薄膜両者を組み合わせたものなど
が主として用いられてきた。Conventionally, this type of circuit board has a thick film conductor paste on an insulating #4 thermal substrate such as an alumina ceramic substrate.
, thick film hybrid integrated circuit boards formed using thick film forming techniques such as printing and firing thick film resistor paste, thin film hybrid integrated circuit boards formed using thin film forming techniques such as vapor deposition and sputtering, thick films, A combination of both thin films and the like has mainly been used.
薄膜混成集積回路基板は、高信頼性、高性能、微細パタ
ーン等が要求される分野、主として産業用電子機器など
に使用されており、厚膜混成集積回路基板に比べてコス
トは高くなる。Thin film hybrid integrated circuit boards are used in fields that require high reliability, high performance, fine patterns, etc., mainly in industrial electronic equipment, and are more expensive than thick film hybrid integrated circuit boards.
一方、厚膜混成集積回路基板は、民生用から産業用まで
殆どの分野で使用されている。On the other hand, thick film hybrid integrated circuit boards are used in most fields from consumer to industrial applications.
第２図は従来例の厚膜混成集積回路基板を示す断面図で
、図において、（１０１）は基板、例えばアルミナセラ
ミックで、（１０２）は厚膜導体による第１導体層、（
１０３）は厚膜抵抗体、（１０４）はクロスガラス層、
（１０５）は厚膜導体による第２導体層を示している。FIG. 2 is a cross-sectional view showing a conventional thick film hybrid integrated circuit board.
103) is a thick film resistor, (104) is a cross glass layer,
(105) indicates a second conductor layer made of a thick film conductor.
導体層には銀−パラジウム、白金−パラジウム、金など
の貴金属ペースト、抵抗体には酸化ルテニウムなどのサ
ーメット抵抗ペーストを用い、印刷、焼成によって形成
している。この貴金属ペーストは、価格が高く、これら
の汎用厚膜導体材料では導体シート抵抗値が２０〜１０
０μ和と高（、回路実装の信号伝送系に問題を生じると
いう問題点があった。また、主として用いられる銀は、
回路素子を半田付けする際に溶融半田中に溶解してしま
うパ半田喰われ”の問題があり、銀入り半田の使用、温
度管理など半田付はプロセスの慎重なコン１−ロールが
必要である。A noble metal paste such as silver-palladium, platinum-palladium, or gold is used for the conductor layer, and a cermet resistance paste such as ruthenium oxide is used for the resistor, and these are formed by printing and firing. This noble metal paste is expensive, and these general-purpose thick film conductor materials have conductor sheet resistance values of 20 to 10.
There was a problem that the sum of 0 μ and high (high) caused problems in the signal transmission system of circuit mounting.Also, the silver mainly used is
When soldering circuit elements, there is a problem of "solder eating" which occurs when the solder melts into the molten solder, so careful control of the soldering process is required, including the use of silver-containing solder and temperature control. .
さらに各層を厚膜で形成するため微細パターンの形成に
は１００〜２００μｍ巾迄との限界があり、部分的な多
層化、２〜３層の多層しかできなかった。Furthermore, since each layer is formed as a thick film, the formation of fine patterns is limited to a width of 100 to 200 μm, and only partial multilayering or multilayering of 2 to 3 layers can be achieved.
上記のような従来の回路基板では導体パターンの微細化
が難しく、かつ部分的な多層化しかできず、十分な高密
度化、高機能化が達成てきないという問題点があった。Conventional circuit boards as described above have problems in that it is difficult to miniaturize conductor patterns, and only partial multilayering is possible, making it impossible to achieve sufficient density and functionality.
この発明は上記のような問題点を解消するためになされ
たもので、基板上に抵抗体を有し、微細な導体パターン
が形成できるとともに導体層の多層化を行なうことによ
り、高密度、高機能な回路基板の製造方法を提供するこ
とを目的としている。。This invention was made to solve the above-mentioned problems. It has a resistor on a substrate, allows the formation of fine conductor patterns, and multi-layers conductor layers. The purpose is to provide a method for manufacturing a functional circuit board. .
この発明の回路基板の製造方法は、基板に抵抗体を形成
する工程、この抵抗体に接続して」−記基板に写真製版
法及びめっき法を用いて所定パターンの第１導体層を形
成する工程、第１導体層を形成した基板に写真製版法を
用いて所定パターンの絶縁性樹脂層を形成する工程、並
びに上記絶縁性樹脂層を形成した基板に写真製版法及び
めっき法を用いて所定パターンの第２導体層を形成する
工程を施すものである。The method for manufacturing a circuit board of the present invention includes a step of forming a resistor on a board, and forming a first conductor layer in a predetermined pattern on the board by using photolithography and plating. a step of forming an insulating resin layer with a predetermined pattern on the substrate on which the first conductor layer has been formed using photolithography; A step of forming a patterned second conductor layer is performed.
この発明による第１導体層は、絶縁性基板上に形成され
た抵抗体と接続して、めっきにより形成されるので、導
体と抵抗体の電気的接続が達成されるとともに、写真製
版法を用いてパターニングされるので微細な導体パター
ンが得られる。また、絶縁性樹脂層を部分的に除去して
貫通孔を設け、乙の部分にめっきにより導体層を形成し
ておけば第１導体層と第２導体層との電気的接続が達成
される。また、第２導体層は、めっきにより形成され、
写真製版法によりパターニングされるので、第１導体層
と同様に微細な導体パターンが得られる。さらに導体層
がめっきにより形成されるので多層化が容易になる。な
お、めっき金属として卑金属（例えば銅、ニッケルなど
）を用いれば″″半田喰われ″がなく半田付信頼性が向
上するとともに、抵抗も小さくできる。The first conductor layer according to the present invention is connected to a resistor formed on an insulating substrate and is formed by plating, so that an electrical connection between the conductor and the resistor is achieved, and a photolithography method is also used to achieve electrical connection between the conductor and the resistor. Since the conductor is patterned using the same method, a fine conductor pattern can be obtained. In addition, if the insulating resin layer is partially removed to provide a through hole and a conductor layer is formed by plating on the part B, electrical connection between the first conductor layer and the second conductor layer can be achieved. . Further, the second conductor layer is formed by plating,
Since it is patterned by photolithography, a fine conductor pattern can be obtained similarly to the first conductor layer. Furthermore, since the conductor layer is formed by plating, multilayering becomes easy. Note that if a base metal (for example, copper, nickel, etc.) is used as the plating metal, there will be no "solder bite", improving soldering reliability and reducing resistance.
以下、乙の発明の一実施例を図について工程順に説明す
る。Hereinafter, one embodiment of the invention of B will be explained in order of steps with reference to the drawings.
第１図（ａ）〜（ｆ）の断面図において（１）は基板で
、この場合は絶縁性のアルミナセラミック基板、（２）
はアルミナセラミック基板（１）上に形成された抵抗体
で、この場合は酸化ルテニウム系厚膜抵抗体、（３）は
アルミナセラミック基板（１）上に酸化ルテニウム系厚
膜抵抗体（２）と接続するように形成された無電解めっ
きに対する触媒作用を有する活性化層、（４）は活性化
層（３）−ヒに第１導体層（５）が形成されるべき部分
のみを除いて形成された樹脂層で、この場合は感光性を
有するポリイミド前駆体を用いて形成されたポリイミド
層、（５）は活性化層（３）上でポリイミド層（４）の
存在しない部分のみに無電解めっきによって形成された
第１導体層、（６）は第１導体層（５）と第２導体層（
８）とを絶縁するための絶縁性Ｖｊ４脂層で、乙の場合
は感光性を有するポリイミド前駆体を用いて形成された
ポリイミド層、（７）は第１導体層（５）と第２導体層
（８）とを接続するためにポリイミド層（６）に形成さ
れた貫通孔、（８）は第１導体層（５）の露出部及び絶
縁性樹脂層（６）上に無電解めっき及び電気めっきによ
り形成された後、エツチングによりパターニングされた
第２導体層である。In the cross-sectional views of FIGS. 1(a) to (f), (1) is a substrate, in this case an insulating alumina ceramic substrate, (2)
is a resistor formed on an alumina ceramic substrate (1), in this case a ruthenium oxide thick film resistor, and (3) is a ruthenium oxide thick film resistor (2) formed on an alumina ceramic substrate (1). An activation layer (4) having a catalytic effect on electroless plating formed to connect is formed on the activation layer (3)-A except for only the portion where the first conductor layer (5) is to be formed. (5) is a polyimide layer formed using a photosensitive polyimide precursor, and (5) is an electroless resin layer formed only on the activation layer (3) where the polyimide layer (4) is not present. The first conductor layer (6) formed by plating is the first conductor layer (5) and the second conductor layer (
8) An insulating Vj4 resin layer for insulating the first conductor layer (5) and the second conductor layer (7) is a polyimide layer formed using a photosensitive polyimide precursor in the case of B. The through hole (8) formed in the polyimide layer (6) to connect the layer (8) is formed by electroless plating and on the exposed portion of the first conductor layer (5) and the insulating resin layer (6). The second conductor layer is formed by electroplating and then patterned by etching.
まずアルミナセラミック基板（１）上に酸化ルテニウム
系抵抗ペースト（図示せず）をスクリーン印刷し、ベル
ト炉を使用して最高温度８５０℃で焼成することにより
、酸化ルテニウム系厚膜抵抗体（２）を形成する。（第
１図ａ）
次にガラス粉末と無電解メッキに対する触媒作用を有す
るパラジウム金属粒子を主成分とするペースト（例えば
奥野製薬製（商標）キャタペース１− ＣＣＰ−３７３
０）を、酸化ルテニウム系厚膜抵抗体（２）と接触する
ようにスクリーン印刷し、焼成しく前記キャタペースト
ＣＣＰ−３７３０では最高温度６８０℃で焼成）活性化
層（３）を形成する。（第１図ｂ）次に、感光性を有す
るポリイミド前駆体（図示せず、例えば東し製（商標）
フォトニース）を抵抗体（２）上も含め塗布、乾燥し、
適当なマスクを用いて紫外線で露光する。その後、現像
液（フォｌ−ニースの場合Ｎメチル−２−ピロリドンと
メタノールを主成分とする）中で現像することにより、
露光されなかった部分のポリイミド前駆体が除去され、
引き続き加熱硬化（フォＩ・ニースの場合最高温度３５
０℃）する乙とにより、ポリイミド層（４）を形成する
。乙のようにして無電解メッキ工程中安定な樹脂層を、
活性化層（３）の第１導体層（５）が形成されるべき部
分を除き、写真製版法により形成する。（第１図Ｃ）
引き続きこの基板全体を無電解メッキ液に浸漬する。例
えば、無電解銅メッキ液マクダミット９０４８（商品名
、マクダミット社製）を６０℃に保持し、この中に浸漬
することにより、上記活性化層（３）が露出した部分の
みに銅メッキが析出し、第１導体層（５）が形成される
。この導体層パターンは写真製版によりパターニングが
行われており、微細なものである。（第１図ｄ）
次に感光性を有するポリイミド前駆体を基板上に塗布、
乾燥し、適当なマスクを用いて紫外線で露光する。その
後、現像液中で現像することにより、露光されなかった
部分のポリイミド前駆体が除去され、引き続き加熱硬化
することにより貫通孔（７）を有するポリイミド層（６
）が得られる。（第１図ｅ）
次に、この基板に無電解めっきを析出させるための活性
化処理を施し、引き続き無電解めっき浴に浸漬すること
により基板上全面にめっきが析出する。これに電気めっ
きを施した後、写真製版法を用いてレジスト層を形成し
、エツチングすることにより第２導体層（８）が得られ
る。（第１図ｆ）上記実施例では抵抗体として酸化ルテ
ニウム系厚膜抵抗体を用いた場合について述べたが、樹
脂中に導電性粒子を分散させて形成される樹脂抵抗体を
使用してもよい。First, a ruthenium oxide-based thick film resistor (2) is created by screen printing a ruthenium oxide-based resistance paste (not shown) on an alumina ceramic substrate (1) and firing it at a maximum temperature of 850°C using a belt furnace. form. (Figure 1a) Next, a paste containing glass powder and palladium metal particles as main components that have a catalytic effect on electroless plating (for example, Catapace 1-CCP-373 manufactured by Okuno Pharmaceutical Co., Ltd. (trademark))
0) is screen printed so as to be in contact with the ruthenium oxide thick film resistor (2), and fired at a maximum temperature of 680° C. for Catapaste CCP-3730) to form an activation layer (3). (Figure 1b) Next, a photosensitive polyimide precursor (not shown, such as Toshi Co., Ltd. (trademark))
Apply Photonice) on the resistor (2) as well, dry it,
Expose to UV light using a suitable mask. Then, by developing in a developer (in the case of Fol-Nice, the main components are N-methyl-2-pyrrolidone and methanol),
The polyimide precursor in the areas that were not exposed to light is removed,
Continue to heat cure (maximum temperature 35 for FoI/Nice)
0° C.) to form a polyimide layer (4). As shown in Part B, a stable resin layer is created during the electroless plating process.
The activation layer (3) is formed by photolithography except for the portion where the first conductor layer (5) is to be formed. (FIG. 1C) Subsequently, the entire substrate is immersed in an electroless plating solution. For example, by holding electroless copper plating solution McDummit 9048 (trade name, manufactured by McDummit) at 60°C and immersing it in it, copper plating is deposited only on the exposed portion of the activation layer (3). , a first conductor layer (5) is formed. This conductor layer pattern is finely patterned by photolithography. (Figure 1d) Next, a photosensitive polyimide precursor is applied onto the substrate.
Dry and expose to UV light using a suitable mask. Thereafter, by developing in a developer, the unexposed portions of the polyimide precursor are removed, and then heated and hardened to form a polyimide layer (6) having through holes (7).
) is obtained. (FIG. 1e) Next, this substrate is subjected to an activation treatment for depositing electroless plating, and subsequently immersed in an electroless plating bath, so that plating is deposited on the entire surface of the substrate. After electroplating this, a resist layer is formed using photolithography and etched to obtain the second conductor layer (8). (Fig. 1 f) In the above embodiment, a case was described in which a ruthenium oxide thick film resistor was used as the resistor, but a resin resistor formed by dispersing conductive particles in a resin may also be used. good.
なお上記実施例では、無電解めっきを析出させるための
活性化層を形成し、この活性化層上にパターン状に樹脂
層を形成し、活性化層の露出部分のみに第１導体層を無
電解めっきにより形成する場合について述べたが、無電
解めっき及び必要に応じて電気めっきを併用し所定のパ
ターン部以外にも導体層を形成した後、写真製版法を用
いてレジスＩ・層を形成し、エツチングすることにより
形成してもよい。In the above example, an activation layer for depositing electroless plating is formed, a resin layer is formed in a pattern on this activation layer, and the first conductor layer is not provided only on the exposed portion of the activation layer. Although we have described the case where it is formed by electrolytic plating, after forming a conductive layer in areas other than the predetermined pattern areas using electroless plating and, if necessary, electroplating in combination, a resist I layer is formed using a photolithography method. However, it may also be formed by etching.
さらに、導体層のパターニング法として、無電解めっき
により導体層を形成した後、写真製版法を用いてレジス
ト層を形成し、レジストが除去され無電解めっきによる
導体層の露出した部分のみに電気めっきを析出させ、続
いてレジス１〜層の除去、及びレジストの除去により露
出した無電解めっきによる導体層を除去する方法を、第
１導体層、第２導体層の一方又は双方に適用してもよい
。Furthermore, as a patterning method for the conductor layer, after forming the conductor layer by electroless plating, a resist layer is formed using photolithography, and after the resist is removed, electroplating is performed only on the exposed part of the conductor layer by electroless plating. The method of depositing resist 1 to layers and removing the conductor layer exposed by electroless plating by removing the resist may be applied to one or both of the first conductor layer and the second conductor layer. good.
また、第１導体層を形成する際に無電解めっきを析出さ
せるための活性化層をペーストの印刷、焼成により形成
する場合について述へたが、他の無電解めっきを析出さ
せるための活性化処理でも、絶縁性基板、抵抗体と良好
な密着力を有する無電解めっき皮膜を得られるものであ
れば良い。In addition, although we have described the case where an activation layer for depositing electroless plating is formed by printing and firing a paste when forming the first conductor layer, activation layers for depositing other electroless platings are also used. Any treatment may be used as long as it can provide an electroless plating film that has good adhesion to the insulating substrate and the resistor.
なお、上記実施例では、絶縁性樹脂層を感光性を有する
ポリイミド前駆体を用いて形成する場合について述へた
が、パターニングが可能で例えば別個なフォトレジス１
−膜を使用してエツチングが可能で無電解メッキ液中で
安定であれば良く、例えばホリアミドカルボン酸系ワニ
ス（これ自身は感光性なし）、エポキシ樹脂等（これ自
身は感光性なし）でも良い。In the above embodiments, the insulating resin layer is formed using a photosensitive polyimide precursor, but patterning is possible and, for example, a separate photoresist 1 is used.
- It is sufficient as long as it can be etched using a film and is stable in an electroless plating solution, such as holamide carboxylic acid varnish (which itself is not photosensitive), epoxy resin, etc. (which itself is not photosensitive). good.
また、上記実施例では、導体層が２層の場合について述
べたが、絶縁性樹脂層の形成、それに続くめっきによる
導体層の形成のプロセスを繰り返すことにより層数を多
くすることが出来ることは言うまでもない。Furthermore, in the above embodiment, the case where there are two conductor layers has been described, but it is possible to increase the number of layers by repeating the process of forming an insulating resin layer and subsequently forming a conductor layer by plating. Needless to say.
この発明は以上説明したとおり、基板に抵抗体を形成す
る工程、この抵抗体に接続して上記基板に写真製版法及
びめっき法を用いて所定パターンの第１導体層を形成す
る工程、第１導体層を形成した基板に写真製版法を用い
て所定パターンの絶縁性樹脂層を形成する工程、並びに
上記絶縁性樹脂層を形成した基板に写真製版法及びめっ
き法を用いて所定パターンの第２導体層を形成する工程
を施すことにより、微細な導体パターンを形成すること
ができ、かつ抵抗体も形成され、多層化も容易に達成で
きるので、高密度、高機能な回路基板を形成できる効果
がある。また、導体材料として卑金属を使用でき、例え
ば銅、ニッケル等を使用すれば、ばんｔ！付は時の導体
層われ、マイグレーション等を低減でき信頼性を高める
ことができるとともに、コストの低減を達成できる。As explained above, the present invention includes a step of forming a resistor on a substrate, a step of connecting to the resistor and forming a first conductor layer of a predetermined pattern on the substrate using a photolithography method and a plating method, a first A step of forming an insulating resin layer with a predetermined pattern on the substrate on which the conductor layer has been formed using a photolithography method, and a step of forming a second insulating resin layer with a predetermined pattern on the substrate on which the insulating resin layer has been formed using a photolithography method and a plating method. By performing the process of forming a conductor layer, a fine conductor pattern can be formed, a resistor can also be formed, and multilayering can be easily achieved, making it possible to form high-density, high-performance circuit boards. There is. Also, base metals can be used as conductor materials, such as copper, nickel, etc., and Bant! Since the conductor layer is attached at the same time, migration and the like can be reduced, reliability can be improved, and costs can be reduced.
第１図（ａ）〜（ｆ）はこの発明の一実施例の回路基板
の製造方法を工程順に示す断面図で、第２図は従来例の
回路基板を示す断面図である。
図において、（１）は絶縁性基板、（２）は抵抗体、（
５）は第１導体層、（６）は絶縁性樹脂層、（８）は第
２導体層である。FIGS. 1(a) to 1(f) are cross-sectional views showing a method of manufacturing a circuit board according to an embodiment of the present invention in the order of steps, and FIG. 2 is a cross-sectional view showing a conventional circuit board. In the figure, (1) is an insulating substrate, (2) is a resistor, (
5) is a first conductor layer, (6) is an insulating resin layer, and (8) is a second conductor layer.
Claims (5)
して上記基板に写真製版法及びめっき法を用いて所定パ
ターンの第１導体層を形成する工程、第１導体層を形成
した基板に写真製版法を用いて所定パターンの絶縁性樹
脂層を形成する工程、並びに上記絶縁性樹脂層を形成し
た基板に写真製版法及びめっき法を用いて所定パターン
の第２導体層を形成する工程を施す回路基板の製造方法
。(1) A step of forming a resistor on a substrate, a step of connecting to the resistor and forming a first conductor layer in a predetermined pattern on the substrate using photolithography and plating, and forming the first conductor layer. A step of forming an insulating resin layer in a predetermined pattern on the substrate using photolithography, and forming a second conductor layer in a predetermined pattern on the substrate on which the insulating resin layer has been formed using photolithography and plating. A method for manufacturing circuit boards that undergoes a process.
第１項記載の回路基板の製造方法。(2) The method for manufacturing a circuit board according to claim 1, wherein the resistor is a cermet resistor.
記載の回路基板の製造方法。(3) The method for manufacturing a circuit board according to claim 1, wherein the resistor is a resin resistor.
である特許請求の範囲第１項ないし第３項のいずれかに
記載の回路基板の製造方法。(4) The method for manufacturing a circuit board according to any one of claims 1 to 3, wherein the plating is either copper or nickel plating.
る特許請求の範囲第１項ないし第４項のいずれかに記載
の回路基板の製造方法。(5) The method for manufacturing a circuit board according to any one of claims 1 to 4, wherein the insulating resin layer is a photosensitive polyimide layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22650285A JPS6285496A (en) | 1985-10-09 | 1985-10-09 | Manufacture of printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22650285A JPS6285496A (en) | 1985-10-09 | 1985-10-09 | Manufacture of printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6285496A true JPS6285496A (en) | 1987-04-18 |
Family
ID=16846116
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22650285A Pending JPS6285496A (en) | 1985-10-09 | 1985-10-09 | Manufacture of printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6285496A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6457695A (en) * | 1987-08-27 | 1989-03-03 | Nec Corp | Hybrid integrated circuit |
| JPH04147695A (en) * | 1990-10-11 | 1992-05-21 | Mitsubishi Materials Corp | Resistor built-in multilayer board |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4978166A (en) * | 1972-12-04 | 1974-07-27 | ||
| JPS5145766A (en) * | 1974-10-17 | 1976-04-19 | Matsushita Electric Ind Co Ltd | TEIKOTSUKI INSATSUHAISENBANNO SEIZOHO |
| JPS52131167A (en) * | 1976-04-26 | 1977-11-02 | Nippon Electric Co | Multilayer circuit substrate |
| JPS53863A (en) * | 1976-06-25 | 1978-01-07 | Hitachi Ltd | Method of producing printed circuit board with resistor |
| JPS53117740A (en) * | 1977-03-23 | 1978-10-14 | Nippon Electric Co | Method of producing thin film circuit |
| JPS56138993A (en) * | 1980-04-01 | 1981-10-29 | Nippon Telegraph & Telephone | Method of producing multilayer printed cirucit board |
| JPS5852900A (en) * | 1981-09-24 | 1983-03-29 | 株式会社日立製作所 | Method of producing ceramic multilayer circuit board |
| JPS5974608A (en) * | 1982-10-21 | 1984-04-27 | Hitachi Ltd | Formation of wiring structure |
| JPS6059765A (en) * | 1983-09-13 | 1985-04-06 | Mitsubishi Electric Corp | Manufacture of hybrid integrated circuit substrate |
-
1985
- 1985-10-09 JP JP22650285A patent/JPS6285496A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4978166A (en) * | 1972-12-04 | 1974-07-27 | ||
| JPS5145766A (en) * | 1974-10-17 | 1976-04-19 | Matsushita Electric Ind Co Ltd | TEIKOTSUKI INSATSUHAISENBANNO SEIZOHO |
| JPS52131167A (en) * | 1976-04-26 | 1977-11-02 | Nippon Electric Co | Multilayer circuit substrate |
| JPS53863A (en) * | 1976-06-25 | 1978-01-07 | Hitachi Ltd | Method of producing printed circuit board with resistor |
| JPS53117740A (en) * | 1977-03-23 | 1978-10-14 | Nippon Electric Co | Method of producing thin film circuit |
| JPS56138993A (en) * | 1980-04-01 | 1981-10-29 | Nippon Telegraph & Telephone | Method of producing multilayer printed cirucit board |
| JPS5852900A (en) * | 1981-09-24 | 1983-03-29 | 株式会社日立製作所 | Method of producing ceramic multilayer circuit board |
| JPS5974608A (en) * | 1982-10-21 | 1984-04-27 | Hitachi Ltd | Formation of wiring structure |
| JPS6059765A (en) * | 1983-09-13 | 1985-04-06 | Mitsubishi Electric Corp | Manufacture of hybrid integrated circuit substrate |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6457695A (en) * | 1987-08-27 | 1989-03-03 | Nec Corp | Hybrid integrated circuit |
| JPH04147695A (en) * | 1990-10-11 | 1992-05-21 | Mitsubishi Materials Corp | Resistor built-in multilayer board |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4897338A (en) | Method for the manufacture of multilayer printed circuit boards | |
| US4629681A (en) | Method of manufacturing multilayer circuit board | |
| KR850001363B1 (en) | Method for manufacturing a fine patterned thick film conductor structure | |
| JP3226489B2 (en) | Suspension board with circuit | |
| JP3655336B2 (en) | Printed wiring board manufacturing method and printed wiring board | |
| JPS61194794A (en) | Manufacture of hybrid integrated circuit board | |
| WO1988005252A1 (en) | Method for the manufacture of multilayer printed circuit boards | |
| JPS6285496A (en) | Manufacture of printed circuit board | |
| JPS6337694A (en) | Manufacture of circuit board | |
| JPS61185995A (en) | Making of circuit board with resistor | |
| JPH08107263A (en) | Manufacturing method of printed-wiring board | |
| JPH1079568A (en) | Manufacturing method of printed circuit board | |
| JPS6167989A (en) | Method of producing multilayer circuit board | |
| JPH03225894A (en) | Manufacture of printed wiring board | |
| JPS62137898A (en) | Munufacture of multilayer circuit board | |
| JPS62171194A (en) | Matrix wiring board | |
| JPS63187687A (en) | Manufacture of printed wiring board | |
| JPS6123390A (en) | Circuit board and method of producing same | |
| JPS63186495A (en) | Manufacture of circuit board | |
| JPS625692A (en) | Manufacture of circuit board | |
| JPS61256688A (en) | Manufacture of circuit board | |
| JPH03191542A (en) | Manufacture of film carrier tape | |
| JPH04357895A (en) | Manufacture of ceramic wiring board | |
| JPS6040200B2 (en) | Multilayer circuit board manufacturing method | |
| JPS59188997A (en) | Method of producing printed circuit board for wiring bonding |