JPS625692A - Manufacture of circuit board - Google Patents

Manufacture of circuit board

Info

Publication number
JPS625692A
JPS625692A JP14933385A JP14933385A JPS625692A JP S625692 A JPS625692 A JP S625692A JP 14933385 A JP14933385 A JP 14933385A JP 14933385 A JP14933385 A JP 14933385A JP S625692 A JPS625692 A JP S625692A
Authority
JP
Japan
Prior art keywords
film
base material
thickness
resist layer
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14933385A
Other languages
Japanese (ja)
Inventor
本間 政治
池田 克人
石山 義夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lincstech Circuit Co Ltd
Original Assignee
Hitachi Condenser Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Condenser Co Ltd filed Critical Hitachi Condenser Co Ltd
Priority to JP14933385A priority Critical patent/JPS625692A/en
Publication of JPS625692A publication Critical patent/JPS625692A/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は無電解メッキ法により導電体を形成する回路板
の製造法に関する。最近のように電子部品の小型化やI
C等の集積回路部品が多く用いられるようになると、導
電体パターンの距離の縮小化がすすみ5メッキレジスト
層を得る手段として。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a circuit board in which conductors are formed by electroless plating. Recently, the miniaturization of electronic components and
As integrated circuit components such as C were increasingly used, the distance between conductive patterns was reduced, and as a means of obtaining a plated resist layer.

フォトマスク方式が有効である。A photomask method is effective.

本発明はフォトマスク方式に使用される感光性樹脂フィ
ルムが耐アルカリ性に強く (メッキ液は高アルカリ)
かつ半田層に浸漬する際に受ける熱劣化が少い(熱によ
り亀裂の発生がなく、フィルムの絶縁抵抗の劣化が少い
)フィルムを用い、このフィルムを永久メツキレシスト
として印刷配線板に形成されたまま残存させる構成のも
のである。
In the present invention, the photosensitive resin film used in the photomask method has strong alkali resistance (the plating solution is highly alkaline).
Using a film that suffers less thermal deterioration when immersed in the solder layer (no cracks occur due to heat, and less deterioration of the insulation resistance of the film), this film is used as a permanent metal resist to form printed wiring boards. It is configured to remain as it is.

この永久メツキレシストは導電体の逆パターンが形成さ
れ、従ってこのレジス1−が付着されない箇所に導電体
が形成される。この導電体層の厚さをメツキレシスト厚
より薄くすることを特徴とする。
This permanent plating resist is formed with a reverse pattern of conductors, so that conductors are formed in locations where this resist 1- is not attached. A feature is that the thickness of this conductive layer is thinner than the thickness of the mesh resist.

従来のアディティブ方式による印刷配線板の製造方法は
基材として触媒入りのエポキシガラス積層板等の絶縁板
を用い、この基材の表面にエポキシ樹脂の逆導電体パタ
ーンを印刷し、この基板を無電解銅メッキ液に浸漬する
と、この逆導電体パターン印刷でメンキレシスiされた
以外の箇所に銅メッキが析出する。この銅メッキの厚み
は基板を浸漬した時間に比例して増加するので厚みは自
由に制御できる。このシンク印刷によりメッキレジスト
層を形成する方式は、導電体パターンの間陪がますまず
せまくなり接近してくると1現在の印刷技術をしては限
界があり、印刷がかずれたり。
The conventional manufacturing method for printed wiring boards using the additive method uses an insulating board such as a catalyst-containing epoxy glass laminate as a base material, prints a reverse conductor pattern of epoxy resin on the surface of this base material, and then removes this board. When immersed in an electrolytic copper plating solution, copper plating is deposited at locations other than those where the electrolytic conductor pattern is printed. The thickness of this copper plating increases in proportion to the time the substrate is immersed, so the thickness can be freely controlled. This method of forming a plating resist layer by sink printing has its limits when the conductor patterns become narrower and closer to each other, and the printing may be misaligned.

蛇行したり、隣接したパターンどうしが接触してしまう
等の問題があり、不良率を低減することができなかった
There were problems such as meandering and adjacent patterns coming into contact with each other, and it was not possible to reduce the defective rate.

本発明の印刷配線板は、メッキレジストをエポキシ樹脂
のシンク印刷方式によらず耐熱・耐薬品性のある感光性
樹脂フィルムを用いて1 その上にネガフィルムをのせ
、光照射することにより、先便光させて、永久フォトプ
リントとしてメツキレシストの作用を行わせるものであ
る。
In the printed wiring board of the present invention, the plating resist is applied by using a heat-resistant and chemical-resistant photosensitive resin film instead of using an epoxy resin sink printing method. It is used to make a permanent photo print and perform the action of a metsukire cyst.

本発明の実施例をは面に基づき説明すると21が基材で
あり、この基材1には無電解銅メッキ液に浸漬した際に
銅の析出を促進する触媒2が混入されている。3は耐熱
・耐薬品性に秀れた感光性樹脂フィルム(例えば日立化
成株式会社製5R−106)であり、このフィルム3を
基材1の表面にラミネート処理する。このフィルムの厚
みは付着メ・ツキ厚より厚いものを用いることにする。
The embodiment of the present invention will be described based on the aspect. Reference numeral 21 is a base material, and this base material 1 is mixed with a catalyst 2 that promotes copper deposition when immersed in an electroless copper plating solution. 3 is a photosensitive resin film having excellent heat resistance and chemical resistance (for example, 5R-106 manufactured by Hitachi Chemical Co., Ltd.), and this film 3 is laminated on the surface of the base material 1. The thickness of this film is greater than the thickness of the adhesion layer.

メンキ厚の標準は30μ程度であるからこの場合に対応
するフィルム厚は40μ以上の適宜な厚みのものを使用
すればよい。
Since the standard film thickness is about 30 μm, a suitable film thickness of 40 μm or more may be used in this case.

この感光性樹脂フィルム3の上に導電体パターンが焼付
けられたネガフィルム4を載置し、光を照射すればネガ
フィルム4の透明部分6をlした透過光によりフィルム
3は硬化7する。この後フィルムの硬化を促進するだめ
の加熱処理を行い。
A negative film 4 on which a conductive pattern has been printed is placed on the photosensitive resin film 3 and irradiated with light, whereby the film 3 is cured by the transmitted light through the transparent portion 6 of the negative film 4. After this, a heat treatment is performed to accelerate the hardening of the film.

冷却して常温に戻ったら、トリクロルエタン等の薬品で
現像するとフィルム3の未硬化部8が、/lll Hさ
れるので、硬化部7のみが基材1に形成された状態で残
る。すなわちメツキレシスト層9が形成されたことにな
る。
After cooling and returning to room temperature, the uncured portion 8 of the film 3 is developed with a chemical such as trichloroethane, so that only the cured portion 7 remains on the base material 1. In other words, the mesh resist layer 9 has been formed.

メッキレジスト層9が形成された基材10を公知の無電
解銅メッキ層に浸漬すると1時間の経過と共に、浸漬時
間に比例して、メッキレジスト9が形成されていない箇
所に銅メッキが析出し導電体11が形成される。この導
電体11の厚みはメッキレジスト層9の厚さより薄<シ
、導電体層11とメツキレシスト層9との間に段差が生
じる。
When the base material 10 on which the plating resist layer 9 is formed is immersed in a known electroless copper plating layer, as one hour passes, copper plating is deposited in areas where the plating resist 9 is not formed in proportion to the immersion time. A conductor 11 is formed. The thickness of the conductor 11 is thinner than the thickness of the plating resist layer 9, and a step is created between the conductor layer 11 and the plating resist layer 9.

本発明の印刷配線板は1表面に付着されたメッキレジス
ト層9を導電体層11厚より厚くすることにより、フラ
ットバック型の電子部品20の端子部21をのせれば 
ffi子部品が位置を決めされるので、その後の半田付
は作業を確実に行え、半田付は作業時に電子部品が移動
してしまうミスを防止できる。また、隣接する導電体間
の間隔がせまくなっても、導体間の沿面距離を長くでき
るので絶縁特性の向上にも効果を有する発明である。
In the printed wiring board of the present invention, the plating resist layer 9 attached to the surface is made thicker than the conductor layer 11, so that the terminal portion 21 of the flat-back type electronic component 20 can be placed on the printed wiring board.
Since the position of the ffi child component is determined, subsequent soldering work can be performed reliably, and mistakes such as the electronic parts moving during soldering work can be prevented. Further, even if the distance between adjacent conductors becomes narrow, the creepage distance between the conductors can be increased, so this invention is effective in improving insulation properties.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の基材の断面図、第2図は基材に感光性
樹脂フィルムをラミネートした断面図。 第3図はネガフィルムをのせて光を照射しフィルムが焼
付された状態を示す断面図、第4図は現像してフィルム
が硬化されメッキレジストとして形成された状態を示す
断面図、第5図はフィルム厚より薄い導電体層が形成さ
れた状態を示す断面図。 第6図は電子部品がセットされた断面図である。 図面において、■は基材、2は基材に混入した触媒、3
は感光性樹脂フィルム、4はネガフィルム、5は照射す
る光、6はネガフィルムの透明部。 7は感光性フィルムの硬化部、9は永久メッキレジスト
 11は導電体、20は電子部品、21は電子部品の端
子部。
FIG. 1 is a sectional view of the base material of the present invention, and FIG. 2 is a sectional view of the base material laminated with a photosensitive resin film. Figure 3 is a sectional view showing the state in which a negative film is placed and exposed to light to be printed, Figure 4 is a sectional view showing the state in which the film is developed and hardened and formed as a plating resist, and Figure 5 is a cross-sectional view showing a state in which a conductor layer thinner than the film thickness is formed. FIG. 6 is a sectional view in which electronic components are set. In the drawing, ■ indicates the base material, 2 indicates the catalyst mixed in the base material, and 3 indicates the catalyst mixed in the base material.
4 is a photosensitive resin film, 4 is a negative film, 5 is irradiated light, and 6 is a transparent part of the negative film. 7 is a cured portion of a photosensitive film, 9 is a permanent plating resist, 11 is a conductor, 20 is an electronic component, and 21 is a terminal portion of the electronic component.

Claims (1)

【特許請求の範囲】[Claims] 1、絶縁基材上に導電体と逆パターンのメッキレジスト
層を形成し、この基板を無電解メッキ液に浸漬してメッ
キレジスト層の厚さよりうすい厚さの導電体パターンを
形成すると共に、メッキレジスト層をそのままソルダー
レジストとして残し、導電体パターン面に電子部品の端
子をのせ半田付けを行うことを特徴とする回路板の製造
法。
1. Form a plating resist layer with a pattern opposite to that of the conductor on an insulating base material, and immerse this substrate in an electroless plating solution to form a conductor pattern with a thickness thinner than the thickness of the plating resist layer. A method of manufacturing a circuit board characterized by leaving a resist layer as it is as a solder resist, placing terminals of electronic components on a conductive pattern surface, and performing soldering.
JP14933385A 1985-07-09 1985-07-09 Manufacture of circuit board Pending JPS625692A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14933385A JPS625692A (en) 1985-07-09 1985-07-09 Manufacture of circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14933385A JPS625692A (en) 1985-07-09 1985-07-09 Manufacture of circuit board

Publications (1)

Publication Number Publication Date
JPS625692A true JPS625692A (en) 1987-01-12

Family

ID=15472813

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14933385A Pending JPS625692A (en) 1985-07-09 1985-07-09 Manufacture of circuit board

Country Status (1)

Country Link
JP (1) JPS625692A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63285996A (en) * 1987-05-18 1988-11-22 Hitachi Condenser Co Ltd Method for fixing electronic parts to printed circuit board
JPH01128590A (en) * 1987-11-13 1989-05-22 Nec Corp Solder feeding film and soldering method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58128791A (en) * 1982-01-27 1983-08-01 日立コンデンサ株式会社 Method of producing printed circuit board and printed circuit board
JPS58220493A (en) * 1982-06-16 1983-12-22 シャープ株式会社 Circuit substrate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58128791A (en) * 1982-01-27 1983-08-01 日立コンデンサ株式会社 Method of producing printed circuit board and printed circuit board
JPS58220493A (en) * 1982-06-16 1983-12-22 シャープ株式会社 Circuit substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63285996A (en) * 1987-05-18 1988-11-22 Hitachi Condenser Co Ltd Method for fixing electronic parts to printed circuit board
JPH01128590A (en) * 1987-11-13 1989-05-22 Nec Corp Solder feeding film and soldering method

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