JPS63285996A - Method for fixing electronic parts to printed circuit board - Google Patents
Method for fixing electronic parts to printed circuit boardInfo
- Publication number
- JPS63285996A JPS63285996A JP62120647A JP12064787A JPS63285996A JP S63285996 A JPS63285996 A JP S63285996A JP 62120647 A JP62120647 A JP 62120647A JP 12064787 A JP12064787 A JP 12064787A JP S63285996 A JPS63285996 A JP S63285996A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- plating resist
- resist layer
- conductive material
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 18
- 239000004020 conductor Substances 0.000 claims abstract description 48
- 229910000679 solder Inorganic materials 0.000 claims abstract description 43
- 238000007747 plating Methods 0.000 claims abstract description 29
- 239000000463 material Substances 0.000 claims abstract description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 6
- 239000000853 adhesive Substances 0.000 claims abstract description 5
- 239000003054 catalyst Substances 0.000 claims abstract description 5
- 239000011889 copper foil Substances 0.000 claims abstract description 5
- 230000001070 adhesive effect Effects 0.000 claims description 4
- 238000007639 printing Methods 0.000 abstract description 6
- 238000005476 soldering Methods 0.000 abstract description 5
- 238000007772 electroless plating Methods 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract 3
- 239000012530 fluid Substances 0.000 abstract 1
- 238000007650 screen-printing Methods 0.000 abstract 1
- 230000000052 comparative effect Effects 0.000 description 5
- 239000000654 additive Substances 0.000 description 4
- 230000000996 additive effect Effects 0.000 description 4
- 238000001035 drying Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 230000013011 mating Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3485—Applying solder paste, slurry or powder
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
- H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
- H05K3/184—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method using masks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はアディティブ法により導電体を形成する印刷配
線板を用い電子部品を固着する方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for fixing electronic components using a printed wiring board on which conductors are formed by an additive method.
従来の技術
配線板は高密度化が進み導体幅及び導体間の距離が著し
く狭くなってきている。また、配線板上に搭載する電子
部品の数も増え、半導体も接続端子の本数が増えている
。Conventional wiring boards have become denser and the conductor widths and distances between conductors have become significantly narrower. Additionally, the number of electronic components mounted on wiring boards is increasing, and the number of semiconductor connection terminals is also increasing.
このように高密度化された配線板に電子部品を固着する
のに半田付けが行われている。このとき、はんだめっき
されていない銅箔回路の所定導体面積にわたり半田ペー
ストを印刷し、乾燥後、フュージングして半田付けする
方法がとられている。Soldering is used to secure electronic components to such high-density wiring boards. At this time, a method is used in which a solder paste is printed over a predetermined conductor area of a copper foil circuit that is not solder plated, and after drying, the paste is fused and soldered.
しかし、配線板は吸湿現象や温度変化により膨張収縮す
るため、細い幅の導体回路に半田ペーストを規則正しく
印刷することは困難な作業である。However, since wiring boards expand and contract due to moisture absorption and temperature changes, it is difficult to regularly print solder paste on narrow conductor circuits.
アディティブ法により製造するＣＧ−４法では、めっき
触媒を含んだ接着剤を積層板の表面に設け、めっきレジ
ストを印刷フォト法で′＃電電路路逆パターンのめっき
レジスト層を形成してから無電解銅めっきを行うため、
導体とめっきレジスト層との段差が小さく、導体回路部
分のみならずめっきレジスト層上に半田ペーストを印刷
する部分ベタ印刷を行っても、その後のフュージング工
程で半田が溶融する際、半田の表面張力で半田が導体上
に集まることがわかった。In the CG-4 method, which is manufactured using an additive method, an adhesive containing a plating catalyst is applied to the surface of the laminate, and a plating resist layer with a reverse pattern of electrical circuits is formed using a printing photo method, and then the plating resist layer is removed. To perform electrolytic copper plating,
Even if the level difference between the conductor and the plating resist layer is small, and the solder paste is printed not only on the conductor circuit area but also on the plating resist layer, the surface tension of the solder will increase when the solder melts in the subsequent fusing process. It was found that solder collects on the conductor.
発明が解決しようとする問題点
ＣＣ−４１法で製造した配線板の導体幅及び導体間の距
離が狭いものを用い、半田ペーストを印刷し、フュージ
ング後、配線板を観察すると、導体間に小さな半田ボー
ルが見受けられた。これは、半田揚げした後、洗浄工程
を省略する場合などに導体間の絶縁性及び信頼性が問題
である。Problems to be Solved by the Invention When using a wiring board manufactured by the CC-41 method with narrow conductor width and narrow distance between conductors, printing solder paste and observing the wiring board after fusing, it was found that there were small gaps between the conductors. Solder balls were observed. This poses a problem in insulation and reliability between conductors when a cleaning step is omitted after soldering.
本発明は半田ペースト印刷後のフュージング工程で半田
ボール発生が少ない配線板を提供する。The present invention provides a wiring board that generates fewer solder balls during the fusing process after printing solder paste.
問題点を解決するための手段
本発明は、触媒入り接着剤を付着した絶縁板を基材とし
、この基材にめっきレジスト層を形成し、無電解ｇＡ箔
による導電体を形成する際導電体の表面よりめっきレジ
スト層の表面が凹んでいてこの段差が２０μ７７Ｌ以下
である配線板を用い、電子部品を取着するための導電体
とめつきレジスト層との上に所定幅の半田ペーストを印
刷し、乾燥した後フュージングし、電子部品をｔａし半
田リフローをして電子部品を固着する方法である。Means for Solving the Problems The present invention uses an insulating plate to which a catalyst-containing adhesive is attached as a base material, forms a plating resist layer on this base material, and forms a conductor using electroless gA foil. Using a wiring board in which the surface of the plating resist layer is recessed from the surface of the board and the level difference is 20μ77L or less, solder paste of a predetermined width is printed on the conductor and the plating resist layer for attaching electronic components. This is a method of fusing the electronic components after drying, tacking the electronic components, and performing solder reflow to secure the electronic components.
無電解めっきによるフルアディティブ法では、配線板に
形成する導体厚さは通常２５μ７７Ｌ以上であり、銅張
り積層板を用いエツチング法による回路では導体厚さは
３５μｍ程度、ざらにスルーホールめっきを行う場合に
は導体厚さは７０μ゛ｍが一般的である。エツチング法
で製造された配線板は、この導体厚７０μ卯の間に半田
レジストを印刷することになり、導体に付着せずに導体
間のみに半田レジスト層を形成することは大変難しい。In the full additive method using electroless plating, the conductor thickness formed on the wiring board is usually 25μ77L or more, and in the circuit using the etching method using a copper-clad laminate, the conductor thickness is about 35μm, and when rough through-hole plating is performed. The conductor thickness is generally 70 μm. In a wiring board manufactured by the etching method, a solder resist is printed between the conductors with a thickness of 70 μm, and it is very difficult to form a solder resist layer only between the conductors without adhering to the conductors.
アディティブ法のＣＧ−４配線板では、めっきレジスト
層が形成されているので導体との段差は小さい。この段
差が小さいほど、半田ペースト中の半田ボールがレジス
ト表面に残る度合が小さく、段差が２０μｍ以下好まし
くは１５μＴｒＬ以下にするとよいことがわかった。In the CG-4 wiring board manufactured using the additive method, since a plating resist layer is formed, the level difference between the plating resist layer and the conductor is small. It has been found that the smaller the level difference is, the less the solder balls in the solder paste remain on the resist surface, and that the level difference is preferably 20 μm or less, preferably 15 μTrL or less.
作用
本発明の配線板は導電体及びめっきレジスト層との段差
が２０μｍ以下に形成するので、導電体のみでなく、導
電体及び導電体間（めっきレジスト層）にわたり、半田
ペーストの印刷を行っても、フュージング工程で半田が
溶融し導体表面に半田が集まり、電子部品の固着を確実
に行うことができる。Function: Since the wiring board of the present invention has a level difference of 20 μm or less between the conductor and the plating resist layer, the solder paste is printed not only on the conductor but also between the conductor and the conductor (the plating resist layer). Also, during the fusing process, the solder melts and collects on the conductor surface, making it possible to securely secure electronic components.
実施例
（実施例１）
触媒入り接着剤１を付着した積層板２（日立化成工業株
式会社製ＡＣＬ−Ｅ−１４４＞を基材３とし、この基材
３にめっきレジストインク（日立化成工業株式会社製Ｈ
ＣＴＭ−０２ＲＶ〜１）を印刷硬化して回路と逆パター
ンのめっきレジスト層４を形成する。Examples (Example 1) A laminate 2 (ACL-E-144 manufactured by Hitachi Chemical Co., Ltd.) to which a catalyst-containing adhesive 1 was adhered was used as a base material 3, and a plating resist ink (produced by Hitachi Chemical Co., Ltd.) was applied to the base material 3. Company made H
CTM-02RV~1) is printed and cured to form a plating resist layer 4 with a pattern opposite to the circuit.
この後無電解めっき液に基材を浸漬して銅箔の導電体５
厚さを３０μ而形成する。導電体５とめつきレジスト層
４との段差は１５μｍのＬＳＩ用のランド６が形成され
る。After this, the base material is immersed in an electroless plating solution to form a copper foil conductor 5.
Form a thickness of 30 μm. A land 6 for LSI is formed with a step difference between the conductor 5 and the plating resist layer 4 of 15 μm.
このランド６上に導電体５及びめっきレジスト層４にわ
たり半田ペースト（タムラ化研株式会社製５Ｓ−３２２
＞をスクリーン印刷し、約２５μｍ厚の半田ペースト層
７を形成した。この後フュージングを行い端子用導体５
に半田８を集め、半田８を冷却した後し８１９の端子１
０を導体５の半田８上に載置し、２５０℃で半田をリフ
ローしてＬＳＩ９を配線板上に固着した。半田リフロー
を行った後ＬＳＩを取り外し、端子用導体５間のめっき
レジスト層４上に残る半田ボールを調査した結果を下表
に示す。Solder paste (5S-322 manufactured by Tamura Kaken Co., Ltd.) is applied over the conductor 5 and the plating resist layer 4 on this land 6.
> was screen printed to form a solder paste layer 7 with a thickness of about 25 μm. After this, fusing is performed and the terminal conductor 5
Collect the solder 8 and after cooling the solder 8, connect the terminal 1 of 819
0 was placed on the solder 8 of the conductor 5, and the solder was reflowed at 250° C. to fix the LSI 9 on the wiring board. After performing solder reflow, the LSI was removed and solder balls remaining on the plating resist layer 4 between the terminal conductors 5 were investigated. The results are shown in the table below.
（実施例２）
実施例１において、基材３上に形成するめつぎレジスト
層４と、無電解銅箔による導電体５との段差を１０μ扉
とした。それ以外は実施例１に基づいて電子部品を固着
し、その後半田ボールを調査し、た。(Example 2) In Example 1, the step difference between the mating resist layer 4 formed on the base material 3 and the conductor 5 made of electroless copper foil was set to 10 μm. Other than that, the electronic components were fixed based on Example 1, and the solder balls were then examined.
（比較例１）
銅張り積層板を基材とし、スルーホールを形成した配線
板を用い、この配線板の導体及び導体間の段差が７０μ
ｍである配線板上に、半田ペーストを印刷し、乾燥した
。(Comparative Example 1) A wiring board with a copper-clad laminate as the base material and through holes formed therein was used, and the level difference between the conductors of this wiring board was 70 μm.
Solder paste was printed on the wiring board of 1.m and dried.
（比較例２）
比較例１で、導体間（沿面距離０．２ｙ）に半田レジス
トを印刷しようとしたが、導体間が狭く、段差が大きい
ので、半田レジストの転写ができなかった。(Comparative Example 2) In Comparative Example 1, an attempt was made to print a solder resist between the conductors (creepage distance of 0.2y), but the solder resist could not be transferred because the distance between the conductors was narrow and the level difference was large.
（比較例３）
実施例１において、基材３に形成した導体５厚さを４０
μｍとし、めっきレジスト４との段差は２５μｍとし、
その後の工程は同一にした。(Comparative Example 3) In Example 1, the thickness of the conductor 5 formed on the base material 3 was set to 40
μm, and the step with the plating resist 4 is 25 μm.
The subsequent steps were the same.
以上の実施例及び比較例で製造したものの特性を下表に
示す。The properties of the products manufactured in the above Examples and Comparative Examples are shown in the table below.
表 以下余白。table Margin below.
発明の効果
（１）配線板への半田ペーストの印刷が均一かつ容易に
行えるようになった。Effects of the invention (1) Printing of solder paste on a wiring board can now be performed uniformly and easily.
（２）狭い導体間への半田ボールの残りがなく、導体間
の絶縁性が良好で、電子部品の接続信頼性だ向上した。(2) There are no residual solder balls between narrow conductors, and the insulation between conductors is good, improving the connection reliability of electronic components.
第１図は本発明の正面図、第２図はランドの平面図、第
３図は同正面図、第４図は半田ペースト塗布箋フュージ
ング後の正面図である。
３：基材、 ４：めっきレジスト、 ５：４体、７：半
田ペースト、 ８：半田、
９：電子部品、 １０：端子。FIG. 1 is a front view of the present invention, FIG. 2 is a plan view of a land, FIG. 3 is a front view of the land, and FIG. 4 is a front view of the solder paste paste after fusing. 3: Base material, 4: Plating resist, 5: 4 bodies, 7: Solder paste, 8: Solder, 9: Electronic component, 10: Terminal.
Claims (1)
の基材にめつきレジスト層を形成した後、無電解銅箔に
よる導電体層を形成する際、導電体とめつきレジスト層
との段差を２０μｍ以下である配線板を用い、電子部品
の端子を固着するための導電体とめっきレジスト層とに
所定面積の半田ペーストを印刷し、乾燥した後、フュー
ジングし、ついで電子部品を載置して半田リフローを行
って電子部品を固着する印刷配線板への電子部品の固着
方法。(1) After forming a plating resist layer on a laminate plate with a catalyst-containing adhesive attached as a base material, and forming a conductor layer using electroless copper foil, the conductor and the plating resist layer are formed. Using a wiring board with a level difference of 20 μm or less, a predetermined area of solder paste is printed on the conductor and plating resist layer for fixing the terminals of electronic components, dried and fused, and then the electronic components are mounted. A method of fixing electronic components to a printed wiring board, in which the electronic components are fixed by placing them on the printed wiring board and performing solder reflow.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62120647A JPS63285996A (en) | 1987-05-18 | 1987-05-18 | Method for fixing electronic parts to printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62120647A JPS63285996A (en) | 1987-05-18 | 1987-05-18 | Method for fixing electronic parts to printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63285996A true JPS63285996A (en) | 1988-11-22 |
Family
ID=14791400
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62120647A Pending JPS63285996A (en) | 1987-05-18 | 1987-05-18 | Method for fixing electronic parts to printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63285996A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5186383A (en) * | 1991-10-02 | 1993-02-16 | Motorola, Inc. | Method for forming solder bump interconnections to a solder-plated circuit trace |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58101492A (en) * | 1981-12-11 | 1983-06-16 | セイコーインスツルメンツ株式会社 | Method of forming conductive pattern of circuit board |
| JPS58138090A (en) * | 1982-02-12 | 1983-08-16 | 株式会社日立製作所 | Method of producing printed circuit board |
| JPS59145592A (en) * | 1984-01-17 | 1984-08-21 | 株式会社ケンウッド | Method of mounting electronic part on printed circuit board |
| JPS625692A (en) * | 1985-07-09 | 1987-01-12 | 日立コンデンサ株式会社 | Manufacture of circuit board |
-
1987
- 1987-05-18 JP JP62120647A patent/JPS63285996A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58101492A (en) * | 1981-12-11 | 1983-06-16 | セイコーインスツルメンツ株式会社 | Method of forming conductive pattern of circuit board |
| JPS58138090A (en) * | 1982-02-12 | 1983-08-16 | 株式会社日立製作所 | Method of producing printed circuit board |
| JPS59145592A (en) * | 1984-01-17 | 1984-08-21 | 株式会社ケンウッド | Method of mounting electronic part on printed circuit board |
| JPS625692A (en) * | 1985-07-09 | 1987-01-12 | 日立コンデンサ株式会社 | Manufacture of circuit board |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5186383A (en) * | 1991-10-02 | 1993-02-16 | Motorola, Inc. | Method for forming solder bump interconnections to a solder-plated circuit trace |
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