JP4687084B2 - Method for manufacturing printed wiring board with built-in passive element - Google Patents

Description

  The present invention relates to a printed wiring board of various electronic devices having a built-in passive element, and more particularly to a method of manufacturing a printed wiring board with a built-in passive element (especially a resistance element) that has a stable element constant and can be manufactured at low cost. is there.

In recent years, as devices such as mobile phones and digital cameras have become smaller and lighter, conventional mounting technologies such as component miniaturization and component spacing have become difficult to cope with. Expectations are growing. Passive components (capacitors, resistors, inductors) can satisfy the characteristics required by device manufacturers relatively easily if existing components are used, but there is a problem that the substrate containing the components becomes thick.
There is an urgent need to develop materials that can sufficiently satisfy the characteristics of small and thin parts.

As a method of forming a resistance element on a printed wiring board, a method of forming a resistance layer with a metal thin film on a copper foil, a method of forming by plating on an insulating substrate, a method in which conductive particles are mixed with a resin, and printing and baking are performed. There are methods.
It is necessary to select a forming method according to the application from the resistance value accuracy, shape, price, and the like. In the method of printing a thick film polymer, a high resistance can be formed, but it is difficult to form at a fine size, and the resistance value changes greatly due to temperature, moisture absorption, etc., and a highly accurate resistance element can be obtained. Have difficulty. The thin film type using a metal material is restricted to a low resistance range as compared with the thick film type, but can be formed with a small size and high accuracy.

  In addition, mobile devices typified by mobile phones are expected to be used in various environments, and are desired to be highly accurate elements that are not affected by temperature changes or humidity changes.

As a method of forming a resistance layer with a metal thin film on a copper foil, a method called Ohmega-Ply has been proposed by Ohmega Electoronics (see, for example, Patent Document 1).
In this method, a thin film resistance layer formed by electrolytic nickel / phosphorous plating on a copper foil is laminated and formed on an insulating material, and the formation of a wiring pattern is limited to the subtractive method. This method involves a step of exposing the nickel-phosphorus film, which is a resistor, to an etching solution before forming an element, and there is a problem in that the resistance value varies depending on the etching state. In addition, since the wiring pattern cannot be formed by the semi-additive method, there is a problem that it is difficult to use the wiring pattern for a high-density wiring substrate.
U.S. Pat. No. 4,808,967

  It is an object of the present invention to provide a method for manufacturing an element-embedded printed wiring board having resistance elements with less variation in resistance value than conventional methods in an element-embedded printed wiring board.

In order to achieve the above object, according to the first aspect of the present invention, in a method for manufacturing a multilayer printed wiring board in which a resistive element including a resistor and an element electrode is incorporated as a passive element, at least the following (a): A method for manufacturing a printed wiring board with a built-in passive element, comprising the steps ( j ) to ( j ).
(A) A step of forming a double-sided wiring board by forming a wiring pattern on both sides of an insulating substrate.
(B) A step of forming insulating layers on both sides of the double-sided wiring board.
(C) A step of forming a via hole in the insulating layer.
(D) A step of forming a plating base conductive layer in the insulating layer and the via hole, and further forming a resist pattern.
(E) A step of forming a conductor layer and a via by performing electrolytic copper plating using the plating base conductive layer as a cathode.
(F) A step of removing the resist pattern, further removing the plating base conductive layer below the resist pattern, forming a wiring pattern and an element electrode on one surface, and forming a pad electrode on the other surface.
(G) forming a photosensitive layer on the wiring pattern and the insulating layer, and further forming a photosensitive layer on the pad electrode and the insulating layer;
(H) The photosensitive layer formed on the pad electrode and the insulating layer obtained by forming the resist pattern having an opening in the photosensitive layer formed on the wiring pattern and the insulating layer obtained by the step. Forming a resist on the substrate.
(I) A step of forming a resistance layer on the resist pattern and in the opening.
(J) A step of peeling the resist pattern and the resist, forming a resistance element in which a resistor is formed between the element electrodes on one surface, and forming a pad electrode on the other surface.
According to a second aspect of the present invention, in the method of manufacturing a multilayer printed wiring board in which a resistive element composed of a resistor and an element electrode is incorporated as a passive element, at least the following steps (a) to ( j ) are provided. This is a method of manufacturing a printed wiring board with a built-in passive element.
(A) A step of forming a double-sided wiring board by forming a wiring pattern on both sides of an insulating substrate.
(B) A step of forming insulating layers on both sides of the double-sided wiring board.
(C) A step of forming a via hole in the insulating layer.
(D) A step of forming a plating base conductive layer on the insulating layer and in the via hole, and further forming a resist pattern.
(E) A step of forming a conductor layer and a via by performing electrolytic copper plating using the plating base conductive layer as a cathode.
(F) A step of removing the resist pattern, further removing the plating base conductive layer below the resist pattern, forming a wiring pattern and an element electrode on one surface, and forming a pad electrode on the other surface.
(G) forming a resistance layer on the wiring pattern and the insulating layer, and further forming a resist on the pad electrode and the insulating layer;
(H) A step of forming a photosensitive layer on the resistance layer.
(I) A step of forming a resist pattern on the photosensitive layer.
(J) removing the resistance layer using the resist pattern as a mask, further peeling the resist pattern and the resist, and forming a resistance element in which a resistor is formed between the element electrodes on one surface; Forming a pad electrode on the other surface;

  According to a third aspect of the present invention, in the method for manufacturing a printed wiring board with a built-in passive element according to the first or second aspect, the resistance layer is formed by plating.

  The passive element according to any one of claims 1 to 3, wherein the resistance layer is a nickel-phosphorus binary alloy or a nickel-phosphorus ternary alloy. This is a method for manufacturing a built-in printed wiring board.

  The manufacturing method of the passive element built-in printed wiring board of the present application is a manufacturing method in which after forming a wiring pattern, a resistance layer is formed on the entire surface by plating, and unnecessary portions are removed. Therefore, it is not necessary to go through a process that causes oxidation or corrosion of the plating film, and it is possible to suppress the variation of the resistor shape and film thickness, that is, the resistance value. Further, since the resistance layer is formed on the entire surface by electroless plating, variations in plating thickness due to the area of the resistance element can be suppressed.

In the present invention, since the resistance element is formed between the wiring patterns on the insulating substrate by plating after the wiring pattern is formed, it is not necessary to go through a process that causes oxidation or corrosion of the resistance layer. Variation can be suppressed.
Further, since the resistance layer is formed on the entire surface by plating, variations in plating thickness due to the area of the resistance element, that is, fluctuations in resistance value can be suppressed.

Hereinafter, embodiments of the present invention will be described in detail.
1 (a) to 1 (e) and FIGS. 2 (f) to 2 (j) are schematic cross-sectional views showing an embodiment of a method for producing a passive element built-in wiring board according to claim 1. FIG.
First, the wiring patterns 21a and 21b are formed on both surfaces of the insulating substrate 11, and the double-sided wiring board 10 is manufactured (see FIG. 1A).
As a method for forming the wiring pattern, any of a subtractive method, a semi-additive method by plating, and a full additive method may be used.

Next, the insulating layer 31 is formed by a method of laminating and heating a resin film on both surfaces of the double-sided wiring board 10 (see FIG. 1B).
Next, drilling is performed by laser processing or the like to form a via hole 32 at a predetermined position of the insulating layer 31 (see FIG. 1C).

  Next, a desmear process and an activation process in the via hole 32 are performed, and a plating base conductive layer (not shown) is formed on the insulating layer 31 and in the via hole 32 by electroless copper plating or the like. . Further, a photosensitive layer is formed by a method such as laminating a dry film, and a series of patterning processes such as pattern exposure and development are performed to form resist patterns 41 and 42 (see FIG. 1D).

  Next, electrolytic copper plating is performed using the plating base conductive layer as a cathode to form a conductor layer 51 and a via 52 having a predetermined thickness (see FIG. 1E).

Next, the resist patterns 41 and 42 are stripped with a dedicated stripping solution, and the plating base conductive layer under the resist patterns 41 and 42 is removed by flash etching, and the wiring pattern 51a and the element electrode are formed on one surface. 51c and a pad electrode 51b are formed on the other surface (see FIG. 2F).
Here, the resistor formation region at the tip of the wiring pattern 51a is referred to as a device electrode 51c.

Next, the photosensitive layer 43 is formed by a method such as laminating a dry film (see FIG. 2G).
Further, a series of patterning processes such as pattern exposure and development are performed to form a resist pattern 43a and a resist 43c in which an opening (resistor forming region) 43b is formed at a predetermined position of the photosensitive layer 43 (FIG. 2 (h) )reference).

  Next, activation processing is performed on the resist pattern 43a and the opening (resistor forming region) 43b, and nickel / phosphorous binary is formed on the resist pattern 43a and the opening (resistor forming region) 43b by electroless plating. A resistance layer 61 made of a nickel alloy or a nickel-phosphorus ternary alloy film is formed (see FIG. 2I).

Next, the resist patterns 43a and 43c are stripped with a dedicated stripping solution to produce a resistance element 60 in which a resistor 61a is formed between the element electrodes 51c at the tip of the wiring pattern 51a, and is formed on one surface of the wiring board. The wiring pattern 51a and the resistance element 60 obtain a four-layer passive element built-in wiring board 100 in which the pad electrode 51b is formed on the other surface (see FIG. 2J).
Here, a four-layer multilayer wiring board has been described as an example of a wiring board with a built-in passive element, but the number of wiring patterns on the wiring board is not limited.

3 (a) to 3 (e) and FIGS. 4 (f) to 4 (j) are schematic cross-sectional views showing an embodiment of a manufacturing method of a passive element built-in wiring board according to claim 2.
First, the wiring patterns 21a and 21b are formed on both surfaces of the insulating substrate 11, and the double-sided wiring board 10 is manufactured (see FIG. 3A).
As a method for forming the wiring pattern, any of a subtractive method, a semi-additive method by plating, and a full additive method may be used.

Next, the insulating layer 31 is formed by a method of laminating and heating resin films on both surfaces of the double-sided wiring board 10 (see FIG. 3B).
Next, drilling is performed by laser processing or the like to form a via hole 32 at a predetermined position of the insulating layer 31 (see FIG. 3C).

  Next, a desmear process and an activation process in the via hole 32 are performed, and a plating base conductive layer (not shown) is formed on the insulating layer 31 and in the via hole 32 by electroless copper plating or the like. . Further, a photosensitive layer is formed by a method such as laminating a dry film, and a series of patterning processes such as pattern exposure and development are performed to form resist patterns 41 and 42 (see FIG. 3D).

Next, electrolytic copper plating is performed using the plating base conductive layer as a cathode to form a conductor layer 51 and a via 52 having a predetermined thickness (see FIG. 3E).
Next, the resist patterns 41 and 42 are stripped with a dedicated stripping solution, and the plating base conductive layer located under the resist patterns 41 and 42 is removed by flash etching. 51c and a pad electrode 51b are formed on the other surface (see FIG. 4F).
Here, the resistor formation region at the tip of the wiring pattern 51a is referred to as a device electrode 51c.

  Next, a catalyst is applied and activated on the wiring pattern 51a and the insulating layer 31, and nickel / phosphorus binary alloy or nickel / phosphorus ternary is formed on the wiring pattern 51a and insulating layer 31 by electroless plating. A resistance layer 62 made of a system alloy film is formed (see FIG. 4G).

  Next, a photosensitive layer 45 is formed on the resistance layer 62 by a method such as laminating a dry film (see FIG. 4H), and a series of patterning processes such as pattern exposure and development are performed to form a resist pattern 45a. It forms (refer FIG.4 (i)).

Next, the resistance layer 62 is removed by etching using the resist pattern 45a as a mask. The etching solution for the resistance layer 62 is preferably an acidic nickel etching solution so that the resist pattern 45a can withstand.
Further, the resist pattern 45a and the resist 44 are stripped with a dedicated stripping solution to produce a resistance element 60 in which a resistor 62a is formed between the element electrodes 51c at the tip of the wiring pattern 51a. A four-layer passive element built-in wiring board 200 having a wiring pattern 51a and a resistance element 60 on the surface and a pad electrode 51b on the other surface is obtained (see FIG. 2J).
Here, a four-layer multilayer wiring board has been described as an example of a wiring board with a built-in passive element, but the number of wiring patterns on the wiring board is not limited.

  First, a double-sided copper-clad laminate in which 18 μm-thick copper foil is laminated on both sides of an insulating base material 11 made of BT (bismaleimide triazine) resin having a thickness of 0.4 mm is used. The mixture was treated with an aqueous ammonium sulfate solution and a 10 vol% sulfuric acid aqueous solution, washed with water and dried. Next, a negative dry film resist (RY-3215: manufactured by Hitachi Chemical Co., Ltd.) is laminated to form a photosensitive layer, pattern exposure is performed with a photomask, and a developer composed of a 1% aqueous sodium carbonate solution at 30 ° C. A resist pattern was formed by developing the resist pattern. Furthermore, using the resist pattern as a mask, the copper foil is etched with ferric chloride solution (45 ° C., specific gravity 1.4), and the resist pattern is peeled off with a stripping solution (3% sodium hydroxide aqueous solution, 40 ° C.). Patterns 21a and 21b were formed to produce a double-sided wiring board 10 (see FIG. 1A).

Next, an epoxy insulating resin sheet was vacuum-pressurized and laminated on both sides of the double-sided wiring board 10 to form an insulating layer 31 (see FIG. 1B).
Next, drilling is performed by laser processing to form a via hole 32 at a predetermined position of the insulating layer 31, and a desmear process and an activation process in the via hole 32 are performed, and an insulating layer is formed by electroless copper plating. A plating base conductive layer (not shown) was formed on 31 and in via hole 32 (see FIG. 1C).

  Next, a negative dry film resist (RY-3215: manufactured by Hitachi Chemical Co., Ltd.) is laminated to form a photosensitive layer, pattern exposure is performed through a photomask, and a developer composed of a 1% sodium carbonate aqueous solution at 30 ° C. is used. Then, development processing was performed to form resist patterns 41 and 42 (see FIG. 1D).

  Next, electrolytic copper plating was performed using the plating base conductive layer as a cathode to form a conductor layer 51 and a via 52 having a thickness of 15 μm (see FIG. 1E).

  Next, the resist patterns 41 and 42 are stripped with a dedicated stripping solution, and the plating base conductive layer under the resist patterns 41 and 42 is removed by flash etching, and the wiring pattern 51a and the element electrode are formed on one surface. 51c and pad electrode 51b were formed on the other surface (see FIG. 2 (f)).

Next, a negative dry film resist (RY-3215: manufactured by Hitachi Chemical Co., Ltd.) was laminated to form a photosensitive layer 43 (see FIG. 2G).
Further, a series of patterning processes such as pattern exposure and development are performed to form a resist pattern 43a and a resist 43c in which an opening (resistor forming region) 43b is formed at a predetermined position of the photosensitive layer 43 (FIG. 2 (h) )reference).

  Next, a Pd catalyst is applied on the resist pattern 43a and in the opening (resistor formation region) 43b with a Pd—Sn colloid solution (OPC80 catalyst: manufactured by Okuno Pharmaceutical Co., Ltd.), and an activator (OPC555 accelerator M: It was activated using Okuno Seiyaku Kogyo). Furthermore, electroless plating is performed on the resist pattern 43a and in the opening (resistor forming region) 43b with an electroless nickel / phosphorus alloy plating solution (Top Nicolon NAC: manufactured by Okuno Pharmaceutical Co., Ltd.). A resistance layer 61 made of a nickel-phosphorus binary alloy film was formed (see FIG. 2 (i)).

  Next, the resist patterns 43a and 43c are peeled off with a 3% aqueous sodium hydroxide solution heated to 40 ° C. to produce a resistance element 60 in which a resistor 61a is formed between the element electrodes 51c at the tip of the wiring pattern 51a. A four-layer passive element built-in wiring board 100 having a wiring pattern 51a and a resistance element 60 formed on one surface of the wiring board and a pad electrode 51b formed on the other surface was obtained (see FIG. 2J).

  First, a double-sided copper-clad laminate in which 18 μm-thick copper foil is laminated on both sides of an insulating base material 11 made of BT (bismaleimide triazine) resin having a thickness of 0.4 mm is used. The mixture was treated with an aqueous ammonium sulfate solution and a 10 vol% sulfuric acid aqueous solution, washed with water and dried. Next, a negative dry film resist (RY-3215: manufactured by Hitachi Chemical Co., Ltd.) is laminated to form a photosensitive layer, pattern exposure is performed with a photomask, and a developer composed of a 1% aqueous sodium carbonate solution at 30 ° C. A resist pattern was formed by developing the resist pattern. Furthermore, using the resist pattern as a mask, the copper foil is etched with ferric chloride solution (45 ° C., specific gravity 1.4), and the resist pattern is peeled off with a stripping solution (3% sodium hydroxide aqueous solution, 40 ° C.). Patterns 21a and 21b were formed to produce a double-sided wiring board 10 (see FIG. 3A).

Next, an epoxy insulating resin sheet was vacuum-pressurized and laminated on both surfaces of the double-sided wiring board 10 to form an insulating layer 31 (see FIG. 3B).
Next, drilling is performed by laser processing to form a via hole 32 at a predetermined position of the insulating layer 31, and a desmear process and an activation process in the via hole 32 are performed, and an insulating layer is formed by electroless copper plating. A plating base conductive layer (not shown) was formed on 31 and in the via hole 32 (see FIG. 3C).

Next, a negative dry film resist (RY-3215: manufactured by Hitachi Chemical Co., Ltd.) is laminated to form a photosensitive layer, pattern exposure is performed through a photomask, and a developer composed of a 1% sodium carbonate aqueous solution at 30 ° C. is used. Then, development processing was performed to form resist patterns 41 and 42 (see FIG. 3D).

  Next, electrolytic copper plating was performed using the plating base conductive layer as a cathode to form a conductor layer 51 and a via 52 having a thickness of 15 μm (see FIG. 3E).

  Next, the resist patterns 41 and 42 are stripped with a dedicated stripping solution, and the plating base conductive layer under the resist patterns 41 and 42 is removed by flash etching, and the wiring pattern 51a and the element electrode are formed on one surface. 51c and pad electrode 51b were formed on the other surface (see FIG. 4F).

Next, the wiring pattern 51a and the insulating layer 31 are washed with a conditioning cleaner (OPC-380 Condy Clean M: manufactured by Okuno Pharmaceutical Co., Ltd.), and with a Pd-Sn colloid solution (OPC-80 catalyst: manufactured by Okuno Pharmaceutical Co., Ltd.). A Pd catalyst was applied, and activation treatment was performed using an activator (OPC-555 accelerator M: manufactured by Okuno Pharmaceutical Co., Ltd.).
Further, the electroless nickel / phosphorus alloy plating solution (Top Nicolon NAC: manufactured by Okuno Pharmaceutical Co., Ltd.) is electrolessly plated on the wiring pattern 51a and the insulating layer 31 to form a 0.3 μm thick nickel / phosphorus binary alloy. A resistance layer 62 made of a film was formed (see FIG. 4G).

Next, a negative dry film resist (RY-3215: manufactured by Hitachi Chemical Co., Ltd.) was laminated on the resistance layer 62 to form a photosensitive layer 45 (see FIG. 4H).
Further, a series of patterning processes such as pattern exposure and development were performed to form a resist pattern 45a (see FIG. 2H).

Next, using the resist pattern 45a as a mask, the resistance layer 62 was etched with an acidic nickel etching solution.
Further, the resist pattern 45a and the resist 44 are stripped with a 3% aqueous sodium hydroxide solution heated to 40 ° C. to produce a resistance element 60 in which a resistor 62a is formed between the element electrodes 51c at the tip of the wiring pattern 51a. As a result, a four-layer passive element built-in wiring substrate 200 in which the wiring pattern 51a and the resistance element 60 were formed on one surface of the wiring substrate and the pad electrode 51b was formed on the other surface was obtained (see FIG. 2 (j)).

(A)-(e) is explanatory drawing which shows a part of process in the manufacturing method of this invention of the wiring board 100 with a built-in passive element. (F)-(j) is explanatory drawing which shows a part of process in the manufacturing method of this invention of the wiring board 100 with a built-in passive element. (A)-(e) is explanatory drawing which shows a part of process in the manufacturing method of this invention of the wiring board 200 with a built-in passive element. (F)-(j) is explanatory drawing which shows a part of process in the manufacturing method of this invention of the wiring board 200 with a built-in passive element.

Explanation of symbols

10 ... Double-sided wiring board 11 ... Insulating base material 21a, 21b ... Wiring pattern 31 ... Insulating layer 32 ... Via hole 41, 42, 43a, 45a ... Resist pattern 43 ... Photosensitive layer 43b ... Opening Part (resistor formation region)
43c, 44 ... resist 51 ... conductor layer 52 ... via 51a ... wiring pattern 51b ... pad electrode 51c ... element electrode 60 ... resistance elements 61, 62 ... resistance layers 61a, 62a ... resistance element 100 200 …… Wiring board with built-in passive element

Claims (4)

In the manufacturing method of the multilayer printed wiring board which incorporates the resistive element which consists of a resistor and an element electrode as a passive element, it comprises at least the following processes (a)-( j ), The passive element built-in printed wiring characterized by the above-mentioned A manufacturing method of a board.
(A) A step of forming a double-sided wiring board by forming a wiring pattern on both sides of an insulating substrate.
(B) A step of forming insulating layers on both sides of the double-sided wiring board.
(C) A step of forming a via hole in the insulating layer.
(D) A step of forming a plating base conductive layer in the insulating layer and the via hole, and further forming a resist pattern.
(E) A step of forming a conductor layer and a via by performing electrolytic copper plating using the plating base conductive layer as a cathode.
(F) A step of removing the resist pattern, further removing the plating base conductive layer below the resist pattern, forming a wiring pattern and an element electrode on one surface, and forming a pad electrode on the other surface.
(G) forming a photosensitive layer on the wiring pattern and the insulating layer, and further forming a photosensitive layer on the pad electrode and the insulating layer;
(H) The photosensitive layer formed on the pad electrode and the insulating layer obtained by forming the resist pattern having an opening in the photosensitive layer formed on the wiring pattern and the insulating layer obtained by the step. Forming a resist on the substrate.
(I) A step of forming a resistance layer on the resist pattern and in the opening.
(J) A step of peeling the resist pattern and the resist, forming a resistance element in which a resistor is formed between the element electrodes on one surface, and forming a pad electrode on the other surface. In the manufacturing method of the multilayer printed wiring board which incorporates the resistive element which consists of a resistor and an element electrode as a passive element, it comprises at least the following processes (a)-( j ), The passive element built-in printed wiring characterized by the above-mentioned A manufacturing method of a board.
(A) A step of forming a double-sided wiring board by forming a wiring pattern on both sides of an insulating substrate.
(B) A step of forming insulating layers on both sides of the double-sided wiring board.
(C) A step of forming a via hole in the insulating layer.
(D) A step of forming a plating base conductive layer on the insulating layer and in the via hole, and further forming a resist pattern.
(E) A step of forming a conductor layer and a via by performing electrolytic copper plating using the plating base conductive layer as a cathode.
(F) A step of removing the resist pattern, further removing the plating base conductive layer below the resist pattern, forming a wiring pattern and an element electrode on one surface, and forming a pad electrode on the other surface.
(G) forming a resistance layer on the wiring pattern and the insulating layer, and further forming a resist on the pad electrode and the insulating layer;
(H) A step of forming a photosensitive layer on the resistance layer.
(I) A step of forming a resist pattern on the photosensitive layer.
(J) removing the resistance layer using the resist pattern as a mask, further peeling the resist pattern and the resist, and forming a resistance element in which a resistor is formed between the element electrodes on one surface; Forming a pad electrode on the other surface;   The method for manufacturing a printed wiring board with a built-in passive element according to claim 1, wherein the resistance layer is formed by plating.   The method for manufacturing a printed wiring board with a built-in passive element according to any one of claims 1 to 3, wherein the resistance layer is a nickel-phosphorus binary alloy or a nickel-phosphorus ternary alloy.

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