JP4645212B2 - Wiring circuit board built-in resistance element - Google Patents

Wiring circuit board built-in resistance element Download PDF

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JP4645212B2
JP4645212B2 JP2005030164A JP2005030164A JP4645212B2 JP 4645212 B2 JP4645212 B2 JP 4645212B2 JP 2005030164 A JP2005030164 A JP 2005030164A JP 2005030164 A JP2005030164 A JP 2005030164A JP 4645212 B2 JP4645212 B2 JP 4645212B2
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resistor
resistance element
resistance
circuit board
water vapor
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明子 佐伯
達広 岡野
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Toppan Inc
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Description

本発明は、配線回路板内に組み込まれる基板内蔵抵抗体に関する。   The present invention relates to a substrate built-in resistor incorporated in a printed circuit board.

電子機器の小型化、高密度化、高性能化が進んでいる。そして、電子機器内に組み込まれる配線回路板も小型化、高密度化、高速化の要求が高まっており、それらの要求を満たした配線回路板が求められている。   Electronic devices are becoming smaller, higher density, and higher performance. And the demand for miniaturization, high density, and high speed is increasing for the wiring circuit board incorporated in the electronic device, and a wiring circuit board that satisfies these requirements is demanded.

従来、配線回路板には半導体チップ、抵抗体、キャパシタ、インダクタ等の部品を表面実装し、実装する部品を小型化することで配線回路板の小型化、高密度化対応を図っている。   Conventionally, components such as a semiconductor chip, a resistor, a capacitor, and an inductor are surface-mounted on a wiring circuit board, and the components to be mounted are miniaturized to reduce the size and density of the wiring circuit board.

しかしながら、表面実装だけでは限界があり、さらなる部品実装密度の向上が求められ、抵抗体、キャパシタ、インダクタ等の部品を内蔵した部品内蔵の配線回路板の開発が進められている。   However, there is a limit to surface mounting alone, and further improvement in component mounting density is required, and development of wiring circuit boards with built-in components that incorporate components such as resistors, capacitors, and inductors is underway.

配線回路板の内部に抵抗体を形成する手法として、絶縁基材上に銅配線により電極を形成し、その電極間にカーボンフィラーと樹脂を混合してなる抵抗ペーストを印刷・焼成し形成する手法が、特許文献1に報告されている。   As a method for forming a resistor inside a printed circuit board, a method is used in which an electrode is formed by copper wiring on an insulating substrate, and a resistance paste formed by mixing a carbon filler and a resin is printed and fired between the electrodes. Is reported in Patent Document 1.

しかしながら、従来の抵抗ペーストの素子においては、絶縁樹脂基材の表面に樹脂を含む抵抗ペーストにより抵抗素子を形成し、各種トリミングにより設計値±1%以内に調整するにも関らず、その後、抵抗体を構成する樹脂の吸湿により抵抗値が増加する問題があった。   However, in the conventional resistance paste element, the resistance element is formed with a resistance paste containing a resin on the surface of the insulating resin base material and adjusted to within a design value ± 1% by various trimmings. There was a problem that the resistance value increased due to moisture absorption of the resin constituting the resistor.

そこで、抵抗体の吸湿による抵抗値変動を抑える方法として抵抗体を絶縁材料でコーティングする手法が特許文献2および3に報告されている。   Therefore, Patent Documents 2 and 3 report a method of coating a resistor with an insulating material as a method of suppressing resistance value fluctuation due to moisture absorption of the resistor.

しかしながら、エポキシ樹脂等によるコーティングでは、コーティング材料自体が有機材料であり吸湿するため、防湿の効果は不十分である。コーティング材料にSiOなどの無機材料を使用した場合は、抵抗体表面からの吸湿を抑えることが可能である。 However, in coating with an epoxy resin or the like, the coating material itself is an organic material and absorbs moisture, so that the moisture-proofing effect is insufficient. When an inorganic material such as SiO 2 is used as the coating material, moisture absorption from the resistor surface can be suppressed.

しかしながら、吸湿は抵抗体の表面からのみでなく素子の形成されている絶縁基材、すなわち下面からも起こるため、表面のオーバーコートのみでは抵抗値が変動してしまう問題があった。
特許第2835451号公報 特開平02−309692号公報 特開平11−4056号公報
However, moisture absorption occurs not only from the surface of the resistor but also from the insulating base material on which the element is formed, that is, from the lower surface, so that there is a problem that the resistance value fluctuates only by the overcoat on the surface.
Japanese Patent No. 2835451 Japanese Patent Laid-Open No. 02-309692 Japanese Patent Laid-Open No. 11-4056

本発明はこのような事情に鑑みてなされたものであり、吸湿による抵抗値の変動の小さい基板内蔵抵抗素子を提供することを目的とする。   The present invention has been made in view of such circumstances, and an object of the present invention is to provide a resistance element with a built-in substrate in which a resistance value variation due to moisture absorption is small.

本発明において上記課題を解決するために、請求項1に係る発明は配線回路板に内蔵して用いられる抵抗素子において、カーボンブラック及び樹脂を含有する抵抗ペーストからなる抵抗体と絶縁基板との間に無電解ニッケル・リン・鉄合金めっきよりなる水蒸気バリア層を備えたことを特徴とする抵抗素子とした。 In order to solve the above-mentioned problems in the present invention, the invention according to claim 1 is a resistance element built in a wiring circuit board, and is provided between a resistor made of a resistance paste containing carbon black and resin and an insulating substrate. And a water vapor barrier layer made of electroless nickel / phosphorus / iron alloy plating .

請求項2に係る発明は、前記水蒸気バリア層において前記抵抗体と重なり合っている部分の抵抗値が前記抵抗体の抵抗値の100倍以上であることを特徴とする請求項1記載の抵抗素子とした。   The invention according to claim 2 is characterized in that the resistance value of the portion of the water vapor barrier layer that overlaps the resistor is 100 times or more the resistance value of the resistor. did.

請求項3に係る発明は、前記抵抗体の表面がオーバーコート層で覆われていることを特徴とする請求項1または2に記載の抵抗素子とした。 The invention according to claim 3 is the resistance element according to claim 1 or 2, wherein the surface of the resistor is covered with an overcoat layer .

請求項4に係る発明は、前記オーバーコート層が無機材料であることを特徴とする請求項3に記載の抵抗素子とした。 The invention according to claim 4 is the resistance element according to claim 3 , wherein the overcoat layer is an inorganic material .

請求項5に係る発明は、請求項1乃至4のいずれかに記載の抵抗素子を内蔵した配線回路板とした。 The invention according to claim 5 is a printed circuit board in which the resistance element according to any one of claims 1 to 4 is incorporated .

請求項6に係る発明は、前記導電性物質がカーボンブラックであることを特徴とする請求項1乃至5のいずれかに記載の抵抗素子とした。   The invention according to claim 6 is the resistance element according to any one of claims 1 to 5, wherein the conductive substance is carbon black.

請求項7に係る発明は、請求項1乃至6記載の抵抗素子を内蔵した配線回路板とした。   The invention according to claim 7 is a printed circuit board in which the resistance element according to any one of claims 1 to 6 is incorporated.

本発明において水蒸気バリア層を絶縁基材と抵抗体の間に設けることによって、抵抗体の基板からの吸湿を防ぐことができた。また、水蒸気バリア層とオーバーコート層で抵抗体の上下を挟むことによって抵抗体全体の吸湿を抑えることができ、抵抗素子の抵抗値の上昇のない信頼性の高い配線基板を得ることができた。   In the present invention, it is possible to prevent moisture absorption from the substrate of the resistor by providing the water vapor barrier layer between the insulating base material and the resistor. In addition, moisture absorption of the entire resistor can be suppressed by sandwiching the upper and lower sides of the resistor between the water vapor barrier layer and the overcoat layer, and a highly reliable wiring board without an increase in the resistance value of the resistor element can be obtained. .

以下本発明の実施形態を説明する。   Embodiments of the present invention will be described below.

図1は本発明の抵抗体、金属酸化膜、オーバーコート及び電極で構成される抵抗素子を有する基板の一例を示す断面図である。絶縁基材11上に銅配線32があり、銅配線32の間に銀ペースト51がある。この銀ペースト51の間に抵抗体52があり、抵抗体52の下には水蒸気バリア層21、抵抗体52の上にはオーバーコート層22がある。水蒸気バリア層21とオーバーコート層22は、少なくとも抵抗体52を覆っていればよい。抵抗体52の上下には任意の数の配線層を形成することが可能である。なお、本発明では絶縁基材が樹脂である場合に、その効果が顕著となる。   FIG. 1 is a cross-sectional view showing an example of a substrate having a resistance element composed of a resistor, a metal oxide film, an overcoat and an electrode of the present invention. There is a copper wiring 32 on the insulating substrate 11, and a silver paste 51 is present between the copper wirings 32. There is a resistor 52 between the silver paste 51, the water vapor barrier layer 21 under the resistor 52, and the overcoat layer 22 over the resistor 52. The water vapor barrier layer 21 and the overcoat layer 22 only need to cover at least the resistor 52. An arbitrary number of wiring layers can be formed above and below the resistor 52. In the present invention, when the insulating base material is a resin, the effect becomes remarkable.

本発明における水蒸気バリア層21としては、前記抵抗体52と重なり合っている部分の抵抗値が前記抵抗体52の抵抗値の100倍以上であれば特に限定されるものではない。水蒸気バリア層の抵抗体下の抵抗値が抵抗体の抵抗値と比較して100倍以上であれば、設計された抵抗体の抵抗値に影響は与えない。水蒸気バリア層としては具体的には金属酸化物といった金属化合物、SiO等のセラミック膜が挙げられる。これら水蒸気バリア層の形成方法としては特に制限されるべきものではなく、従来公知の各種薄膜形成技術、塗装・塗膜形成技術等を適宜利用することができるものである。薄膜形成技術としては真空蒸着法、スパッタ蒸着法、イオンプレーティング法といった物理的競う成長法(PVD)や化学的気相成長法(CVD)といった真空中でおこなう方法とスピンコート法、ディップコート法、ロールコート法、スプレーコート法やめっき法などの大気中で行なう方法が挙げられる。なお、水蒸気バリア層の膜厚は0.02μm以上が好ましい。0.02μm以下の場合は十分な水蒸気バリア性能を得ることができない。水蒸気バリア層の膜厚およびコスト面を考慮すると、無電解めっき法を用いて水蒸気バリア層を形成する方法が好適である。めっき液にはニッケル・リン系が好ましく、具体的にはニッケル・リン・鉄、ニッケル・リン・タングステン、ニッケル・リン・モリブデン、ニッケル・リン・レニウム・ニッケル・リン・クロムを用いることができる。 The water vapor barrier layer 21 in the present invention is not particularly limited as long as the resistance value of the portion overlapping the resistor 52 is 100 times or more the resistance value of the resistor 52. If the resistance value under the resistor of the water vapor barrier layer is 100 times or more compared to the resistance value of the resistor, the resistance value of the designed resistor is not affected. Specific examples of the water vapor barrier layer include metal compounds such as metal oxides and ceramic films such as SiO 2 . The method for forming these water vapor barrier layers is not particularly limited, and various conventionally known thin film forming techniques, coating / coating film forming techniques, and the like can be appropriately used. Thin film formation techniques include vacuum deposition, sputter deposition, ion plating, physical competing growth (PVD), chemical vapor deposition (CVD), vacuum coating, spin coating, and dip coating. And a method of performing in air such as a roll coating method, a spray coating method and a plating method. The film thickness of the water vapor barrier layer is preferably 0.02 μm or more. In the case of 0.02 μm or less, sufficient water vapor barrier performance cannot be obtained. In consideration of the film thickness and cost of the water vapor barrier layer, a method of forming the water vapor barrier layer using an electroless plating method is preferable. The plating solution is preferably nickel / phosphorus, and specifically nickel / phosphorus / iron, nickel / phosphorus / tungsten, nickel / phosphorus / molybdenum, nickel / phosphorus / rhenium / nickel / phosphorus / chromium can be used.

導電性物質を有する樹脂ペーストからなる抵抗体52において導電性物質としてはアセチレンブラック、ファーネスブラック、サーマルブラック、グラファイト等の安価なカーボンブラックが好ましい。また、樹脂成分としてはエポキシ樹脂、フェノール樹脂、ポリイミド樹脂等が挙げられるが、特にこれに限定されるものではない。また、導電性フィラーの他に印刷性や安定性を高めるため、無機フィラーが添加されていてもよい。また、抵抗体の形成方法としては各種印刷法が挙げられるが、中でもスクリーン印刷が好適である。   In the resistor 52 made of a resin paste having a conductive substance, the conductive substance is preferably an inexpensive carbon black such as acetylene black, furnace black, thermal black, or graphite. Examples of the resin component include an epoxy resin, a phenol resin, and a polyimide resin, but are not particularly limited thereto. In addition to the conductive filler, an inorganic filler may be added in order to improve printability and stability. In addition, as a method for forming the resistor, various printing methods may be mentioned, and among these, screen printing is preferable.

オーバーコート層22としては、水蒸気透過率が低く、絶縁性の高い材料が好ましく、ポリシラザン系、特に低温、例えば260℃以下で硬化可能なポリシラザン系材料が好ましい。また、オーバーコート形成方法としては各種薄膜形成技術、各種塗装・塗膜形成技術を適宜利用することができる。   As the overcoat layer 22, a material having a low water vapor transmission rate and a high insulating property is preferable, and a polysilazane material, particularly a polysilazane material curable at a low temperature, for example, 260 ° C. or less is preferable. As the overcoat forming method, various thin film forming techniques and various coating / coating film forming techniques can be used as appropriate.

次に本発明の抵抗体内蔵配線回路板の製造方法について説明する。図2に本発明の抵抗素子内蔵配線回路板の製造方法の一例として第一の実施形態を示す。   Next, the manufacturing method of the resistor built-in wiring circuit board of this invention is demonstrated. FIG. 2 shows a first embodiment as an example of a method for manufacturing a resistance element built-in wiring circuit board according to the present invention.

まず、絶縁基材11の片面に適切な前処理をし無電解ニッケル・リン・鉄合金めっきをおこない、過硫酸アンモニウム水溶液でソフトエッチングし十分に高抵抗となる様、膜厚を調整することにより水蒸気バリア層21を形成する(図2(a)参照)。
続いて、適切な前処理を行い無電解銅めっきにより薄膜導体層を形成する(図示せず)。この薄膜導体層を陰極とし電解銅めっきにより導体層31を形成する(図2(b)参照)。導体層31上に、ドライフィルムを貼り合わせる等の方法で感光層(レジスト)を形成し、露光、現像等の一連のパターニング処理を行って、レジストパターン41を形成する(図2(c)参照)。次に、レジストパターン41をマスクにして、導体層31をエッチング処理し、レジストパターン41を専用の剥離液で除去して、絶縁基材11上に銅配線32を形成する(図2(d)参照)。
First, an appropriate pretreatment is performed on one surface of the insulating base material 11, electroless nickel / phosphorus / iron alloy plating is performed, and water vapor is obtained by adjusting the film thickness so that soft etching is performed with an ammonium persulfate aqueous solution and the resistance becomes sufficiently high. A barrier layer 21 is formed (see FIG. 2A).
Subsequently, an appropriate pretreatment is performed to form a thin film conductor layer by electroless copper plating (not shown). Using this thin film conductor layer as a cathode, a conductor layer 31 is formed by electrolytic copper plating (see FIG. 2B). A photosensitive layer (resist) is formed on the conductor layer 31 by a method such as bonding a dry film, and a series of patterning processes such as exposure and development are performed to form a resist pattern 41 (see FIG. 2C). ). Next, using the resist pattern 41 as a mask, the conductor layer 31 is etched, and the resist pattern 41 is removed with a special stripping solution to form a copper wiring 32 on the insulating substrate 11 (FIG. 2D). reference).

その後抵抗素子を形成する部分以外に再度レジストパターン42を形成し(図2(e)参照)、抵抗素子部に銅を選択的にエッチングする液(アルカリエッチング液)を使用して抵抗体部分の銅を除去する(図2(f)参照)。   Thereafter, a resist pattern 42 is formed again in addition to the portion where the resistance element is formed (see FIG. 2E), and a solution for selectively etching copper (alkali etching solution) is used for the resistance element portion. Copper is removed (see FIG. 2 (f)).

この抵抗体部に銅電極33間をつなぐように抵抗ペーストをスクリーン印刷・焼成し抵抗体52を形成する。このとき抵抗ペーストと銅電極との間の接触抵抗を小さくするため銀ペースト51または銀めっきを挟むのが望ましい(図2(g)(h)参照)。このように形成した抵抗体の表面にオーバーコート層22をコーティングする。これらの工程で本発明の基板内蔵抵抗素子60を形成することができる(図2(i)参照)。さらに、この上に絶縁樹脂12を積層し、レザー加工による穴あけなど通常のプリント配線基板の多層化工程を行うことで、本発明の抵抗素子内蔵配線回路板100を得ることができる(図2(j)参照)。   A resistor paste is screen-printed and fired so as to connect between the copper electrodes 33 to the resistor portion to form the resistor 52. At this time, it is desirable to sandwich the silver paste 51 or silver plating in order to reduce the contact resistance between the resistance paste and the copper electrode (see FIGS. 2G and 2H). The overcoat layer 22 is coated on the surface of the resistor thus formed. The substrate built-in resistor element 60 of the present invention can be formed by these steps (see FIG. 2 (i)). Further, the insulating resin 12 is laminated thereon, and a normal printed wiring board multilayering process such as drilling by leather processing is performed to obtain the resistance element built-in wiring circuit board 100 of the present invention (FIG. 2 ( j)).

図3に本発明の抵抗体内蔵配線回路板の製造方法の一例として第二の実施形態を示す。まず、絶縁基材11と導体層31からなる銅貼積層板13(図3(a)参照)上に、ドライフィルムを貼り合わせる等の方法で感光層(レジスト)を形成し、露光、現像等の一連のパターニング処理を行って、レジストパターン41を形成する。(図3(b)参照) 次に、レジストパターン41をマスクにして、導体層31をエッチング処理し、レジストパターン41を専用の剥離液で除去して、絶縁基材11上に銅配線32および銅電極33を形成する。(図3(c)参照)   FIG. 3 shows a second embodiment as an example of a method of manufacturing a resistor built-in wiring circuit board according to the present invention. First, a photosensitive layer (resist) is formed on a copper-clad laminate 13 (see FIG. 3A) composed of an insulating base material 11 and a conductor layer 31 by a method such as bonding a dry film, and exposure, development, etc. The resist pattern 41 is formed by performing a series of patterning processes. (See FIG. 3B.) Next, using the resist pattern 41 as a mask, the conductor layer 31 is etched, the resist pattern 41 is removed with a special stripping solution, and the copper wiring 32 and A copper electrode 33 is formed. (See Fig. 3 (c))

その後、抵抗素子を形成する部分以外に再度レジストパターン42を形成し(図3(d)参照)、水蒸気バリア層21を形成する。(図3(e)参照) レジストパターン42を専用の剥離液で除去する。(図3(f)参照)   Thereafter, a resist pattern 42 is formed again other than the portion where the resistance element is formed (see FIG. 3D), and the water vapor barrier layer 21 is formed. (See FIG. 3E) The resist pattern 42 is removed with a special stripping solution. (See Fig. 3 (f))

抵抗体部に銅電極33間をつなぐように抵抗ペースト52をスクリーン印刷・焼成し抵抗素子を形成する。このとき抵抗体と銅電極との間の接触抵抗を小さくするため銀ペースト51または銀めっきを挟むのが望ましい。(図3(g)(h)参照)このように形成した抵抗素子の表面にSiOなどの無機絶縁膜22をコーティングする。これらの工程で本発明の基板内蔵抵抗素子60を形成することができる。(図3(i)参照)さらに、この上に絶縁樹脂12を積層し、レザー加工による穴あけなど通常のプリント配線基板の多層化工程を行うことで、本発明の抵抗素子内蔵配線回路板100を得ることができる。(図3(j)参照) Resistive paste 52 is screen-printed and fired so as to connect between the copper electrodes 33 to the resistor portion, thereby forming a resistance element. At this time, it is desirable to sandwich the silver paste 51 or silver plating in order to reduce the contact resistance between the resistor and the copper electrode. (See FIGS. 3G and 3H) The surface of the resistance element formed in this way is coated with an inorganic insulating film 22 such as SiO 2 . The substrate built-in resistance element 60 of the present invention can be formed by these steps. (Refer to FIG. 3 (i)) Furthermore, the insulating resin 12 is laminated thereon, and a multilayered process of a normal printed wiring board such as drilling by leather processing is performed, whereby the resistance element built-in wiring circuit board 100 of the present invention is obtained. Obtainable. (See Fig. 3 (j))

以下、実施例について詳細に説明する。まず、絶縁基材をコンディショニングクリーナー(奥野製薬工業製:OPC−380コンディクリーンM)で洗浄し、触媒付与(奥野製薬工業製:OPC−80キャタリスト)、活性化処理(奥野製薬工業製:OPC−555アクセレーターM)の前処理を施した。次に、無電解ニッケル・リン・鉄合金めっき液で0.3μmほどめっきした。搭載する抵抗体の設計値に対してめっき膜の抵抗値が十分高くなる様、5g/L過硫酸アンモニウム水溶液にて20分間ディップエッチングし、無電解ニッケル・リン・鉄合金めっきの膜厚を0.2μmに調整した。このようにして水蒸気バリア層を形成した。次に、無電解銅めっき(シプレイ・ファーイースト CUPOSIT)により薄膜導体層を形成する。このとき無電解銅めっき厚は1μm程度あればよい。この薄膜導体層を陰極とし2A/dmで30分間、電解銅めっきを行い銅厚が15μmとなるよう調整した。続いて厚さ15μmの日立化成製ドライフィルムレジストRY−3215をラミネータを用いて110℃、3kg/cmでラミネートコーティングを行った。露光量55mJの条件で露光し、1%炭酸ナトリウム水溶液で現像を行うことでレジストパターンを形成した。次に、レジストパターンをマスクにして塩化第二鉄液を用いて銅をエッチング処理した後、レジストパターンを5%水酸化ナトリウム水溶液により除去することで配線層を形成した。再度、フォトリソグラフィ工程によって露光、現像を行うことで抵抗体以外の部分をレジストでマスクし、抵抗体部分の銅をアルカリエッチング液で除去した。続いて、銀ペーストを銅配線に重なるようにスクリーン印刷し、150℃で30分間硬化させた。カーボン粒子を含みエポキシ樹脂をバインダーとする抵抗ペーストをその端部が銀ペースト電極に重なるようにスクリーン印刷し、200℃で2時間硬化させた。レーザートリミングにより抵抗値を調整後、さらに、抵抗体上にクラリアント製ポリシラザン材料を定量塗工機により滴下し150℃で1時間硬化させた。このようにして本発明の基板内蔵用抵抗素子を形成した。 Hereinafter, examples will be described in detail. First, the insulating base material is washed with a conditioning cleaner (Okuno Pharmaceutical Co., Ltd .: OPC-380 Condy Clean M), applied with a catalyst (Okuno Pharmaceutical Co., Ltd .: OPC-80 Catalyst), and activated (Okuno Pharmaceutical Co., Ltd .: OPC). -555 accelerator M) was pretreated. Next, it plated about 0.3 micrometer with the electroless nickel * phosphorus * iron alloy plating solution. Dip etching is performed with a 5 g / L ammonium persulfate aqueous solution for 20 minutes so that the resistance value of the plating film becomes sufficiently higher than the design value of the mounted resistor, and the film thickness of the electroless nickel / phosphorus / iron alloy plating is set to 0. Adjusted to 2 μm. In this way, a water vapor barrier layer was formed. Next, a thin-film conductor layer is formed by electroless copper plating (Shipley Far East CUPOSIT). At this time, the electroless copper plating thickness may be about 1 μm. Using this thin film conductor layer as a cathode, electrolytic copper plating was performed at 2 A / dm 2 for 30 minutes to adjust the copper thickness to 15 μm. Subsequently, a laminate coating of 15 μm thick Hitachi Chemical dry film resist RY-3215 was performed at 110 ° C. and 3 kg / cm using a laminator. The resist pattern was formed by exposing with the exposure amount of 55 mJ, and developing with 1% sodium carbonate aqueous solution. Next, copper was etched using ferric chloride solution using the resist pattern as a mask, and then the resist pattern was removed with a 5% aqueous sodium hydroxide solution to form a wiring layer. Again, exposure and development were performed by a photolithography process to mask portions other than the resistor with a resist, and copper in the resistor portion was removed with an alkaline etching solution. Subsequently, the silver paste was screen printed so as to overlap the copper wiring and cured at 150 ° C. for 30 minutes. Resistive paste containing carbon particles and epoxy resin as a binder was screen-printed so that the end portion overlaps the silver paste electrode, and cured at 200 ° C. for 2 hours. After adjusting the resistance value by laser trimming, a polysilazane material made of Clariant was further dropped on the resistor by a quantitative coating machine and cured at 150 ° C. for 1 hour. Thus, the resistance element for incorporating a substrate of the present invention was formed.

抵抗素子形成後、抵抗素子間の抵抗値は100.9kΩであった。その後、抵抗素子内臓基板を温度85゜C、湿度85%の試験室中に100時間放置し、再度、抵抗素子間の抵抗値を測定したところ、104.9kΩであった。   After forming the resistance elements, the resistance value between the resistance elements was 100.9 kΩ. Thereafter, the substrate with a built-in resistor element was left in a test chamber at a temperature of 85 ° C. and a humidity of 85% for 100 hours, and the resistance value between the resistor elements was measured again. As a result, it was 104.9 kΩ.

(比較例1)
水蒸気バリア層形成工程を除き、実施例1と同様に基板内蔵用抵抗素子を形成した。抵抗素子形成後、抵抗素子間の抵抗値は100.3kΩであった。その後、抵抗素子内臓基板を温度85゜C、湿度85%の試験室中に100時間放置し、再度、抵抗素子間の抵抗値を測定したところ、112.3kΩであった。
(Comparative Example 1)
A substrate built-in resistance element was formed in the same manner as in Example 1 except for the water vapor barrier layer forming step. After forming the resistance elements, the resistance value between the resistance elements was 100.3 kΩ. Thereafter, the resistance element-embedded substrate was left in a test chamber at a temperature of 85 ° C. and a humidity of 85% for 100 hours, and when the resistance value between the resistance elements was measured again, it was 112.3 kΩ.

本発明の基板内蔵抵抗体の一例を示す断面図である。It is sectional drawing which shows an example of the board | substrate built-in resistor of this invention. (a)〜(j)は本発明の第1実施形態に示す基板内蔵抵抗体の製造工程の一部を示す模式断面図である。(A)-(j) is a schematic cross section which shows a part of manufacturing process of the resistor with a built-in substrate shown in 1st Embodiment of this invention. (a)〜(j)は本発明の第2実施形態に示す基板内蔵抵抗体の製造工程の一部を示す模式断面図である。(A)-(j) is a schematic cross section which shows a part of manufacturing process of the resistor with a built-in board | substrate shown to 2nd Embodiment of this invention.

符号の説明Explanation of symbols

11…絶縁基材
12…絶縁樹脂
13…銅貼積層板
21…水蒸気バリア層
22…オーバーコート層
31…導体層
32…銅配線
33…銅電極
41…レジストパターン
42…レジストパターン
51…銀ペースト
52…抵抗体
60…基板内蔵抵抗素子
100…抵抗素子内蔵配線回路板
DESCRIPTION OF SYMBOLS 11 ... Insulating base material 12 ... Insulating resin 13 ... Copper adhesion laminated board 21 ... Water vapor barrier layer 22 ... Overcoat layer 31 ... Conductor layer 32 ... Copper wiring 33 ... Copper electrode 41 ... Resist pattern 42 ... Resist pattern 51 ... Silver paste 52 ... Resistor 60 ... Built-in resistor element 100 ... Resistance element built-in wiring circuit board

Claims (5)

配線回路板に内蔵して用いられる抵抗素子において、カーボンブラック及び樹脂を含有する抵抗ペーストからなる抵抗体と絶縁基板との間に無電解ニッケル・リン・鉄合金めっきよりなる水蒸気バリア層を備えたことを特徴とする抵抗素子。 In a resistance element built in a wiring circuit board, a water vapor barrier layer made of electroless nickel / phosphorus / iron alloy plating is provided between a resistor made of a resistance paste containing carbon black and a resin and an insulating substrate. A resistance element. 前記水蒸気バリア層において前記抵抗体と重なり合っている部分の抵抗値が前記抵抗体の抵抗値の100倍以上であることを特徴とする請求項1記載の抵抗素子。   The resistance element according to claim 1, wherein a resistance value of a portion of the water vapor barrier layer overlapping the resistor is 100 times or more of a resistance value of the resistor. 前記抵抗体の表面がオーバーコート層で覆われていることを特徴とする請求項1または2に記載の抵抗素子。 The resistance element according to claim 1, wherein a surface of the resistor is covered with an overcoat layer . 前記オーバーコート層が無機材料であることを特徴とする請求項3に記載の抵抗素子。 The resistance element according to claim 3 , wherein the overcoat layer is an inorganic material . 請求項1乃至4のいずれかに記載の抵抗素子を内蔵した配線回路板。A printed circuit board incorporating the resistance element according to claim 1.
JP2005030164A 2005-02-07 2005-02-07 Wiring circuit board built-in resistance element Expired - Fee Related JP4645212B2 (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0350784A (en) * 1989-07-18 1991-03-05 Matsushita Electric Ind Co Ltd Manufacture of printed circuit board

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0350784A (en) * 1989-07-18 1991-03-05 Matsushita Electric Ind Co Ltd Manufacture of printed circuit board

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