JP4661338B2 - Method for forming resistor - Google Patents

Method for forming resistor Download PDF

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JP4661338B2
JP4661338B2 JP2005138170A JP2005138170A JP4661338B2 JP 4661338 B2 JP4661338 B2 JP 4661338B2 JP 2005138170 A JP2005138170 A JP 2005138170A JP 2005138170 A JP2005138170 A JP 2005138170A JP 4661338 B2 JP4661338 B2 JP 4661338B2
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plating
resistor
noble metal
wiring
forming
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JP2006319024A (en
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達広 岡野
真也 志摩
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Toppan Inc
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Description

本発明は、内部に抵抗素子を有するプリント配線板の抵抗体の形成方法に関し、特に絶縁基板上の一対の電極とその間に配置された抵抗体の形成方法に関する。   The present invention relates to a method of forming a resistor of a printed wiring board having a resistance element therein, and more particularly to a method of forming a pair of electrodes on an insulating substrate and a resistor disposed therebetween.

近年、携帯電話やデジタルカメラなどの機器の小型化と軽量化が進むにつれて、プリント配線板に実装する素子においては、素子の小型化や素子同士の間隔の削減といった要求が強まっている。これに対し、従来の実装技術では対応が難しくなり、これら素子をプリント配線板内に内蔵した多層プリント配線基板への期待が高まっている。受動素子(キャパシタ、抵抗、インダクタ)は既存のチップ素子を埋め込めば機器メーカーが必要とする特性を比較的容易に満たすことができるが、素子を内蔵した基板が厚くなってしまうという問題点がある。薄い部品や薄膜素子で十分に特性を満たすことができる方法の開発などが急がれている。   In recent years, as devices such as mobile phones and digital cameras have been reduced in size and weight, there has been an increasing demand for elements to be mounted on a printed wiring board, such as miniaturization of elements and reduction in the distance between elements. On the other hand, it is difficult to cope with the conventional mounting technology, and there is an increasing expectation for a multilayer printed wiring board in which these elements are built in a printed wiring board. Passive elements (capacitors, resistors, inductors) can satisfy the characteristics required by device manufacturers relatively easily by embedding existing chip elements, but there is a problem that the substrate containing the elements becomes thick. . There is an urgent need to develop a method that can sufficiently satisfy characteristics with thin parts and thin film elements.

プリント配線板内部に抵抗素子を作りこむ方法としては、銅箔上に金属薄膜で抵抗層を形成する方法、絶縁基板上にめっきで形成する方法、抵抗性の厚膜ポリマーを印刷する方法などがある。抵抗値、精度、形状、価格などから用途に応じて形成方法を選択していく必要がある。厚膜ポリマーを印刷する方法では、高抵抗なものを形成できるが、微細な寸法になると形成が困難である。金属材料を用いた薄膜タイプは、厚膜タイプに比べ、抵抗値範囲が低抵抗に制約されるが、小さなサイズで高精度に形成できる。   As a method of creating a resistance element inside a printed wiring board, a method of forming a resistance layer with a metal thin film on a copper foil, a method of forming by plating on an insulating substrate, a method of printing a resistive thick film polymer, etc. is there. It is necessary to select a forming method according to the application from the resistance value, accuracy, shape, price, and the like. In the method of printing a thick film polymer, it is possible to form a high-resistance material, but it is difficult to form a fine size. The thin film type using a metal material is restricted to a low resistance range as compared with the thick film type, but can be formed with a small size and high accuracy.

以下に公知の文献を示す。
特開平11−004056号公報
Known documents are shown below.
JP-A-11-004056

抵抗体ペーストを用いた抵抗素子の形成では、銅の配線層に電極を形成して直接銅上に抵抗ペーストを形成すると、銅の酸化によって抵抗素子の抵抗値が次第に上昇するという問題が発生していた。それに対応するため、最近では抵抗ペーストを形成する電極部に金めっきや銀めっきなどの貴金属めっきを施すことで抵抗素子の抵抗値変動を少なくしている。(図1参照)この貴金属めっきを施す際に、配線パターンによっては独立した配線となるために無電解めっきを用いることが多いが、無電解めっきでは貴金属めっきの膜厚が薄く、抵抗値を安定化するためには薄過ぎる場合がある。また、電解めっきで貴金属めっきする際には、めっきのためのめっきリードが必要となり、そのための配線レイアウトが必要で、めっき後にこのめっきリードを切断する必要があった。   In the formation of a resistance element using a resistor paste, when an electrode is formed on a copper wiring layer and a resistance paste is formed directly on copper, the resistance value of the resistance element gradually increases due to copper oxidation. It was. In order to cope with this, recently, the resistance variation of the resistance element is reduced by applying noble metal plating such as gold plating or silver plating to the electrode portion on which the resistance paste is formed. (Refer to Fig. 1) When applying this noble metal plating, electroless plating is often used because it becomes independent wiring depending on the wiring pattern, but in electroless plating, the thickness of the noble metal plating is thin and the resistance value is stable It may be too thin to make. Moreover, when noble metal plating is performed by electrolytic plating, a plating lead for plating is required, and a wiring layout for that purpose is required, and it is necessary to cut this plating lead after plating.

本発明は、上述の課題に鑑みてなされたものであり、本発明の請求項1の発明は、多層配線基板に内蔵する抵抗ペーストを用いた抵抗体の形成方法において、絶縁層上に抵抗体を接続する配線電極と配線電極を電解めっきするためのめっきリードとを具備した配線層を形成し、配線電極の接続部分とめっきリードの一部分とに銅よりもイオン化傾向の小さい金属の貴金属めっきを電解めっきで形成し、配線電極間に貴金属めっきした接続部分を介しかつ貴金属めっき部分を被うように抵抗ペーストを用いて抵抗体を形成し、前記銅配線層をCZ処理または黒化処理によって粗化してめっきリードの貴金属めっきを施した一部分を局部電池の作用によって切断することを特徴とする抵抗体の形成方法としたものである。 The present invention has been made in view of the above-mentioned problems. The invention according to claim 1 of the present invention is a method of forming a resistor using a resistor paste built in a multilayer wiring board. A wiring layer having a wiring electrode for connecting the electrode and a plating lead for electrolytic plating of the wiring electrode is formed, and a noble metal plating of a metal having a smaller ionization tendency than copper is formed on the connection part of the wiring electrode and a part of the plating lead. A resistor is formed by using a resistance paste so as to cover the noble metal plating portion through the connection portion formed by electrolytic plating and noble metal plating between the wiring electrodes, and the copper wiring layer is roughened by CZ treatment or blackening treatment. The method of forming a resistor is characterized in that a part of the plated lead subjected to noble metal plating is cut by the action of a local battery .

上記の発明では、抵抗体を形成する際に、配線レイアウトを気にせずに、その配線電極
部に貴金属めっきを電解めっきで形成できる。めっきリードの一部分に貴金属めっきが施してあると、銅のような配線層の粗化処理の際に、局部電池の作用によって貴金属の端部で配線層が切れてしまう。抵抗素子の部分も、貴金属めっきが施してあるが、この部分は抵抗体が貴金属めっきを被っているため、銅配線に影響を及ぼすことはない。
In the above invention, when forming the resistor, noble metal plating can be formed on the wiring electrode portion by electrolytic plating without worrying about the wiring layout. If noble metal plating is applied to a part of the plating lead, the wiring layer is cut at the end of the noble metal by the action of the local battery during the roughening treatment of the wiring layer such as copper. The resistance element portion is also plated with noble metal, but this portion does not affect the copper wiring because the resistor is covered with the noble metal plating.

本発明の請求項2の発明は、貴金属めっきに銀、金、パラジウムを含む金属を用いたことを特徴とする請求項1記載の抵抗体の形成方法としたものである。   According to a second aspect of the present invention, there is provided the resistor forming method according to the first aspect, wherein a metal containing silver, gold or palladium is used for the noble metal plating.

上記発明では、貴金属めっきに、一般に市販されている金や銀、パラジウムなどの金属を含む電解めっき液を使用することができる。   In the said invention, the electroplating liquid containing metals, such as gold | metal | money, silver, and palladium which are generally marketed, can be used for noble metal plating.

多層配線基板に内蔵する抵抗体の形成方法では、抵抗体と電極配線の界面に電解めっきによる貴金属めっきを介したことで、抵抗素子の抵抗値変動がなくなり、精度の高い抵抗素子を基板内に埋め込むことが可能になった。また、めっきリードの切断が容易になったために、電解めっきの際のめっきリードのための配線レイアウトを自由に設計することができ、切断のための配置を考える必要がなくなった。無電解めっきは、めっき浴の管理が難しく寿命も短いため、電解めっきを採用できることで、基板のコストダウンもできる。   In the method of forming a resistor incorporated in a multilayer wiring board, the resistance value fluctuation of the resistance element is eliminated by passing noble metal plating by electrolytic plating at the interface between the resistor and the electrode wiring, and a highly accurate resistance element is placed in the substrate. It became possible to embed. Further, since the plating lead can be easily cut, it is possible to freely design a wiring layout for the plating lead at the time of electrolytic plating, and it is not necessary to consider an arrangement for cutting. Since electroless plating is difficult to manage the plating bath and has a short life, electrolytic plating can be employed, thereby reducing the cost of the substrate.

本発明の多層配線基板に内蔵する抵抗体の形成方法を図1、2、3を使って説明する。図1、2、3は、本発明の抵抗体の形成方法の一例を、平面(左側)及び断面(右側)で見た部分説明図である。本例の抵抗素子内蔵基板の抵抗体の形成方法は、図1(a)のように絶縁基板1上に抵抗体を形成するための配線電極10と貴金属めっきを施すためのめっきリード11を形成し、次に図1(b)のように部分的に貴金属めっきを施すためのレジスト15を基板と配線層全面にコートする。ただし、図1(b)の平面で見た図には、説明のため、レジスト15は示していない。図1(c)のように露光と現像を行い、貴金属めっきを施すための露出部を形成したレジストパターン15aを形成する。図2(d)のように貴金属めっきを施して、レジストの開口部に貴金属めっき25を行う。図2(e)のようにレジストを除去した後に、図2(f)のように抵抗体30を銀めっき25を被うように電極10上に形成する。図3(g)では、多層配線層の上層を形成するために、接着層と配線層との密着を向上するため、銅の表面をCZ処理や黒化処理によって粗化する必要があるが、その工程によって露出している貴金属めっきの部分が侵食され、切断されている。このため、従来のようにめっきリードをわざわざ切断する必要がなく、抵抗素子の端子部にも適度な膜厚の貴金属めっきが行える抵抗素子の形成方法を提供できる。   A method of forming a resistor incorporated in the multilayer wiring board of the present invention will be described with reference to FIGS. 1, 2 and 3 are partial explanatory views of an example of a method of forming a resistor according to the present invention as seen in a plane (left side) and a cross section (right side). The method of forming a resistor of the resistor element-embedded substrate of this example forms a wiring electrode 10 for forming a resistor and a plating lead 11 for performing noble metal plating on the insulating substrate 1 as shown in FIG. Then, as shown in FIG. 1B, a resist 15 for partially precious metal plating is coated on the entire surface of the substrate and the wiring layer. However, the resist 15 is not shown in the figure seen from the plane of FIG. As shown in FIG. 1C, exposure and development are performed to form a resist pattern 15a having an exposed portion for precious metal plating. As shown in FIG. 2D, noble metal plating is performed, and noble metal plating 25 is performed on the opening of the resist. After removing the resist as shown in FIG. 2E, a resistor 30 is formed on the electrode 10 so as to cover the silver plating 25 as shown in FIG. In FIG. 3G, in order to improve the adhesion between the adhesive layer and the wiring layer in order to form the upper layer of the multilayer wiring layer, it is necessary to roughen the copper surface by CZ treatment or blackening treatment. The exposed precious metal plating portion is eroded and cut by the process. For this reason, it is not necessary to cut the plating lead as in the prior art, and it is possible to provide a method for forming a resistance element capable of plating a noble metal with an appropriate film thickness on the terminal portion of the resistance element.

以下、実施例について図1、2、3を用いて詳細に説明する。   Examples will be described in detail below with reference to FIGS.

本発明の抵抗素子内蔵基板の抵抗体の形成方法の実施例は次の方法のようになる。   An embodiment of a method for forming a resistor of a resistance element built-in substrate according to the present invention is as follows.

配線基板1に12μmの銅箔を両面に有する0.6mm厚のBTレジン基板(三菱ガス化学社製)を用いて、通常のプリント配線基板の形成方法と同様にフォトリソグラフィ工程とエッチングにより、抵抗素子を形成する部分に配線電極10とめっきリード11を含む配線層を形成した(図1(a))。   Using a 0.6 mm-thick BT resin substrate (Mitsubishi Gas Chemical Co., Ltd.) having a 12 μm copper foil on both sides of the wiring substrate 1, resistance is obtained by a photolithography process and etching in the same manner as a normal printed wiring substrate formation method. A wiring layer including the wiring electrode 10 and the plating lead 11 was formed in a portion where the element is to be formed (FIG. 1A).

抵抗素子を形成する配線電極10部ならびにめっきリード11の切断部に選択的にめっきを行うために、レジスト15として15μm厚のドライフィルムレジスト(RY3315 日立化成工業製)をラミネーターを用いてラミネートした(図1(b))。ラミネート条件は、110℃,3MPa,0.5m/secである。めっき部分の電極配線が露出
するようなパターンで露光現像することで、図1(c)のようにレジストパターン15aを形成することができた。露光条件は、60mJ/cm2で現像は、1%の炭酸ソーダ溶液でスプレー現像で、15秒ほどの現像時間で現像することができた。レジストパターンを形成した後、電解銀めっき液(テンペレジスト銀めっき液 日本高純度化学製)を用いて、めっき膜厚が0.5μm以上となるようにめっき処理を施した(図2(d))。めっき後に、3%の水酸化ナトリウム溶液でドライフィルムレジストの除去を行った(図2(e))。洗浄、乾燥後に抵抗体30として抵抗ペーストをスクリーン印刷で電極配線上に形成した銀めっきが被われるように印刷した(図2(f))。印刷後、80℃で30分乾燥後に180℃、2時間の本ベークを行った。次に、上層の配線層を形成するために、配線層の粗化をメック社のCZ処理によって行った。このCZ処理によってめっきリード部に形成した露出している銀めっきの両端で配線層が切断され、めっきリードの断線した回路として働く配線層が形成できた(図3(g))。接着層にプリプレグを介して、銅箔などを積層することで、めっきリードの切断を行う必要がなく、次の配線層の形成が可能となった。また、銀めっきの厚みも無電解めっきで形成するよりも短時間に膜厚も厚くできるため、抵抗の変動がなく、製造時間の短縮につながった。
In order to selectively perform plating on the wiring electrode 10 part forming the resistance element and the cut part of the plating lead 11, a 15 μm thick dry film resist (RY3315 manufactured by Hitachi Chemical Co., Ltd.) was laminated as a resist 15 using a laminator ( FIG. 1 (b)). Lamination conditions are 110 ° C., 3 MPa, and 0.5 m / sec. The resist pattern 15a can be formed as shown in FIG. 1C by exposing and developing with a pattern in which the electrode wiring in the plated portion is exposed. The exposure conditions were 60 mJ / cm 2 , and the development was performed with a 1% sodium carbonate solution by spray development, and development was possible in about 15 seconds. After the resist pattern was formed, a plating process was performed using an electrolytic silver plating solution (Tempe resist silver plating solution, manufactured by Nippon High Purity Chemical Co., Ltd.) so that the plating film thickness was 0.5 μm or more (FIG. 2D). ). After plating, the dry film resist was removed with a 3% sodium hydroxide solution (FIG. 2 (e)). After washing and drying, a resistor paste was printed as a resistor 30 so as to cover the silver plating formed on the electrode wiring by screen printing (FIG. 2 (f)). After printing, this was baked at 80 ° C. for 30 minutes, and then baked at 180 ° C. for 2 hours. Next, in order to form an upper wiring layer, the wiring layer was roughened by the CZ process of MEC. By this CZ treatment, the wiring layer was cut at both ends of the exposed silver plating formed on the plating lead portion, and a wiring layer serving as a circuit in which the plating lead was disconnected was formed (FIG. 3G). By laminating a copper foil or the like on the adhesive layer via a prepreg, it is not necessary to cut the plating lead, and the next wiring layer can be formed. Moreover, since the thickness of the silver plating can be increased in a shorter time than that formed by electroless plating, the resistance does not fluctuate and the manufacturing time is shortened.

貴金属めっきにパラジウムめっきを用いても、実施例1と同様に抵抗値の安定しためっきリードの切断が必要ない抵抗素子を内蔵した多層配線基板を形成することが可能であった。   Even when palladium plating is used for the noble metal plating, it is possible to form a multilayer wiring board having a built-in resistance element that does not require cutting of a plating lead having a stable resistance value, as in the first embodiment.

図4のような独立した回路が存在する場合でも配線レイアウトを気にせずに電解めっきのめっきリードを配置することが可能であり、めっきリードの切断を考えない抵抗体を内蔵する配線基板の形成が可能であった。詳細なめっき方法などは、実施例1や2と同様である。   Even when an independent circuit as shown in FIG. 4 exists, it is possible to arrange electrolytic plating plating leads without worrying about the wiring layout, and to form a wiring board with a built-in resistor that does not consider cutting of the plating leads Was possible. The detailed plating method and the like are the same as those in the first and second embodiments.

本発明の配線回路基板内蔵用抵抗素子の形成方法は、配線回路基板上に実装されている実装部品を基板内部に内蔵しようというものである。実装部品を基板内部に取り込むことで、実装エリアにスペースが生まれより高機能な部品を実装することが可能となる。また、従来の基板サイズも小さくすることが可能となり、電子機器の軽薄短小化を促進する原動力ともなる。   The method for forming a resistance element for embedding a wired circuit board according to the present invention intends to incorporate a mounting component mounted on the wired circuit board inside the board. By incorporating the mounting component into the board, a space is created in the mounting area, and it becomes possible to mount a higher-performance component. In addition, it is possible to reduce the size of the conventional substrate, which is a driving force for promoting the reduction in the thickness and thickness of electronic devices.

本発明の抵抗体の形成方法の一例を平面および断面で見た部分説明図である。It is the partial explanatory view which looked at an example of the formation method of the resistor of the present invention in the plane and the section. 本発明の抵抗体の形成方法の一例を平面および断面で見た部分説明図である。It is the partial explanatory view which looked at an example of the formation method of the resistor of the present invention in the plane and the section. 本発明の抵抗体の形成方法の一例を平面および断面で見た部分説明図である。It is the partial explanatory view which looked at an example of the formation method of the resistor of the present invention in the plane and the section. 本発明の抵抗体の形成方法の他の例を平面で見た部分説明図である。It is the partial explanatory view which looked at other examples of the formation method of the resistor of the present invention on the plane.

符号の説明Explanation of symbols

1・・・・・・・・・ 配線基板
10・・・・・・・・・ 電極配線
11・・・・・・・・・ めっきリード
11a・・・・・・・・・ 切断されためっきリード
15・・・・・・・・・ めっきレジスト
15a・・・・・・・・・ パターニングされためっきレジスト
25・・・・・・・・・ 電解めっきによる貴金属めっき
30・・・・・・・・・ 抵抗体
1 ... Wiring board 10 ... Electrode wiring 11 ... Plating lead 11a ... Cut plating Lead 15 ... Plating resist 15a ... Patterned plating resist 25 ... Precious metal plating 30 by electrolytic plating ... ... Resistors

Claims (2)

多層配線基板に内蔵する抵抗ペーストを用いた抵抗体の形成方法において、絶縁層上に抵抗体を接続する配線電極と配線電極を電解めっきするためのめっきリードとを具備した配線層を形成し、配線電極の接続部分とめっきリードの一部分とに銅よりもイオン化傾向の小さい金属の貴金属めっきを電解めっきで形成し、配線電極間に貴金属めっきした接続部分を介しかつ貴金属めっき部分を被うように抵抗ペーストを用いて抵抗体を形成し、前記銅配線層をCZ処理または黒化処理によって粗化してめっきリードの貴金属めっきを施した一部分を局部電池の作用によって切断することを特徴とする抵抗体の形成方法。 In a method of forming a resistor using a resistor paste built in a multilayer wiring board, a copper wiring layer having a wiring electrode for connecting the resistor and a plating lead for electrolytic plating of the wiring electrode is formed on the insulating layer. The noble metal plating of metal having a smaller ionization tendency than copper is formed by electrolytic plating on the connection part of the wiring electrode and a part of the plating lead, and the noble metal plating part is covered through the connection part where the noble metal plating is provided between the wiring electrodes. A resistor is formed using a resistance paste, and the copper wiring layer is roughened by CZ treatment or blackening treatment, and a portion of the plating lead subjected to noble metal plating is cut by the action of a local battery. Body formation method. 貴金属めっきに銀、金、パラジウムを含む金属を用いたことを特徴とする請求項1記載の抵抗体の形成方法。
2. The method of forming a resistor according to claim 1, wherein a metal containing silver, gold, or palladium is used for the noble metal plating.
JP2005138170A 2005-05-11 2005-05-11 Method for forming resistor Expired - Fee Related JP4661338B2 (en)

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JP2005138170A JP4661338B2 (en) 2005-05-11 2005-05-11 Method for forming resistor

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JP4661338B2 true JP4661338B2 (en) 2011-03-30

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH114056A (en) * 1997-06-11 1999-01-06 Sony Corp Printing resistance printed circuit board and manufacture thereof
JP2001028478A (en) * 1999-07-14 2001-01-30 Mitsui Mining & Smelting Co Ltd Flexible printed wiring board, its manufacturing method, and screen plate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH114056A (en) * 1997-06-11 1999-01-06 Sony Corp Printing resistance printed circuit board and manufacture thereof
JP2001028478A (en) * 1999-07-14 2001-01-30 Mitsui Mining & Smelting Co Ltd Flexible printed wiring board, its manufacturing method, and screen plate

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