JPS5974608A - Formation of wiring structure - Google Patents

Formation of wiring structure

Info

Publication number
JPS5974608A
JPS5974608A JP18367282A JP18367282A JPS5974608A JP S5974608 A JPS5974608 A JP S5974608A JP 18367282 A JP18367282 A JP 18367282A JP 18367282 A JP18367282 A JP 18367282A JP S5974608 A JPS5974608 A JP S5974608A
Authority
JP
Japan
Prior art keywords
layer
insulating layer
conductor
substrate
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18367282A
Other languages
Japanese (ja)
Inventor
Kazunari Takemoto
一成 竹元
Fumio Kataoka
文雄 片岡
Fusaji Shoji
房次 庄子
Ataru Yokono
中 横野
Shunichiro Kuwazuka
鍬塚 俊一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP18367282A priority Critical patent/JPS5974608A/en
Publication of JPS5974608A publication Critical patent/JPS5974608A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00Details of transformers or inductances, in general

Abstract

PURPOSE:To obtain a flat insulation layer by a method wherein a conductor layer of a prescribed pattern is formed on a substrate and the 1st insulation layer of approximately the same thickness as the conductor layer is formed on the part of the substrate other than the pattern of the conductor layer and then an insulation layer for the prescribed pattern is formed. CONSTITUTION:The conductor layer 5 of a prescribed pattern is formed on a substrate 4 and an insulation layer 6 of approximately the same thickness as the conductor layer 5 is formed between the conductor pattern 5 and 5. After the difference in level between the conductor pattern 5 and 5 is thus filled, an insulation layer 7 is formed and a flat insulation layer is obtained. Moreover, a conductor layer 5 and an insulation layer 6 can be formed on the insulation layer 7 and an insulation layer can be formed on them. By laminating successively like this, multi-layer conductor can be formed. By the precision leveling like this, photo-lithography technology can be used and a magnetic circuit which is especially useful in case of composing a thin film magnetic head.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、薄膜磁気ヘッド等のコイル配線に適用される
配線構造体の成形方法に係り、この配線構造体の絶縁層
を平坦にする成形方法に関する。
[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a method for forming a wiring structure applied to coil wiring of a thin film magnetic head, etc., and a forming method for flattening an insulating layer of this wiring structure. Regarding.

〔従来技術〕[Prior art]

配線構造体の絶縁層の平坦化は、この絶縁層の表面にパ
ターンを形成する際大きな影響を与える。
Planarization of the insulating layer of the wiring structure has a great influence on forming a pattern on the surface of this insulating layer.

例えば磁気ヘッドの場合は、その性能に重大な影響を与
えることになる。
For example, in the case of a magnetic head, this has a significant impact on its performance.

特に薄膜プロセスにおいては、パターンの微細化が進む
につれて、配線構造体の絶縁層の高精度な平坦化が要求
され、大きな技術的課題になっている。
Particularly in thin film processes, as patterns become finer, highly accurate planarization of insulating layers of wiring structures is required, which has become a major technical issue.

例えば薄膜技術を用いて製造される磁気ヘッドについて
説明すると、従来は、導体コイルと磁性体との間の絶縁
および導体同志間の絶縁に有機樹脂が使用されるが、こ
れらの絶縁層を平坦にするのが困難であった。
For example, regarding magnetic heads manufactured using thin film technology, conventionally organic resins are used for insulation between the conductor coil and the magnetic material and between conductors, but these insulating layers can be flattened. It was difficult to do so.

例えば、有機樹脂としてポリイミド系樹脂を用いた場合
について第1図を基に更に詳しく説明する。
For example, a case where a polyimide resin is used as the organic resin will be described in more detail with reference to FIG.

図において、基板l上に配線2を形成し、この配線2.
の上にポリイミド絶縁層3を塗布して配線構造体を成形
するようにしていた。
In the figure, a wiring 2 is formed on a substrate l, and this wiring 2.
A wiring structure was formed by applying a polyimide insulating layer 3 thereon.

このような方法で配線構造体を製造した場合、基板1上
に形成された配線2の段差によって、この配線2を被覆
するポリイミド絶縁層3は、配線2の上と配線2と配線
2の間の基板1の上とで同じ高さVCならず、ポリイミ
ド絶縁層3の表面にうねりを未するという欠点があった
When a wiring structure is manufactured by such a method, the polyimide insulating layer 3 covering the wiring 2 is formed on the wiring 2 and between the wirings 2 due to the step difference in the wiring 2 formed on the substrate 1. There was a drawback that the height VC was not the same as that on the substrate 1, and the surface of the polyimide insulating layer 3 was not undulated.

この絶縁層の上に例えば磁性膜を形成すると、磁性膜自
体永うねりを生じ、磁気特性が低下する1、゛ という問題があった。
For example, when a magnetic film is formed on this insulating layer, the magnetic film itself permanently undulates, resulting in a decrease in magnetic properties.

〔発明の目的〕[Purpose of the invention]

本発明は、上記従来の欠点を解決し、平坦な絶縁層を得
ることができる配線構造体の成形方法を提供せんとする
ものである。
The present invention aims to solve the above-mentioned conventional drawbacks and provide a method for forming a wiring structure that can obtain a flat insulating layer.

〔発明の概要〕[Summary of the invention]

即ち本発明は、絶縁層を第1絶縁層と第2絶縁層に分け
て行なうようにし、基板上に形成された導体と導体の間
に第1P3緑層を設けて導体間の段差をなくし、その上
に第2絶縁層を形成して平坦化するようにしたものであ
って、先ず基板上に75r定のパターンを有する導体層
を形成し、次いで、この導体層のパターン以外の基板上
に導体層と同程度の層厚さの第1絶縁層を形成し、その
後導体層と第1絶縁層の上に第2絶縁層を形成して絶縁
層の表面を平坦化したことを%徴とするものである。
That is, in the present invention, the insulating layer is divided into a first insulating layer and a second insulating layer, and a first P3 green layer is provided between the conductors formed on the substrate to eliminate the difference in level between the conductors. A second insulating layer is formed on the second insulating layer and flattened. First, a conductor layer having a 75r constant pattern is formed on the substrate, and then a second insulating layer is formed on the substrate other than the pattern of this conductor layer. A first insulating layer with a thickness similar to that of the conductor layer is formed, and then a second insulating layer is formed on the conductor layer and the first insulating layer to flatten the surface of the insulating layer. It is something to do.

更に上記第2絶縁層の上に同じ方法で導体層と第1絶縁
層を形成し、更にその十に第2絶縁層を形成し、このよ
うに第2絶縁層、導体層及び第1絶縁層と順次積層する
ことにより、複数層の導体層を形成することを特徴とす
る。
Further, a conductor layer and a first insulating layer are formed on the second insulating layer by the same method, and a second insulating layer is further formed on top of the second insulating layer, and in this way, the second insulating layer, the conductor layer, and the first insulating layer are formed. It is characterized by forming a plurality of conductor layers by sequentially laminating the conductor layers.

〔発明の実施例〕[Embodiments of the invention]

以下本発明の一笑施例についてその詳細を説明する。先
ず、第2図を用いて、実施例の概略を説明する。
The details of a simple embodiment of the present invention will be explained below. First, the outline of the embodiment will be explained using FIG. 2.

図において、基板4上に所定のパターンを有する導体層
5を形成する。次にこの導体JvI5と5の間に同程度
の層厚さの第1絶縁層6を形成する。
In the figure, a conductor layer 5 having a predetermined pattern is formed on a substrate 4. Next, a first insulating layer 6 having a similar thickness is formed between the conductors JvI5 and 5.

このようにして導体層5と5の間の段差をなくした後、
第2絶縁層7を形成することによって平坦な絶縁層を形
成することができる。
After eliminating the step between the conductor layers 5 and 5 in this way,
By forming the second insulating layer 7, a flat insulating layer can be formed.

更に、この絶縁層7の上に導体層5と第1絶縁層6、第
2絶縁層7というように順次積層することによって複数
層の導体層を形成することができる。
Furthermore, a plurality of conductor layers can be formed by sequentially stacking the conductor layer 5, the first insulating layer 6, and the second insulating layer 7 on the insulating layer 7.

以下その詳細をさらに詳しく説明する。第2図において
基板4上に導体層を蒸着或いはスパッタリングによって
堆積し、フォトエツチング技法によって所定パターンの
導体層5を形成する(第2図(a)図)。次に有機樹脂
を塗布して加熱処理し、導体層5と同程度の厚さに製膜
した後、フォトエツチング技法によって伽)図に示すよ
うに、導体層5と5の間の隙間に埋め込むように、第1
絶縁層6を形成する。このように基板4上に導体層5と
第1絶縁層6を形成した後、(c)図に示すように、第
2絶縁層7を形成する。
The details will be explained in more detail below. In FIG. 2, a conductive layer is deposited on a substrate 4 by vapor deposition or sputtering, and a predetermined pattern of a conductive layer 5 is formed by photoetching (FIG. 2(a)). Next, an organic resin is applied and heat-treated to form a film to the same thickness as the conductor layer 5, and then it is embedded in the gap between the conductor layers 5 using a photo-etching technique as shown in the figure. Like, 1st
An insulating layer 6 is formed. After forming the conductor layer 5 and the first insulating layer 6 on the substrate 4 in this way, the second insulating layer 7 is formed as shown in FIG.

このようにして単一層の導体パターンを平坦化した配線
構造体を成形する。
In this way, a wiring structure with a flattened single-layer conductor pattern is formed.

次V?−複数層の導体パターンを平坦化した配線構造体
を製造する場合は、第2図(C)図に示す第2絶縁層7
の上に(a)図に示す導体層5を形成し、次いで同じよ
うに第1絶縁層6、次いで第2絶縁層7というようにI
IFj次くり返し積層することにより、行なわれる。
Next V? - When manufacturing a wiring structure with a flattened conductor pattern of multiple layers, the second insulating layer 7 shown in FIG.
A conductor layer 5 as shown in FIG.
This is done by repeatedly stacking layers IFj times.

以上のように構成した本実施例の作用を次に説明する。The operation of this embodiment configured as above will be explained next.

基板4上に所定のノ(ターンに堆積した導体層5と5の
間に第2絶縁層6を埋め込むことによって、導体N5同
志の段差がなくなり、基板4上に堆積された導体層と第
1絶縁層6の共通平面は、平坦化される。このようにし
て平坦化された導体層5と第1絶縁層6の共通平面上に
第2絶縁層7を形成することによって、上記共通平面に
ならった絶縁表面となる。
By embedding the second insulating layer 6 between the conductor layers 5 deposited in a predetermined turn on the substrate 4, the difference in level between the conductors N5 is eliminated, and the conductor layer deposited on the substrate 4 and the first The common plane of the insulating layer 6 is flattened. By forming the second insulating layer 7 on the common plane of the conductor layer 5 and the first insulating layer 6 which have been flattened in this way, the common plane is flattened. This results in a smooth insulating surface.

又この絶縁表面(第2絶縁層7表面)上に、導体層5、
第1絶縁層6及び第2絶縁層7を同様にくり返し積層す
ることにより、複数層の導体パターンを平坦化した配線
構造体とする。
Further, on this insulating surface (the surface of the second insulating layer 7), a conductor layer 5,
By repeatedly laminating the first insulating layer 6 and the second insulating layer 7 in the same manner, a wiring structure in which a plurality of layers of conductive patterns are planarized is obtained.

以下実際に実施した例を以下に示す。Examples of actual implementation are shown below.

実施例1: 単一層の導体パターンを平坦化した配線構造体について
、基板4の全曲に約2μmの層厚さの導体層を蒸着によ
り堆積しくスパッタリングによって堆積しても同じ効果
を得た)、フォトエツチング技法を用いて線幅10μm
S線間隔8μmの配線パターンを形成した。(この配線
パタ一ンはめっき技法を用いて行なっても同じ効果を得
た。)次に有機樹脂を塗布して加熱処理し、配線パター
ン層と同程度の厚さに製膜し、フォトエツチング技法を
用いて、配線の隙間に有機樹脂の第1絶縁層を埋め込む
ように形成した。最後に約2μmの層厚さの第2絶縁層
を形成した。このように形成した第2絶縁層の上面のう
ねり高さは0.2μm以下という良好な平坦面を有して
いることを確認した。
Example 1: Regarding a wiring structure in which a single-layer conductor pattern was flattened, the same effect was obtained by depositing a conductor layer with a thickness of about 2 μm over the entire curve of the substrate 4 by vapor deposition and sputtering). Line width 10μm using photoetching technique
A wiring pattern with an S line interval of 8 μm was formed. (The same effect was obtained even if this wiring pattern was made using plating techniques.) Next, an organic resin was applied and heat treated to form a film to the same thickness as the wiring pattern layer, and then photo-etched. A first insulating layer of an organic resin was formed to fill the gap between the wiring lines using a technique. Finally, a second insulating layer having a layer thickness of about 2 μm was formed. It was confirmed that the upper surface of the second insulating layer formed in this manner had a good flat surface with a waviness height of 0.2 μm or less.

実施例2: 薄膜磁気ヘッドの導体コイルの成形について、第3図に
おいて、セラミック基板8の全面に無機絶縁膜(例えば
At205 )をスパッタリングし、平坦な下地膜9を
形成した。次にこの下地膜9上に2μmの厚さのパーマ
ロイをスパッタリングで堆積し、フォトエツチング技法
によってパターン形成し、下部磁性体層10を形成した
。次にギヤツプスペーサとして約Jμmの厚さの無機絶
縁m(例えハAt203) 11 kスパッタリングで
堆積し、フォトエツチング技法によってパターン化した
。その上にxoooAのCr r 1.5 JimのC
u 、 1000 AのCrf蒸着しくスパッタリング
しても同じ効果を得たつ、フォトエツチング技法によっ
て線幅10μm、線間隔5μmiCパターン化し、第1
層導体コイル12を形成した。
Example 2: Regarding the formation of a conductor coil for a thin film magnetic head, as shown in FIG. 3, an inorganic insulating film (for example, At205) was sputtered over the entire surface of a ceramic substrate 8 to form a flat base film 9. Next, permalloy with a thickness of 2 μm was deposited on this base film 9 by sputtering, and patterned by a photoetching technique to form a lower magnetic layer 10. Next, as a gear spacer, an inorganic insulating material (for example, At203) with a thickness of about J .mu.m was deposited by sputtering and patterned by a photoetching technique. On top of that xoooA's Cr r 1.5 Jim's C
The same effect was obtained by sputtering CrF vapor deposition at 1000 A, but the first
A layered conductor coil 12 was formed.

次Kg光性ポリイミド前駆体組成物(%願昭56−54
408号参照)を用いてフォトリソグラフィー技法を用
いて、コイルの隙間に理め込むようにパターン形成し、
第1絶縁層13とした。このときの第1絶縁層13の厚
さは、第1層導体コイル12と同程度の約1.7μmで
あった。更に上記の感光性ポリイミド前駆体組成物を用
いて、フォトリソグラフィー技法によって第1層導体コ
イル12及び第1絶縁層13上に、約1.5μmの厚さ
の第2絶縁層14をパターン形成した。
Next Kg photosensitive polyimide precursor composition (%
408) using photolithography technique to form a pattern so as to fit into the gap between the coils,
A first insulating layer 13 was used. The thickness of the first insulating layer 13 at this time was about 1.7 μm, which was about the same as that of the first layer conductor coil 12. Further, using the above photosensitive polyimide precursor composition, a second insulating layer 14 having a thickness of about 1.5 μm was patterned on the first layer conductor coil 12 and the first insulating layer 13 by photolithography technique. .

次に第1層導体コイル12と同様に約1.7μmの厚−
さの第2層導体コイル15を、又第1絶縁層13と同様
にして第3絶縁層16を、更に第2絶縁層14と同様に
して第4絶縁層17を順次形成する。
Next, as with the first layer conductor coil 12, a thickness of about 1.7 μm is applied.
The second layer conductor coil 15, the third insulating layer 16 in the same manner as the first insulating layer 13, and the fourth insulating layer 17 in the same manner as the second insulating layer 14 are successively formed.

なおこのときの第3絶縁層16及び第4絶縁層17の厚
さはそれぞれ約1.7μm + 1.5μm になるよ
うに形成した。
Note that the thicknesses of the third insulating layer 16 and the fourth insulating layer 17 at this time were each approximately 1.7 μm + 1.5 μm.

以上のように構成した基板全面に2μmの厚さのパーマ
ロイをスパッタリングで堆積し、フォトエツチング技法
によってパターン化し、上部磁性体層18とした。
Permalloy with a thickness of 2 μm was deposited on the entire surface of the substrate constructed as described above by sputtering, and patterned by photoetching to form the upper magnetic layer 18.

このようにして成形して得られた第4絶縁層17の上面
は、うねり高さが0.2μm以下であり、磁気ヘッドの
磁気特性は、満足すべきものであった。
The upper surface of the fourth insulating layer 17 obtained by molding in this manner had a waviness height of 0.2 μm or less, and the magnetic properties of the magnetic head were satisfactory.

実施例3: 薄膜磁気ヘッドの導体コイル成形の他の実施例について
、第3図を用いて説明する。第2実施例と同様にして基
板8上に下地膜9を形成する。この下地膜の上にめっき
技法を用いて約2μmの下部磁性体層10を形成する。
Example 3: Another example of forming a conductor coil for a thin film magnetic head will be described with reference to FIG. A base film 9 is formed on a substrate 8 in the same manner as in the second embodiment. A lower magnetic layer 10 having a thickness of about 2 μm is formed on this base film using a plating technique.

次いで、キャップスベ−サとして約i 11mの厚さの
無機絶縁膜11を前記実施例2と同様にして形成する。
Next, an inorganic insulating film 11 having a thickness of about 11 m is formed as a cap baser in the same manner as in the second embodiment.

続いて、めっき技法により線幅LOμm、線間隔5線間
隔5官1層導体コイル12を形成する。この第工層導体
コイル12の隙間にちょうど埋まるように、フォトリソ
グラフィー技法によって約1.7μmの厚さの絶縁J脅
13を形成する。この第1絶縁層には、AZ−1350
J(シップレイ社製)を用いた。次いで同じ(AZ−1
350Jを用いてフォトリソグラフィー技法により、第
1層導体コイル12と第1絶縁層13の上に約1.5μ
m厚さの第2絶縁層14をパターン形成した。更に第1
層導体コイル12と同様にして約1.7μmの厚さの第
2層厚体コイル15を、又第1絶縁層13と同様にして
約1.7μmの厚さの第3絶縁層16を、更に又第2絶
縁層14と同様にして約1.5μmの厚さの第4絶縁層
17をlllil次形成した。最後に、めっき技法を用
いて、約2μmの厚さの上部磁性体層18を形成した。
Subsequently, a five-layer single-layer conductor coil 12 having a line width of LO μm and a line spacing of 5 lines is formed by plating. An insulating layer 13 having a thickness of about 1.7 μm is formed by photolithography so as to exactly fill the gap between the conductor coils 12 in the first layer. This first insulating layer contains AZ-1350
J (manufactured by Shipley) was used. Then the same (AZ-1
Approximately 1.5μ was deposited on the first layer conductor coil 12 and first insulating layer 13 by photolithography using 350J.
A second insulating layer 14 having a thickness of m was patterned. Furthermore, the first
A second thick body coil 15 with a thickness of about 1.7 μm in the same manner as the layer conductor coil 12, and a third insulating layer 16 with a thickness of about 1.7 μm in the same manner as the first insulating layer 13, Furthermore, in the same manner as the second insulating layer 14, a fourth insulating layer 17 having a thickness of about 1.5 μm was formed. Finally, the upper magnetic layer 18 having a thickness of about 2 μm was formed using a plating technique.

以上のように構成した第4絶縁層17上面のうねり高さ
は、0.2μm以下であり、磁気ヘッドの磁気特性は、
満足すべきものであった。
The undulation height of the upper surface of the fourth insulating layer 17 configured as described above is 0.2 μm or less, and the magnetic properties of the magnetic head are as follows.
It was satisfying.

因みに、従来技術において(第1図)、基板1全面に約
2μmの厚さの導体を蒸着して堆積し、フォトエツチン
グ技法を用いて、線幅10μm,線間隔8μmの配線パ
ターンを形成し、次いでこの配線パターンに有機樹脂を
塗布して加熱処理し、導体層と同程度の厚さに製膜し、
絶縁層3を形成したところ、絶縁層3のうねり高さは0
.5μm以上あり、そのうねり高さは、実施例1に比べ
約2.5倍以上であった。
Incidentally, in the prior art (FIG. 1), a conductor with a thickness of about 2 μm is deposited by vapor deposition on the entire surface of a substrate 1, and a wiring pattern with a line width of 10 μm and a line spacing of 8 μm is formed using a photoetching technique. Next, an organic resin is applied to this wiring pattern and heat treated to form a film with the same thickness as the conductor layer.
When the insulating layer 3 was formed, the waviness height of the insulating layer 3 was 0.
.. It was 5 μm or more, and the waviness height was about 2.5 times or more compared to Example 1.

〔発明の効果〕〔Effect of the invention〕

以上詳述した通り本発明の方法によれば、絶縁層を第1
層絶縁層と第2絶縁層の二つに分け、基板上に形成した
導体層の間に第1層絶縁層を埋め込み、導体層間の段差
をなくし、その上に第2絶縁層を形成するようにしたの
で、導体パターンを高精度に平坦化した配線構造体にす
ることができた。この高精度の平坦化によって、更に微
細なパターンを形成するフォトリソグラフィーの操作が
有利になると共に、何層にも積層した立体配線構造体の
製造が可能となり、特に薄膜磁気ヘッドを構成した場合
に、上部磁性層に不要な凹凸を作らないので、磁気回路
的に有効であり、優れた効果を萎する。
As detailed above, according to the method of the present invention, the insulating layer is
The first insulating layer is divided into two, an insulating layer and a second insulating layer, and the first insulating layer is buried between the conductor layers formed on the substrate, eliminating the step between the conductor layers, and forming the second insulating layer on top of the first insulating layer. As a result, it was possible to create a wiring structure in which the conductor pattern was flattened with high precision. This high-precision planarization not only makes it advantageous to use photolithography to form even finer patterns, but also makes it possible to manufacture three-dimensional wiring structures with multiple layers, especially when constructing a thin-film magnetic head. Since unnecessary unevenness is not created on the upper magnetic layer, it is effective in terms of magnetic circuits and has excellent effects.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、従来例を示し、単層の導体を有する配線構造
体の断面図である。第2図は本発明の一実施例を示し、
単層の導体を例に、配線構造体の成形方法を示した図で
ある。第3図は本発明の他の実施例を示し、薄膜磁気ヘ
ッドを例に、複数層の導体を有する配管構造体を断面に
示した図である。 4・・・基板、5・・・導体層、6・・・第1絶縁層、
7・・・第2絶縁層。 代理人 弁理士 秋 本 正 実 第1図 第2図 (0) 5 第3図 第1頁の続き 0発 明 者 横野中 横浜市戸塚区吉田町292番地株 式会社日立製作所生産技術研究 所内 0発 明 者 鍬塚俊一部 小田原市国府津2880株式会社日 立製作所小田原工場内
FIG. 1 shows a conventional example and is a sectional view of a wiring structure having a single layer of conductors. FIG. 2 shows an embodiment of the present invention,
FIG. 3 is a diagram illustrating a method for forming a wiring structure using a single-layer conductor as an example. FIG. 3 shows another embodiment of the present invention, and is a cross-sectional view of a piping structure having multiple layers of conductors, taking a thin film magnetic head as an example. 4... Substrate, 5... Conductor layer, 6... First insulating layer,
7... Second insulating layer. Agent Tadashi Akimoto, Patent Attorney Figure 1, Figure 2 (0) 5 Continuation of Figure 3, Page 1 0 Inventor Yokononaka, Hitachi, Ltd. Production Technology Laboratory, 292 Yoshida-cho, Totsuka-ku, Yokohama 0 Author: Shun Kuwazuka, Hitachi, Ltd., Odawara Factory, 2880 Kokufutsu, Odawara City

Claims (1)

【特許請求の範囲】 1 基板上VCJ5T定のパターンを有する導体層を形
成し、該導体ノーのパターン以外の基板上に導体層と同
程度の層厚さの第1絶縁層を形成し、次いで前記導体層
と第1絶縁層の上に所定のパターンを有する第2絶縁層
を形成し、単一層の導体層としたことを特徴とする配線
構造体の成形方法。 2、特許請求の範囲第1項の第1絶縁層及び第2絶縁層
において、これら絶縁層の少なくとも一方の絶縁層を感
光性材料とし、フォトリソグラフィー技術によって形成
することを特徴とする配線構造体の成形方法。 3、特許請求の範囲第1項の第1絶縁増及び第2絶縁層
において、これら絶縁層の少なくとも一方のP縁層を感
光性ポリイミド前駆体組成物とし、フォトリソグラフィ
ー技術によって形成したことを特徴とする配線構造体の
成形方法。 4、基板上に所定のパターンを有する導体層を形成し、
該導体層のパターン以外の基板上に4体層と同程度の層
厚さの第1絶縁層を形成し、次いで前記導体層と第1絶
縁層の上に所定のパターンを有する第2絶縁層を形成し
、更に該第2絶縁層の上に所定パターンを有する導体層
、第1絶縁層。 及び第2絶縁層をくり返し積層し、複数層の導体層を形
成したことをlrf徴とする配線構造体の成形方法。 5、特許請求の範囲第4項の第1絶縁層及び第2絶縁層
において、これら絶縁層の少なくとも一方の絶縁層を感
光性材料とし、フォトリングラフイー技術によって形成
することを特徴とする配線構造体の成形方法。 6、特許請求の範囲第4項の第1絶縁層及び第2絶縁層
において、これら絶縁層の少なくとも一方の絶縁層を感
光性ポリイミド前駆体組成物とし、−フォトグラフィー
技術によって形成したことを特徴とする配線構造体の成
形方法。
[Claims] 1. A conductor layer having a constant pattern of VCJ5T is formed on a substrate, a first insulating layer having a layer thickness comparable to that of the conductor layer is formed on the substrate other than the pattern of the conductor, and then A method for forming a wiring structure, characterized in that a second insulating layer having a predetermined pattern is formed on the conductor layer and the first insulating layer to form a single-layer conductor layer. 2. A wiring structure characterized in that in the first insulating layer and the second insulating layer according to claim 1, at least one of these insulating layers is made of a photosensitive material and is formed by photolithography technology. molding method. 3. In the first insulation layer and the second insulation layer according to claim 1, the P edge layer of at least one of these insulation layers is made of a photosensitive polyimide precursor composition and is formed by photolithography technology. A method for forming a wiring structure. 4. Forming a conductor layer with a predetermined pattern on the substrate,
A first insulating layer having a layer thickness comparable to that of the four-body layer is formed on the substrate other than the pattern of the conductor layer, and then a second insulating layer having a predetermined pattern is formed on the conductor layer and the first insulating layer. a conductive layer and a first insulating layer, further having a predetermined pattern on the second insulating layer. and a method for forming a wiring structure in which a second insulating layer is repeatedly laminated to form a plurality of conductor layers. 5. Wiring characterized in that in the first insulating layer and the second insulating layer according to claim 4, at least one of these insulating layers is made of a photosensitive material and is formed by photophosphorography technology. How to form the structure. 6. In the first insulating layer and the second insulating layer according to claim 4, at least one of these insulating layers is made of a photosensitive polyimide precursor composition, and is formed by -photography technology. A method for forming a wiring structure.
JP18367282A 1982-10-21 1982-10-21 Formation of wiring structure Pending JPS5974608A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18367282A JPS5974608A (en) 1982-10-21 1982-10-21 Formation of wiring structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18367282A JPS5974608A (en) 1982-10-21 1982-10-21 Formation of wiring structure

Publications (1)

Publication Number Publication Date
JPS5974608A true JPS5974608A (en) 1984-04-27

Family

ID=16139903

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18367282A Pending JPS5974608A (en) 1982-10-21 1982-10-21 Formation of wiring structure

Country Status (1)

Country Link
JP (1) JPS5974608A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61243447A (en) * 1985-04-22 1986-10-29 Asahi Chem Ind Co Ltd Formation of pattern
JPS6285496A (en) * 1985-10-09 1987-04-18 三菱電機株式会社 Manufacture of printed circuit board
JPS6320710A (en) * 1986-07-11 1988-01-28 Matsushita Electric Ind Co Ltd Production of thin film magnetic head
JPH0290593A (en) * 1988-09-28 1990-03-30 Hitachi Ltd Manufacture of multilayer wiring board
JPH02126610A (en) * 1988-11-07 1990-05-15 Murata Mfg Co Ltd High frequency coil and manufacture thereof
WO2022070962A1 (en) * 2020-09-30 2022-04-07 富士フイルム株式会社 Method for manufacturing inductor and method for manufacturing electronic component

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61243447A (en) * 1985-04-22 1986-10-29 Asahi Chem Ind Co Ltd Formation of pattern
JPS6285496A (en) * 1985-10-09 1987-04-18 三菱電機株式会社 Manufacture of printed circuit board
JPS6320710A (en) * 1986-07-11 1988-01-28 Matsushita Electric Ind Co Ltd Production of thin film magnetic head
JPH0290593A (en) * 1988-09-28 1990-03-30 Hitachi Ltd Manufacture of multilayer wiring board
JPH02126610A (en) * 1988-11-07 1990-05-15 Murata Mfg Co Ltd High frequency coil and manufacture thereof
WO2022070962A1 (en) * 2020-09-30 2022-04-07 富士フイルム株式会社 Method for manufacturing inductor and method for manufacturing electronic component

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