JP3025362B2 - Method for manufacturing multilayer wiring board - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer wiring board, and more particularly to a method for manufacturing a multilayer wiring board having vias for electrically connecting thin film wiring layers.

[0002]

2. Description of the Related Art Generally, a plurality of thin film wiring layers in a multilayer wiring board are interconnected by vias formed in an insulating layer.

Conventionally, such a multilayer wiring board has been manufactured as shown in FIGS.

[0004] First, a first-layer thin film wiring layer 2 having a predetermined pattern is formed on an alumina substrate 1. In this step, first, a thin film wiring layer is formed on the entire surface of the alumina substrate 1. After that, a photoresist is applied on the thin film wiring layer, exposed using a photomask, and then developed to form a predetermined photoresist pattern. Then, the thin film wiring layer is selectively etched and removed using the photoresist pattern as a mask. Thus, a thin film wiring layer 2 having a predetermined pattern is formed (step a).

Next, an alumina substrate 1 and a thin film wiring layer 2
After forming a dry film or a photosensitive resist 31 on the entire surface, exposure and development are performed to form a via hole 4 in the dry film or the photosensitive resist 31 on the thin film wiring layer 2.
1 is formed (step b). Here, the dry film is thermocompressed by a laminator, and the photosensitive resist is applied by a spinner.

Thereafter, a first via 5 having a height of 5 to 50 μm is formed in the via hole 41 by performing Cu plating (step c).

Then, the dry film or the photosensitive resist 31 is peeled off (step d).

Next, as a first insulating layer 6, a polyimide heat-resistant resin is applied to a thickness of 5 to 50 μm (step e).

Thereafter, in order to remove the polyimide heat-resistant resin adhering on the via 5, a polishing process is performed until the via 5 is exposed (step f).

Further, as shown in FIG. 3, a second thin film wiring layer 7 is selectively formed in the same manner as in the step a (step g).

Next, a dry film or a photosensitive resist 32 is formed on the entire surface of the insulating layer 6 and the thin film wiring layer 7 in the same manner as in step b, and then exposed and developed to form a second layer of thin film wiring. A via hole 42 is formed in the dry film or the photosensitive resist 32 on the layer 7 (Step h).

Thereafter, in the same manner as in step c, a second via 8 having a height of 10 to 50 μm is formed in the via hole 42 by Cu plating (step i).

Next, the photosensitive resist 32 is peeled off (step j).

Next, as a second insulating layer 9, a polyimide heat-resistant resin is applied to a thickness of 10 to 50 μm (step k).

Thereafter, in the same manner as in step f, a polishing treatment is performed to remove the polyimide heat-resistant resin adhering on the second via 8 (step l).

Thereafter, the third thin film wiring layer 10 is formed in the same manner as in the step a (step m).

Hereinafter, steps h to m are repeated according to the number of layers.

[0018]

However, in the above-described conventional manufacturing method, the first and second vias 5 are formed in addition to the three photolithography steps for forming the thin film wiring layers 2, 7, and 10. , 8 also required one photolithography step each. That is, a total of five photolithography steps were required to manufacture a multilayer wiring board having three thin film wiring layers 2, 7, and 10. According to such a conventional manufacturing method, even if the first via 5 and the second via 8 are at the same position, each of the vias 5 and 8 has one
Two photolithography steps were required.

In addition, for example, in the photolithography step when the second via 8 is formed, the photosensitive resist 32
Is formed on the entire surface, dried (pre-baked), photomask is aligned, exposed, developed, solidified (post-baked), and peeled off. Further, in order to form the second via 8, a step of filling the via hole 42 by Cu plating is also required. As described above, if the number of photolithography steps is one, the number of steps is remarkably increased, and the cost is increased.

The present invention has been made in view of such a conventional problem, and has as its object to provide a method for manufacturing a multi-layer wiring board with a reduced number of steps and a low cost.

[0021]

According to the present invention, there is provided a method for manufacturing a multilayer wiring board in which thin film wiring layers and insulating layers are alternately stacked on a substrate, and the thin film wiring layers are electrically connected by vias. In the method, after forming an n-th thin film wiring layer on the substrate, the (n + 1) th thin film wiring layer subsequently formed on the n-th thin film wiring layer is raised. A via having a height as high as possible is formed, and then an n-th insulating layer and an (n + 1) -th thin film wiring layer are sequentially formed to form the n-th thin film wiring layer and the (n +
The (1) th thin film wiring layer is interconnected with the via via the via and the (n + 1) th thin film wiring layer is raised above the via, and then the (n + 1) th insulating layer and the ( forming an (n + 2) th thin film wiring layer in sequence and directly connecting the (n + 1) th thin film wiring layer and the (n + 2) th thin film wiring layer on the via; A characteristic method for manufacturing a multilayer wiring board is obtained. Note that n is a positive integer.

[0022]

In the method of manufacturing a multi-layer wiring board of the present invention having the above-described structure, a single via formation is required for connecting the nth to (n + 2) th thin film wiring layers between layers. Unlike the related art, it is not necessary to form the second via connecting the (n + 1) th thin film wiring layer and the (n + 2) th thin film wiring layer. Therefore, the number of photolithography steps required for interlayer connection is one, which is one less than the conventional one. As described above, since the number of photolithography steps is reduced by one, many manufacturing steps required for one photolithography step can be omitted.

[0023]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view for explaining one embodiment of the present invention. In order to facilitate understanding of the present embodiment, the cutting direction is different from that of the cross section of FIGS. 2 and 3 for explaining the prior art by 90 °.

As shown in FIG. 1, first, an alumina substrate 1
The first thin film wiring layer 2 having a predetermined pattern was formed thereon.

In this step, first, a thin film wiring layer was formed on the entire surface of the alumina substrate 1. First, a Ti layer is formed on the entire surface of the alumina substrate 1 by sputtering, a Mo layer is formed on the entire surface by sputtering, and a Cu layer is formed on the alumina substrate 1 by plating.
This was performed by forming the entire surface to a thickness of 0 to 20 μm. If the Cu layer may be thin, the Cu layer can be formed by a sputtering method. T at the bottom
The i layer is provided for improving the adhesion between the thin film wiring layer and the alumina substrate 1, and the intermediate Mo layer is provided for preventing the diffusion of Ti.

Instead of such a three-layered wiring layer made of Ti / Mo / Cu, a lower layer may be a Cr layer and an upper layer may be a two-layered Cr / Cu layer having a Cu layer. Cr is provided to improve the adhesion between the wiring layer and the alumina substrate 1. These Cr layer and Cu layer can be provided by a sputtering method.
When providing a layer, it is preferable to provide a Cu layer by a plating method.

Next, a photoresist was applied to the thin film wiring layer provided in this manner, exposed using a photomask, and then developed to form a predetermined photoresist pattern. Next, using the photoresist pattern as a mask, the thin film wiring layer was selectively removed by etching to form a thin film wiring layer 2 having a predetermined pattern (Step A).

Next, after laminating a dry film 3 having a thickness of 25 μm on the alumina substrate 1 and the thin film wiring layer 2, exposure and development are performed to obtain a first thin film wiring layer 2.
Via holes 4 having a diameter of 100 μm for forming vias were formed in the upper dry film 3 (step B).

Thereafter, Cu plating is performed to fill the via hole 4 with a via, and the via 1 having a height of 100 to 150 μm is formed.
1 was formed (Step C).

Then, the dry film 3 was peeled off (step D).

Next, as the first insulating layer 6, a polyimide heat-resistant resin was applied to a thickness of 25 to 30 μm (step E).

Thereafter, in order to remove the polyimide heat-resistant resin adhered on the via 11, a polishing treatment was performed (step F). Utilizing the hardness difference between copper and the polyimide heat-resistant resin, # 4000 of alumina abrasive grains capable of polishing only the polyimide heat-resistant resin was used as the abrasive. Polishing was performed until the via 11 was exposed. As described above, when the alumina abrasive grains are used, the polishing rate of Cu used for the via 11 is low, and the polishing rate of the polyimide heat-resistant resin used for the insulating layer 9 is high. Can be used as

Further, the second thin film wiring layer 7 was selectively formed in the same manner as in the step A (step G). The second thin film wiring layer 7 is raised above the via 11.

Next, in the same manner as in the step E, as the second insulating layer 9, a polyimide-based heat-resistant resin is formed on the second thin-film wiring layer 7 and the first insulating layer 6 to have a thickness. 25-30
μm (Step H).

Thereafter, in the same manner as in the step F, mainly the via 1
In order to remove the polyimide-based heat-resistant resin adhering on the second thin film wiring layer 7 in the portion raised on
Polishing was performed until the thin film wiring layer 7 as a layer was exposed (step I). Also in this case, the second thin film wiring layer 7 could be used as a polishing stopper.

Thereafter, the third thin film wiring layer 10 is formed in the same manner as in the step A, and the second thin film wiring layer 7 and the third thin film wiring layer 10 are And the three thin film wiring layers 2, 7, 10 are connected to the via 1
1 to obtain a multilayer wiring board connected between layers.

In this embodiment, the photolithography process required for manufacturing a multilayer wiring board having three thin film wiring layers 2, 7, and 10 interconnected by vias is four.
This is a number of times, and the number of photolithography steps can be reduced by one compared with the related art. Therefore, a number of manufacturing steps required for one photolithography step can be omitted, and cost reduction can be achieved.

In this embodiment, the case where the three thin film wiring layers 2, 7, and 10 are connected to each other is described. However, even when four or more thin film wiring layers are connected to each other, the vias 11 are connected. If it is formed high, four or more thin-film wiring layers can be directly connected to each other only by forming a single-layer via.

[0040]

As described above, according to the method for manufacturing a multilayer wiring board of the present invention, after forming the nth thin film wiring layer, the (n + 1) th thin film wiring layer is formed on the nth thin film wiring layer. And) forming a via having a height at which the second thin film wiring layer is raised, and then directly connecting the (n + 1) th and (n + 2) th thin film wiring layers on the via. As a result, the number of photolithography steps is reduced by one compared with the related art, so that many manufacturing steps required for the photolithography step can be omitted, and cost reduction can be achieved.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view for explaining one embodiment of the present invention.

FIG. 2 is a process sectional view showing a conventional manufacturing method.

FIG. 3 is a process sectional view showing a conventional manufacturing method.

[Description of Signs] 1 ... Alumina substrate 2 ... First layer thin film wiring layer 3 ... Dry film 6 ... First layer insulating layer 7 ... Second layer thin film wiring layer 9 ... Second layer insulation Layer 10: Third thin film wiring layer 11: Via

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H05K 3/46

Claims (1)

(57) [Claims] 1. A method of manufacturing a multilayer wiring board, wherein thin-film wiring layers and insulating layers are alternately stacked on a substrate, and the thin-film wiring layers are electrically connected by vias. After forming the first thin film wiring layer, a via having a height capable of raising the (n + 1) th thin film wiring layer formed thereafter is formed on the nth thin film wiring layer, and thereafter, An nth insulating layer and an (n + 1) th thin film wiring layer are sequentially formed, and the nth thin film wiring layer and the (n + 1) th thin film wiring layer are connected by the via. At the same time, the (n + 1) th thin-film wiring layer is raised above the via and the (n +
(1) A first insulating layer and a (n + 2) th thin film wiring layer are sequentially formed, and the (n + 1) th thin film wiring layer and the (n + 2) th thin film are formed on the via. A method for manufacturing a multilayer wiring board, wherein a wiring layer is directly connected between layers.