JPH07288247A - Dry etching method for silicon oxide film - Google Patents

Abstract

PURPOSE:To provide an etching method for a silicon oxide film, which has the smooth side wall and the vertical profile. CONSTITUTION:A hard-baked resist 3, a thin Ti layer 4 and a resist 5 are formed on a silicon oxide film 2 on a substrate. The resist 5 and the Ti layer 4 are patterned, and the resist 5 is removed by oxigen-based reactive ion etching. Then, a resist pattern 3 (b) is formed, and the silicon oxide film 2 at the lower layer undergoes dry etching by reactive ion etching using fluorocarbon gas.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a method for finely removing thin or thick silicon oxide for use in VLSI and photonic integration processes.

The present invention relates to a method for etching doped and undoped silicon oxide having an arbitrary thickness, and more particularly to a deep vertical dry etching method for silicon oxide having smooth sidewalls. In particular, it can be used to etch contact holes in silicon oxide, which is useful in three-dimensional integrated circuits, or thick silicon oxide, which is useful in the production of silica-based optical components, and to make hybrid modules on silicon crystal substrates. it can.

[0003]

BACKGROUND OF THE INVENTION Doped and undoped silicon oxide are etched using plasma assisted ion etching by reactive ion etching (RIE) or reactive ion beam etching (RIBE) using fluorocarbons. As device size shrinks, 1000-5000 angstroms vertical etch is an essential requirement in making contact holes in silicon oxide. To this end, the choice of mask material, along with its smoothness, plays an important role. For etching silicon oxide,
Photoresists and metals are commonly used as mask materials. A general photoresist can be used for etching silicon oxide without any special treatment.

In this case, typical photoresists exhibit a low selectivity, typically 1-2, for etching the underlying silicon oxide in a fluorocarbon gas plasma. Not only that, during the silicon oxide etching process, the plastic flow of the photoresist pattern due to high energy ions expands the etching pattern. For this reason, a single layer of a conventional photoresist mask cannot be used for etching into microstructured patterns that require additional stability of the mask material during the etching process.
It is known in the art to etch silicon or other substrates using a multilayered mask material composed of polyimide and thick Al (aluminum). The same type of multilayered mask can also be used for etching silicon oxide. However, no specific method has been developed that can be used only for etching silicon oxide itself.
For this purpose, the conditions for providing the mask material should be optimized. When conventional processes are used to provide a multi-layered mask, it becomes difficult to achieve a vertical and smooth mask profile, which causes subsequently etched layers to deteriorate their profile shape. Is generally indicated. This etched profile cannot be used for some applications, especially in the manufacture of optical devices.

FIGS. 7A to 7D show an Al metal layer 10
2 shows an example of a typical etching process in which a layer is coated on the Si substrate 1 and deposited on the hard-baked polyimide 9. In a typical process, the thickness of the upper Al layer 10 used is in the range of 1000-2000 angstroms and the pattern is made using dry etching technique with photoresist 11 as mask. It To dry-etch this Al, general reactive ion etching (RI
E) technology is used in a chlorine (Cl) based reactive gas plasma. When the process is performed in a reactive gas plasma, an Al-based compound is deposited on the Al sidewalls, and this passivated layer 12 cannot be easily removed before the polyimide etch. The size of this passivated layer 12 is so large that it is difficult to obtain patterns in the submicron range. This passivated layer can be wet etched using a conventional resist etchant with ultrasonic cleaning.

However, due to this additional process, the partial delamination of the Al pattern was
It occurs due to poor adhesion of l. This is alleviated slightly using a buffer layer between the polyimide and the Al layer.
Japanese Unexamined Patent Publication (Kokai) No. 58-114433 "Improved Curable Polyurethane" discloses forming holes in a silicon wafer by using a two-layer mask composed of Al, C and polyimide layers. C is used to avoid leaving passivated etch residues on the Al pattern and spoiling the pattern. This process requires the additional step of depositing a thin film at a limited rate. Therefore, it is desirable that a simple process using only multilayered masks can be realized using simple means.

[0007]

As mentioned above, the VLS is used.
In I process applications, the thickness of the silicon oxide that is etched typically varies from 1000 to 5000 angstroms. Here, it is the main purpose to achieve submicron range patterns with vertical sidewalls, which are achieved using conventional etching techniques developed to date.

Since a conventional LSI is an electrically based circuit, the smoothness of the side surface of the etched profile does not pose a problem to the overall performance. Etching deep silicon oxide using the same etching process used in VLSI does not yield a vertical, smooth profile. Therefore, for deep etch thicknesses of 2 μm and above, processes should be developed that control the anisotropic etch as well as the side smoothness. In the etching of shallow silicon oxide that can be used in VLSI applications, the verticality of the profile can be controlled by using the process as described above.
Even in this case, when the etching thickness varies up to 5000 Å (often up to 1 μm), common photoresists (eg AZ1350J or PMMA or AZ4903) are used as mask material.
Etc.) of the same thickness is not problematic to some extent in achieving a vertical silicon oxide profile. The shape of the profile depends on the etching conditions and the photoresist treatment. Deep silicon oxide etching can also be performed using thick photoresist masks or other types of hard masks such as metals. If the next underlayer etch profile angle is not considered to be a significant factor, use a photoresist with a thickness equal to or greater than the silicon oxide etch thickness,
It can be used as a mask material for etching deep silicon oxide.

FIGS. 8 (a) and 8 (b) show one typical example of a conventional etching process for deep silicon oxide formed on the silicon oxide 2 where the thick photoresist pattern 15 is etched. As shown in FIG. 8A, when the thickness of the photoresist used as the mask is 1.5 μm or more, it becomes difficult to obtain a vertical mask profile by using a normal photolithography technique, and the oxidation becomes difficult. The etched profile of silicon exhibits a tapered profile angle that depends on the photoresist thickness.

For example, as the thickness of the photoresist becomes thicker, the side wall angle (θ ₁ in FIG. 8A) of the photoresist pattern following photolithography becomes 90 °.
Getting smaller. Therefore, when the tapered photoresist pattern is used as a mask in the subsequent etching of silicon oxide, its etching profile is equal to or less than that of the photoresist mask as shown in FIG. 8B. Always shows the tapered profile angle (θ ₂ ). The profile angle of the underlying etched layer depends not only on the initial resist pattern angle, but also on the etch rate of both the photoresist and the material being etched (in this case silicon oxide). Besides these, the etching conditions also play an important role in the profile angle. For example, if the etching conditions are such that high energy ions are used, the taper angle achieved will be less than or equal to the angle of the photoresist mask, and the underlying etching pattern will be wider due to photoresist mask erosion.
Therefore, it can be seen that the use of a thick photoresist mask provides a tapered profile for the underlying etch. Tapered angles are difficult to control,
It depends on the type and thickness of the photoresist used and also on the etching conditions. Furthermore, if thick photoresist masks are used, vertical etching of deep silicon oxide is also completely impossible. A process for etching deep silicon oxide with a profile angle close to 90 ° must be developed.

For vertical etching of silicon oxide, hard mask materials such as metals can be used. Cr
Alternatively, a metal mask such as a Ni-Cr alloy or Al can be used for etching deep silicon oxide. Figure 9
Is a schematic diagram showing the etching of deep silicon oxide,
Metal mask 1 on silicon oxide 2 deposited on substrate 1
6 is deposited. Following photolithography, a resist pattern 17 is created, followed by a metal pattern 16
(A) is produced using dry etching or wet etching. Whichever etching technique is used, the metal pattern 16 (a) has a side surface roughness of 1
8 is always shown, and subsequent etching of the underlayer 2 also shows side roughness 19. Generally, a metal having a high boiling point such as Cr, Mo, W or the like is used as the metal mask. From a process perspective, using a metal mask is the simplest method for etching deep silicon oxide.

However, it has several drawbacks. For example, a smooth mask pattern is difficult to obtain even using dry etching, therefore etching silicon oxide according to the shape of the mask pattern has a high roughness of the sidewalls of the etched profile. The degree of this side roughness depends on the etching technique by which the metal mask pattern is made. The use of reactive gas plasma or dry etching techniques such as Argon (Ar) ion beam etching techniques cannot reduce the side roughness to a certain extent that is difficult to reach. In the experiments to date, it has been found that the use of a Cr mask results in a side surface roughness of 1200 Angstroms or more resulting from subsequent etching of the silicon oxide. This level of side roughness produced in the etched profile cannot be used in applications where a smooth vertical etch is highly desired, especially in photonic integration process applications. Therefore, it is clear that a well-defined process must be developed for deep silicon oxide etching. Any common etching technique can be used to etch silicon oxide, but it is difficult to obtain a vertical profile with smooth sidewalls. To obtain a vertical profile with smooth sidewalls, an etching process involving mask smoothness must be performed prior to etching the underlying silicon oxide.

[0013]

The above-mentioned problems can be completely solved by using the present invention. In the present invention, different techniques are used to achieve vertically etched profiles with smooth sidewalls for shallow and deep silicon oxide etching.

First, the method encountered in the etching of conventional microstructured silicon oxide will be described. This etching method is used for etching of ordinary photoresist, as compared to etching of silicon oxide in the submicron range.
It is based on the use of multilayered masks made of thin metal and photo-insensitive resist. In this case, titanium (Ti) is used as the metal mask. The reason is Ti
Shows good adhesion to the hard-baked resist. It has been found that cracking occurs when other metals such as chromium (Cr) are used on the hard baked resist. Compared to the conventional etching process in which a multi-layered mask with a thick layer of Al is used, we have found that T with a thickness of 600 angstroms or less.
Use a thin layer of i. As a result, either wet etching or simple ion beam etching gives vertical and smooth Ti patterns. Therefore, the problems that occur in the conventional process due to the roughness of Al by reactive dry etching can be overcome. The buffer layer (see JP-A-58-114433, cited above) is no longer needed to enhance the adhesion of the metal to the hard baked resist.

The hard baked resist is then dry etched using oxygen-based RIE instead of using ion beam etching (IBE) techniques. The process pressure is below 8 Pascal and the electric power is below 0.
It is 20 W / cm ² or less. The process self-bias is −
400V or more. Under this condition, it was found that the etching rate of the hard-baked resist was 700 angstroms / minute or more, and the Ti etching rate was almost negligible. The upper metal layer can be etched or left prior to the subsequent etching of the silicon oxide.

For deep silicon oxide etching with high yield, a buffer layer consisting of a thin metal layer between the silicon oxide and the photo-insensitive resist is used. The use of a photo-insensitive resist instead of a photoresist increases the stability of the mask during the etching process and allows for a more vertical profile with less lateral roughness. Unless otherwise defined, the term resist means the photoinsensitive resist used as the primary layer in this example. Hard baking the resist at temperatures above 240 ° C. is done to release moisture and other unwanted gases from the resist. 1.5-2.0 μm for etching thin silicon oxide
Hard baked resist is used to avoid resist erosion. However, deep silicon oxide etching requires a resist thickness of 1-2 μm greater than the desired silicon oxide etch thickness, which is spin coated using multi-step spinning. Then, following each step, a high temperature bake is required and moisture and other unwanted gases can be released during the bake.

The use of a thin metal between the silicon oxide and the hard-baked resist as a buffer layer can improve the stability of the upper, multilayered mask to reactive plasmas. Otherwise, the poor adhesion of the hard-baked resist to silicon oxide causes the multi-layered mask pattern to delaminate during the lengthy silicon oxide etching process, resulting in undesired silicon oxide etch profiles. It is made. The thickness of the buffer metal layer is 150 angstroms or less. A feature of the present invention is that this thin buffer metal layer not only improves the stability of the top hard-baked photoresist against silicon oxide, but also acts as an etch stop during the patterning of the hard-baked resist. Is. Following the etching of the underlayer, the remaining top hard-baked resist can be lifted off by wet etching the metal. Smoothing the mask pattern plays an important role in the subsequent etching profile.

Vertical patterns of hard-baked resists are obtained using oxygen-based RIE techniques operated at pressures below 8 Pascal and self-bias above -400V. Under this condition, the etch rate of the hard-baked photo-insensitive resist is 700 Å / min or more, and the thin Ti on top is not etched. In order to obtain smooth sidewalls for the etch profile, patterning the hard-baked resist is followed by a buffer metal surface and passivated etch residue on the sidewalls of the hard-baked resist, the top metal used. The sample can be immersed and etched in a common wet etchant (Ti in this case). For example, if the top metal is Ti, the etch residue is etched using a solution containing Ti etchant or NH ₄ F.

However, different types of metal layers must be used for both the buffer layer and the top metal.
As mentioned above, it has been found that when Cr is used as the top mask, cracks occur in the metal deposited or deposited on the hard-baked resist. This is,
That is why it is not recommended to use Cr as the upper metal layer. This experiment was performed using Ti as the top metal and Cr as the buffer layer. Other combinations can be used. The metal of the buffer layer should be a thin metal layer of the kind that has a high boiling point and can be easily dry-etched with a fluorocarbon gas plasma (fluorocarbon gas is used to etch silicon oxide). S
i or polysilicon, or can withstand temperatures of 250 ° C. or higher and cannot be dry-etched by oxygen plasma, for example, Mo, Ni—Cr alloy, Ti, WSi
It can be any type of metal, such as _x , Pt, Ta, etc.

The upper metal may be different from the lower thin metal and may be Ti, Al, Si, polysilicon or the like. The top metal layer should not be the same metal as the buffer layer. The reason is that, following oxygen-based RIE, the etch residues that are believed to form on the etched surface and sidewalls of the hard-baked resist are wet etched prior to the etching of the underlying silicon oxide. Because. If the same type of metal is used, a wet-baked resist etch followed by a wet etch lifts off the overlying multilayered mask. In this experiment, a photo-insensitive resist was used. However, instead of using a resist, any type of polymer that is spin-coated and deposited can be used.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT First, an etching process which is often used in VLSI applications and which can be used to make fine-structured fine holes in silicon oxide is described. Figure 1
Is the first to fabricate microstructured silicon oxide patterns
FIG. 6 is a diagram showing an etching process in the example of FIG.

A doped and undoped silicon oxide 2 having an arbitrary thickness is deposited on a silicon substrate 1.
Subsequently, a photo-insensitive resist 3 (for example, trade name: OFR-GA2) having a thickness of 1.5 μm or more is spin-coated, and then it is baked at a temperature of 240 ° C. or more for 45 minutes or more. It should be noted that the resist used in this example is a light insensitive resist unless otherwise stated. 6 after hard baking
A thin layer of Ti4 with a thickness of less than 00 Å,
It is vapor-deposited on the hard-baked resist 3 and patterned by using a general photolithography technique.

A feature of this embodiment is the use of a thin layer of Ti compared to the conventional etching process (see FIG. 7). Following photolithography, a thin layer of Ti can be wet etched using a common etchant or dry etched using IBE to form the Ti pattern 4 (a). The advantage of using thin Ti is that its pattern 4 (a)
Does not require reactive ion etching to form
Therefore, problems such as those found in conventional processes, such as passivation of etch residues on the sidewalls and delamination of the pattern during etching of the passivated layer, do not occur.

Following the formation of Ti pattern 4 (a), the top hard-baked resist is etched using an oxygen-based reactive ion etching technique. The process pressure and power are 8 Pascal or less and 0.20 W / cm ² or less, respectively, and the self-bias voltage is -4.
It is set to 00V or more. The gas flow rate should be kept as low as possible to avoid undercuts that make the resist pattern thinner.

Another feature of the invention is the oxygen-based IBE.
The result of using RIE instead of using is that there is also no damage due to the relatively high energy ions. Following the formation of the hard-based resist pattern 3 (b), the underlying silicon oxide is removed by RIE or RIB.
Dry etch in a fluorocarbon gas plasma using a technique such as E technique. The upper metal is
With Ti typically having a selectivity of 10 or less for etching silicon oxide depending on the etching thickness of silicon oxide, the top Ti layer is left with a mask of hard-baked resist. In that case, both are separately wet etched using a conventional wet etchant followed by silicon oxide etching (not shown in FIG. 1).

FIG. 2 shows the etching process of silicon oxide for the submicron range in the second embodiment. In FIG. 2, the same members as those in the first embodiment are designated by the same reference numerals. In the second embodiment,
Following the formation of hard-baked resist pattern 3 (b), the top thin Ti metal is wet etched using a conventional wet etchant containing ammonia hydroxide. If the resist pattern is created in an oxygen plasma, the Ti surface can oxidize, in which case a two stage wet etch is used. After that, the silicon oxide is etched using only the hard-baked resist pattern 3 (b) as a mask. The use of hard-baked resist pattern 3 (b) as a mask for etching the underlying silicon oxide does not affect the etch profile shape.

In this embodiment (FIGS. 1 and 2),
Thin Ti was used as a mask for patterning the hard baked resist. Si, polysilicon, Al, Mo which is difficult to etch with oxygen plasma
Other types of materials such as etc. can be used as mask materials to create patterns of hard baked resist. In this example, a photo-insensitive resist was used for the multilayered mask. A general photoresist can also be used. However, in that case, the baking temperature is
It must be about 300 ° C. (even higher due to its glass transition temperature) in order to make the photoresist light insensitive during plasma exposure. Since the thin Ti layer is used as a mask material in etching hard-baked resist, no additional dry etching process using reactive gas is required. Therefore, there is no opportunity for passivated etch residues to form during the etch, and no opportunity for stripping of the pattern during the etch of the passivated layer. Therefore, the patterns of both the hard baked resist and the silicon oxide etch are more vertical and smooth.
These examples, if using conventional processes,
It is very difficult to achieve.

In the above, the process for the etching of shallow silicon oxide in the submicron range has been described. The following describes different processes developed for etching silicon oxide of any thickness, especially for deep silicon oxide deeper than 2 μm.
It should be noted that the same type of process can also be used to etch silicon oxide in the shallow submicron range. The etching process as described above also
Can be used for deep silicon oxide etching. The only difference is the thick hard-baked resist. In this case, etching of silicon oxide is possible only under constant etching conditions. This is because delamination of the multilayered mask occurs due to high energy ion injection during the etching process. This problem occurs whenever the silicon oxide etching process is lengthened depending on the etching thickness. This was initially thought to be due to pre-contamination of the silicon oxide surface which weakens its adhesion to the spin-coated resist. This problem is also not mitigated by subjecting the silicon oxide to a high temperature treatment prior to spin coating the resist to remove pre-contamination. As a result, it was confirmed that the hard-baked resist had poor adhesion to silicon oxide. This problem is mitigated using a thin buffer layer between the hard-baked resist and silicon oxide.

FIG. 3 is a diagram showing a silicon oxide etching process according to a third embodiment of the present invention.
In FIG. 3, the same members as those in the first embodiment are designated by the same reference numerals. Therefore, repeated description is omitted here. In the third embodiment, a thin buffer layer 6 having a thickness of 150 Å or less is deposited on the silicon oxide 2 before the spin coating of the resist 7. This type of material used as the buffer layer 6 has a high boiling point and must not be dry etched with oxygen plasma. In this example, Cr was used. Mo, Ni-Cr
Other materials such as alloys, Ti, Ta, Pt, Si, polysilicon can also be used.

Following the formation of the buffer layer 6, a photo-insensitive resist (eg, trade name: OFR-GA2, etc.) is spin-coated on the buffer layer 6, which is then applied under the same conditions as previously described 45. Bake hard for more than a minute. The resist used is
Unless otherwise stated, all types of light insensitive resists. In this case, the thickness of the spin-coated resist depends on the etching thickness of silicon oxide. There is always a need for resists with a thickness of 1 μm or more compared to the etched thickness of silicon oxide, which is done using multi-step spin coating, followed by a long high temperature bake. Is required (under the conditions mentioned above).

Next, a thin layer 8 of metal such as Ti having a thickness of 600 angstroms or less is deposited on the hard-baked resist 7. A feature of this embodiment is the use of two different types of materials for the buffer layer 6 and the top layer 8. For example, in this example, the top layer 8 is Ti and the buffer layer 6 is Cr. Other processes following this step have already been described in the first example. Therefore, their description is omitted here. In this example, a light-insensitive hard bake resist was used. Broadly, it can be a polyimide containing all types of resists. In addition to Cr / hard-baked resist / Ti, Mo / hard-baked resist / Ti, or W / hard-baked resist /
Ti, or WSi _x / hard-baked resist /
Other combinations such as Ti and the like can be used. Instead of Ti, Al can be used in these combinations. In the third example, a multi-layer mask over the Cr buffer layer was used for subsequent silicon oxide etching. The feature of this embodiment is that the hard-baked resist left on the buffer layer can be lifted off by the wet etching of the buffer layer during the ultrasonic cleaning, following the etching of the underlying silicon oxide.

FIG. 4 is a diagram showing an etching process for deep silicon oxide in the fourth embodiment. In FIG. 4, the same members as those in the first and third embodiments are designated by the same reference numerals. Therefore, repeated description is omitted here. Similar to the second embodiment, the upper thin Ti is wet-etched before the silicon oxide is etched. As mentioned above, different layers are used for the buffer layer and the top layer, so that the wet etching of the top metal does not make the buffer layer a wet etch. The silicon oxide is then etched using the hard baked resist mask 7 (b) on the buffer layer 6. The other processes subsequent to this step have already been described in the third embodiment, and the description thereof will be omitted here.
The finally obtained etching profile was not affected at all.

FIG. 5 is a schematic diagram showing an etching process for etching deep silicon oxide in the fifth embodiment. 5, the same members as those in the first and third embodiments are designated by the same reference numerals. Therefore,
A similar description is omitted here. Prior to etching the silicon oxide, the lower buffer layer 6 was wet etched using a commercially available wet etch to form a pattern 6
(C) can be produced. Resist pattern 7
It should be noted that when (b) is formed using oxygen plasma, the surface of the buffer layer 6 may be oxidized.
In that case, when oxidation occurs, two-step wet etching including wet etching of the buffer layer and wet etching of the oxide layer is performed. As mentioned above, this type of material chosen for the buffer layer must not be easily oxidized by the oxygen plasma. It will be appreciated that if Cr is used for the buffer layer, its oxide layer (if any) can be wet etched using conventional wet etchants. Wet etching requires a few seconds because a thin layer is used for the buffer layer. The other processes subsequent to this step are the same as those described in the first and third embodiments, and thus the description thereof is omitted here.

FIG. 6 is a diagram showing an etching process for deep silicon oxide in the sixth embodiment. 6, the same members as those in the first, second, third, fourth and fifth embodiments are designated by the same reference numerals. Therefore, repeated description is omitted here. Before etching the silicon oxide, the upper thin Ti layer 8 is wet etched. As a result, the hard-baked resist 7 (b) along with the thin buffer layer 6 (c) is used as a mask for subsequent silicon oxide etching. The process following this step has already been described in the third example. This embodiment is not only used in VLSI applications where etching of submicron silicon oxide is desired, but also in applications such as three-dimensional VLSI processes and photonic integration where deep silicon oxide etching is required. used.

[0035]

According to the present invention, it is possible to form silicon oxide holes in the submicron range of 0.2 μm or less. In addition, etching of deep silicon oxide having a good controllability of the etching profile of 20 μm or more
RIE or RI in fluorocarbon gas plasma
This can be done using BE.

[Brief description of drawings]

FIG. 1 is a diagram showing an etching process of shallow silicon oxide in a submicron range according to a first embodiment.

FIG. 2 is a diagram showing an etching process of silicon oxide in a submicron range according to a second embodiment.

FIG. 3 is a diagram showing an etching process of a silicon oxide having an arbitrary thickness in the third embodiment, in particular, a deep silicon oxide etching process.

FIG. 4 is a diagram showing an etching process of a silicon oxide having an arbitrary thickness, in particular, a deep silicon oxide etching process according to a fourth embodiment.

FIG. 5 is a diagram showing an etching process of deep silicon oxide in a fifth embodiment.

FIG. 6 is a diagram showing a deep silicon oxide etching process in a sixth embodiment.

FIG. 7 is a diagram showing an etching process of silicon oxide in the submicron range.

FIG. 8 shows a general etching process for deep silicon oxide.

FIG. 9 shows a general etching process for deep silicon oxide.

[Explanation of symbols]

 1 substrate 2 silicon oxide film 3 resist pattern 4 Ti pattern 5 photoresist pattern 6 metal buffer layer 7 resist pattern 8 upper metal 9 polyimide 10 Al layer 11 photoresist 12 passivated layer 15 thick photoresist pattern 16 metal pattern 17 resist pattern 18 Side roughness 19 Side roughness

Claims (12)

[Claims] 1. A method of dry-etching shallow silicon oxide in the submicron range, which comprises a step (A) of producing a multilayer mask, which step comprises:
(A) A step of forming a photoresist pattern (5) using photolithography, (b) a step of forming a thin Ti pattern 4 (a), and (c) a hard-baked light-insensitive resist pattern. 3 (b), and (B) dry etching the underlying silicon oxide (2) using a fluorocarbon gas-based reactive ion etching or reactive ion beam etching technique. A method for dry etching a silicon oxide film, comprising: 2. The method of dry etching a shallow silicon oxide film according to claim 1, wherein the hard-baked photo-insensitive register pattern 3 is used.
Etching (b) using oxygen-based reactive ion etching (RIE) under the conditions of a pressure of 8 Pa (pascal) or less, a power of 0.2 W / cm ² or less, and a self-bias of -400 V or more. A dry etching method for a silicon oxide film, which is produced by performing wet etching for several seconds using an etchant containing ammonia hydroxide to remove a residue. 3. The method for dry etching a shallow silicon oxide film according to claim 1, wherein instead of using thin Ti, it has good adhesion to a hard-baked resist and is deposited at 200 ° C. or lower. A method of dry etching a shallow silicon oxide film, characterized by using Si or SiN _x . 4. The method for dry etching a shallow silicon oxide film according to claim 1, wherein the underlying silicon oxide (2) is etched by a mask pattern of a hard-baked photo-insensitive resist pattern 3 (b), or Photo-insensitive resist pattern 3 (b)
And a thin Ti pattern 4 (a) are used as a mask pattern to perform a dry etching method for a silicon oxide film. 5. A method of dry etching deep silicon oxide, comprising the step of: (A) producing a multi-layered mask.
(A) a step of forming a photoresist pattern using photolithography, and (b) a metal pattern 8 (a)
And (c) a hard-baked polymer pattern 7 (b) on a thin metal (6) to be a buffer layer, and (B) a fluorocarbon gas using a reactive ion etching technique. A dry etching method for a silicon oxide film, which has a step of dry etching silicon oxide with plasma. 6. The method for dry etching a deep silicon oxide film according to claim 5, wherein the kinds of materials used as the buffer layer (6) and the upper metal (8) are different from each other. Dry etching method. 7. The method of dry etching a deep silicon oxide film according to claim 5, wherein the upper metal (8) provided on the hard-baked resist (7) is Ti or amorphous Si or Si.
A dry etching method for a silicon oxide film, wherein the dry etching method is any one of N _x . 8. The method of dry etching a deep silicon oxide film according to claim 5, wherein the hard-baked material (7) used is 300 ° C.
A dry etching method for a silicon oxide film, which is a resist (light-sensitive or light-insensitive) that can endure the above and can be easily dry-etched using oxygen plasma. 9. The method of dry etching a deep silicon oxide film according to claim 5, wherein the silicon oxide (2) is used as an upper metal pattern 8 (a) and a buffer layer (6) used to enhance the adhesion. A method of dry etching a silicon oxide film, which comprises etching using a mask pattern made of the above hard-baked resist 7 (b). 10. The method for dry etching a deep silicon oxide film according to claim 5, wherein the silicon oxide (2) is used to enhance the adhesion of the hard-baked resist (7) to the silicon oxide (2). Dry etching method for a silicon oxide film, characterized in that dry etching is performed using the mask pattern of the hard-baked resist 7 (b) on the buffer layer (6). 11. The method for dry etching a deep silicon oxide film according to claim 5, wherein the silicon oxide (2) is used as a thin metal 8 (a), a hard-baked resist 7 (b), and a lower thin metal 6 are formed.
A dry etching method for a silicon oxide film, which comprises etching using a mask pattern consisting of (c). 12. The method of dry etching a deep silicon oxide film according to claim 5, wherein the silicon oxide (2) is hard-baked in the resist 7.
A dry etching method for a silicon oxide film, which comprises etching using a mask pattern composed of (b) and a thin buffer layer 6 (c).