JPH03211834A - Formation of wiring pattern - Google Patents
Formation of wiring patternInfo
- Publication number
- JPH03211834A JPH03211834A JP634590A JP634590A JPH03211834A JP H03211834 A JPH03211834 A JP H03211834A JP 634590 A JP634590 A JP 634590A JP 634590 A JP634590 A JP 634590A JP H03211834 A JPH03211834 A JP H03211834A
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring pattern
- thickness direction
- coating film
- insulating substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title 1
- 229910052751 metal Inorganic materials 0.000 claims abstract description 35
- 239000002184 metal Substances 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000000463 material Substances 0.000 claims description 11
- 238000010030 laminating Methods 0.000 claims description 4
- 238000007743 anodising Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 abstract description 23
- 238000000576 coating method Methods 0.000 abstract description 23
- 230000003647 oxidation Effects 0.000 abstract description 7
- 238000007254 oxidation reaction Methods 0.000 abstract description 7
- 238000000206 photolithography Methods 0.000 abstract description 6
- 239000003792 electrolyte Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 46
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000008151 electrolyte solution Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- ing And Chemical Polishing (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はLSI、薄膜デバイス等の半導体製造プロセス
に用いられる配線パターンの形成方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming wiring patterns used in semiconductor manufacturing processes such as LSIs and thin film devices.
従来、ガラス等の絶縁基板上に配線パターンを形成する
場合、フォトリソグラフィ法が用いられる。このフォト
リソグラフィ法は、蒸着あるいはスパッタ笠の方法によ
って絶縁基板上に形成された金属膜の上にレジスト材を
積層し、このレジスト材を所定パターンのマスクを用い
て露光し、さらに現像処理した後に金属膜を膜厚方向に
エツチングして基板上に配線パターンを形成する方法で
ある。Conventionally, a photolithography method is used when forming a wiring pattern on an insulating substrate such as glass. In this photolithography method, a resist material is layered on a metal film formed on an insulating substrate by vapor deposition or sputtering method, this resist material is exposed to light using a mask with a predetermined pattern, and then developed. This method forms a wiring pattern on a substrate by etching a metal film in the film thickness direction.
しかしながら、上述したフォトリソグラフィ法はレジス
トの解像度やエツチング技術に限界があるため、絶縁基
板上に微小面積の配線パターンを形成することは困難で
あった。However, since the photolithography method described above has limitations in resist resolution and etching technology, it has been difficult to form a wiring pattern with a minute area on an insulating substrate.
本発明は上記のような事情に鑑みてなされたもので、そ
の目的は絶縁基板上に微小面積の配線パターンを形成す
ることのできる配線パターンの形成方法を提供すること
にある。The present invention has been made in view of the above circumstances, and its object is to provide a method for forming a wiring pattern that can form a wiring pattern with a minute area on an insulating substrate.
上記課題を解決するために本発明による配線パターンの
形成方法は、絶縁基板上に配線パターン形成用の金属膜
を形成する工程と、前記金属膜の上に該金属膜とは異な
る金属からなる被膜を形成する工程と、前記被膜の上に
マスク材を積層する工程と、前記マスク材で覆われてい
ない部分の被膜を膜厚方向にエツチングする工程と、こ
の工程の後に前記被膜の一部を陽極酸化する工程と、こ
の工程の後に陽極酸化されていない被膜を膜厚方向にエ
ツチングする工程と、この工程の後に陽極酸化された被
膜をマスクとして前記金属膜を膜厚方向にエツチングす
る工程とを具備したものである。In order to solve the above problems, a method for forming a wiring pattern according to the present invention includes a step of forming a metal film for forming a wiring pattern on an insulating substrate, and a coating made of a metal different from the metal film on the metal film. , a step of laminating a mask material on the film, a step of etching the part of the film not covered with the mask material in the film thickness direction, and after this step, a part of the film is removed. a step of anodizing, a step of etching the non-anodized film in the thickness direction after this step, and a step of etching the metal film in the thickness direction using the anodized film as a mask after this step. It is equipped with the following.
すなわち、本発明では陽極酸化された被膜をマスクとし
て金属膜を膜厚方向にエツチングするので、絶縁基板上
に微小面積の配線パターンを形成することができる。That is, in the present invention, since the metal film is etched in the film thickness direction using the anodized film as a mask, a wiring pattern with a minute area can be formed on the insulating substrate.
以下、本発明の一実施例を第1a図〜第1h図を参照し
て説明する。Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 1a to 1h.
第1a図〜第1h図において、1はガラス等からなる絶
縁基板であり、この絶縁基板1上に微小面積の配線パタ
ーンを形成する場合には、まず第1a図に示すように絶
縁基板1上にクロム等からなる配線パターン形成用の金
属膜2を蒸着あるいはスパッタ等の方法により形成する
。1a to 1h, reference numeral 1 denotes an insulating substrate made of glass or the like. When forming a wiring pattern with a minute area on this insulating substrate 1, first place the insulating substrate 1 on the insulating substrate 1 as shown in FIG. 1a. Then, a metal film 2 for forming a wiring pattern made of chromium or the like is formed by a method such as vapor deposition or sputtering.
次に第1b図に示すように金属膜2の上に金属膜2とは
異なる金属(例えばアルミニウム等)からなる被膜3を
蒸着あるいはスパッタ等の方法により形成する。Next, as shown in FIG. 1b, a coating 3 made of a metal different from the metal film 2 (for example, aluminum) is formed on the metal film 2 by a method such as vapor deposition or sputtering.
次に第1C図に示すように被膜3の上にマスク材として
のレジスト4を積層した後、第1d図に破線で示すよう
にレジスト4で覆われていない部分の被83を膜厚方向
にエツチングする。そして、エツチング後に被膜3を電
解液に浸し、被膜3の一部を陽極酸化する。このとき、
陽極酸化は被膜3の端部側から膜厚方向と直交する方向
に進行する。したがって、陽極酸化の時間を予め定めて
おくことにより、第1e図に示すように被膜3の端部に
微小面積の陽極酸化部3aを作ることができる。Next, as shown in FIG. 1C, after laminating a resist 4 as a mask material on the coating 3, the coating 83 in the portion not covered with the resist 4 is removed in the film thickness direction as shown by the broken line in FIG. 1D. Etching. After etching, the coating 3 is immersed in an electrolytic solution, and a portion of the coating 3 is anodized. At this time,
Anodic oxidation proceeds from the end side of the coating 3 in a direction perpendicular to the film thickness direction. Therefore, by predetermining the anodic oxidation time, it is possible to form an anodized portion 3a with a minute area at the end of the coating 3, as shown in FIG. 1e.
次にレジスト4を除去した後、第1f図に破線で示すよ
うに陽極酸化されていない部分の被膜3を膜厚方向にエ
ツチングし、金属膜2の上に陽極酸化された被膜つまり
陽極酸化部3aのみを残す。Next, after removing the resist 4, the part of the coating 3 that has not been anodized is etched in the film thickness direction as shown by the broken line in FIG. Leave only 3a.
なお、このとき金属膜2は被膜3と異なる金属(例えば
クロム等)から形成されているので、被膜3と共にエツ
チングされることはない。Note that, at this time, since the metal film 2 is made of a metal different from that of the coating 3 (for example, chromium, etc.), it is not etched together with the coating 3.
その後、第1g図に示すように被膜3の陽極酸化部3a
をマスクとして金属膜2を膜厚方向にエツチングする。Thereafter, as shown in FIG. 1g, the anodized portion 3a of the coating 3 is
The metal film 2 is etched in the film thickness direction using as a mask.
そして、エツチング後に第1g図に破線で示すように陽
極酸化部3aをエツチングすることにより、絶縁基板1
上に微小面積の配線パターンを形成することができる。After etching, the anodized portion 3a is etched as shown by the broken line in FIG. 1g, thereby etching the insulating substrate 1.
A wiring pattern with a minute area can be formed thereon.
なお、金属膜2は被膜3と異なる金属であるので、陽極
酸化部3aとも異なる。よって、金属膜2は陽極酸化部
3aと共にエツチングされることはない。Note that since the metal film 2 is made of a different metal from the coating 3, it is also different from the anodized portion 3a. Therefore, the metal film 2 is not etched together with the anodized portion 3a.
したがって、上記実施例では陽極酸化された被膜つまり
陽極酸化部3aをマスクとして金属膜2を膜厚方向にエ
ツチングするので、フォトリソグラフィ法で形成される
配線パターンよりもさらに微小面積の配線パターンを絶
縁基板1上に形成することができる。Therefore, in the above embodiment, since the metal film 2 is etched in the film thickness direction using the anodized film, that is, the anodized portion 3a as a mask, a wiring pattern having a smaller area than that formed by photolithography is insulated. It can be formed on the substrate 1.
なお、上記実施例では被膜3の上に積層されるマスク材
としてレジスト4を用いたが、レジスト以外のマスク材
でも実施可能である。また、本発明の要旨を逸脱しない
範囲で種々の変形実施が可能であることは改めて説明す
るまでもない。In the above embodiment, the resist 4 was used as the mask material laminated on the coating 3, but it is also possible to use a mask material other than resist. Further, it goes without saying that various modifications can be made without departing from the gist of the present invention.
以上説明したように本発明は、絶縁基板上に配線パター
ン形成用の金属膜を形成する工程と、前記金属膜の上に
該金属膜とは異なる金属からなる被膜を形成する工程と
、前記被膜の上にマスク材を積層する工程と、前記マス
ク材で覆われていない部分の被膜を膜厚方向にエツチン
グする工程と、この工程の後に前記被膜の一部を陽極酸
化する工程と、この工程の後に陽極酸化されていない被
膜を膜厚方向にエツチングする工程と、この工程の後に
陽極酸化された被膜をマスクとして前記金属膜を膜厚方
向にエツチングする工程とを具備したものである。した
がって、フォトリソグラフィ法で形成される配線パター
ンよりもさらに微小面積の配線パターンを絶縁基板上に
形成することができる。As explained above, the present invention includes a step of forming a metal film for forming a wiring pattern on an insulating substrate, a step of forming a film made of a metal different from the metal film on the metal film, and a step of forming a film made of a metal different from the metal film on the metal film. a step of laminating a mask material thereon, a step of etching the portion of the film not covered with the mask material in the film thickness direction, a step of anodizing a part of the film after this step, and this step. This method comprises a step of etching the unanodized film in the film thickness direction after this step, and a step of etching the metal film in the film thickness direction using the anodic oxidized film as a mask after this step. Therefore, a wiring pattern with an even smaller area can be formed on the insulating substrate than a wiring pattern formed by photolithography.
第1a図〜第1h図は本発明の一実施例を示す配線パタ
ーンの形成工程図である。
1・・・絶縁基板、2・・・金属膜、3・・・被膜、3
a・・・陽極酸化部、4・・・レジスト。FIGS. 1a to 1h are process diagrams for forming a wiring pattern showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Insulating substrate, 2... Metal film, 3... Coating, 3
a...Anodized part, 4...Resist.
Claims (1)
工程と、前記金属膜の上に該金属膜とは異なる金属から
なる被膜を形成する工程と、前記被膜の上にマスク材を
積層する工程と、前記マスク材で覆われていない部分の
被膜を膜厚方向にエッチングする工程と、この工程の後
に前記被膜の一部を陽極酸化する工程と、この工程の後
に陽極酸化されていない被膜を膜厚方向にエッチングす
る工程と、この工程の後に陽極酸化された被膜をマスク
として前記金属膜を膜厚方向にエッチングする工程とを
具備したことを特徴とする配線パターンの形成方法。A step of forming a metal film for forming a wiring pattern on an insulating substrate, a step of forming a film made of a metal different from the metal film on the metal film, and a step of laminating a mask material on the film. , a step of etching the portion of the film not covered with the mask material in the film thickness direction, a step of anodizing a part of the film after this step, and a step of removing the unanodized film after this step. A method for forming a wiring pattern, comprising the steps of etching in the thickness direction, and after this step, etching the metal film in the thickness direction using an anodized film as a mask.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP634590A JPH03211834A (en) | 1990-01-17 | 1990-01-17 | Formation of wiring pattern |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP634590A JPH03211834A (en) | 1990-01-17 | 1990-01-17 | Formation of wiring pattern |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03211834A true JPH03211834A (en) | 1991-09-17 |
Family
ID=11635785
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP634590A Pending JPH03211834A (en) | 1990-01-17 | 1990-01-17 | Formation of wiring pattern |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03211834A (en) |
-
1990
- 1990-01-17 JP JP634590A patent/JPH03211834A/en active Pending
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