JP2527579B2 - Method for manufacturing thin film transistor - Google Patents
Method for manufacturing thin film transistorInfo
- Publication number
- JP2527579B2 JP2527579B2 JP29092387A JP29092387A JP2527579B2 JP 2527579 B2 JP2527579 B2 JP 2527579B2 JP 29092387 A JP29092387 A JP 29092387A JP 29092387 A JP29092387 A JP 29092387A JP 2527579 B2 JP2527579 B2 JP 2527579B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- pattern
- insulating
- patterning
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000010409 thin film Substances 0.000 title claims description 6
- 238000000034 method Methods 0.000 title description 12
- 239000010408 film Substances 0.000 claims description 94
- 239000004065 semiconductor Substances 0.000 claims description 25
- 238000000059 patterning Methods 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 230000001681 protective effect Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910006404 SnO 2 Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Description
【発明の詳細な説明】 （イ） 産業上の利用分野 本発明は薄膜トランジスタ（以後TFTと称す）の製造
方法に関し、特にアクティブマトリクス型の液晶ディス
プレイに用いられるTFTの製造方法に関する。The present invention relates to a method of manufacturing a thin film transistor (hereinafter referred to as a TFT), and more particularly to a method of manufacturing a TFT used for an active matrix type liquid crystal display.
（ロ） 従来の技術 近年、TFTを使用したアクティブマトリクス型の液晶
ディスプレイの開発が盛んであり、例えば、日経マイク
ロデバイス1986年11月号の記事「CRTに迫る液晶アクテ
ィブ・マトリクス・ディスプレイ」（51頁〜53頁）に詳
しい。(B) Conventional technology In recent years, active matrix type liquid crystal displays using TFTs have been actively developed. For example, Nikkei Microdevices November 1986 issue, “Liquid Crystal Active Matrix Display Approaching CRT” (51 Page 53).
このような液晶ディスプレイは小型・薄型が可能であ
る事から、CRTに代わるものとして注目されているもの
の、TFTの構造の複雑さから製造工程数が多くなり、コ
スト高となる欠点があった。Since such a liquid crystal display can be made small and thin, it has been attracting attention as an alternative to a CRT, but it has the drawback of increasing the number of manufacturing steps and increasing the cost due to the complexity of the TFT structure.
例えば、第３図に示す一般的な従来のTFTを基板
（Ｂ）上に製造する場合には、ゲート電極（Ｇ）ゲート
絶縁膜（Ｉ）、アモルファス−シリコン膜からなる半導
体膜（Ａ）、保護膜（Ｐ）、ドレイン電極（Ｄ）並びに
ソース電極（Ｓ）、さらに表示電極（Ｅ）を夫々パター
ニニング形成する為に、少なくとも６回のマスク工程が
必要であった。又、さらにTFTに信号蓄積用容量を内蔵
したり遮光膜を付設する場合には、８〜９回のマスク工
程を必要とする。For example, in the case of manufacturing a general conventional TFT shown in FIG. 3 on a substrate (B), a gate electrode (G), a gate insulating film (I), a semiconductor film (A) made of an amorphous-silicon film, At least 6 mask processes were required to form the protective film (P), the drain electrode (D), the source electrode (S), and the display electrode (E) by patterning. Further, when the TFT has a built-in signal storage capacitor or a light-shielding film is additionally provided, the mask process is required 8 to 9 times.
従って、従来のTFTの製造方法では、工程数が多くな
り、これが歩留り低下を招く要因となっていた。Therefore, in the conventional TFT manufacturing method, the number of steps is increased, which causes a decrease in yield.
（ハ） 発明が解決しようとする問題点 本発明は上述の点に鑑みてなされたものであり、TFT
製造時のマスク工程の削減を図るものである。(C) Problems to be Solved by the Invention The present invention has been made in view of the above points, and TFT
It is intended to reduce the number of mask processes during manufacturing.
（ニ） 問題点を解決するための手段 本発明の薄膜トランジスタの製造方法は、絶縁基板上
に、透明導電膜と導電膜を順次堆積形成する工程と、前
記透明導電膜と導電膜を、ゲート電極と表示電極とのパ
ターンを兼ねる露光マスクを用いて、夫々パターニング
する工程と、絶縁基板上のゲート電極形成面側に第１の
絶縁膜、半導体膜、第２の絶縁膜を順次堆積形成する工
程と、前記第２の絶縁膜と前記半導体膜のパターンを兼
ねる露光マスクを用いて、第２の絶縁膜の外形と半導体
膜を夫々パターニングする工程と、前記第１の絶縁膜
の、上記表示電極の少なくとも一部が露出するパターン
と、第２の絶縁膜のソースあるいはドレインのコンタク
ト用開口のパターンを兼ねる露光マスクを用いて、これ
ら絶縁膜をパターニングする工程と、前記第１の絶縁膜
から露出した前記表示電極の前記導電膜を、エッチング
除去する工程と、上記絶縁基板の表面に、上記開口と上
記表示電極を含むように、不純物がドーピングされた半
導体膜、及び金属膜を順次堆積形成する工程と、前記開
口に配置されるソースあるいはドレイン電極のためのパ
ターン及び、上記電極のうちいずれか一方を前記表示電
極にまで延出せしめたパターンを備えた露光マスクによ
って、上記金属膜及び上記不純物がドーピングされた半
導体膜をパターニングする工程と、からなるものであ
る。(D) Means for Solving the Problems A method of manufacturing a thin film transistor according to the present invention includes a step of sequentially depositing and forming a transparent conductive film and a conductive film on an insulating substrate, and the transparent conductive film and the conductive film as a gate electrode. Patterning using an exposure mask that also serves as a pattern for the display electrode and a step of sequentially depositing and forming a first insulating film, a semiconductor film, and a second insulating film on the gate electrode formation surface side on the insulating substrate. And a step of patterning the outer shape of the second insulating film and the semiconductor film, respectively, using an exposure mask that also serves as the pattern of the second insulating film and the semiconductor film, and the display electrode of the first insulating film. Patterning these insulating films using an exposure mask that also serves as a pattern in which at least a part of the insulating film is exposed and a pattern of a source or drain contact opening of the second insulating film, A step of etching away the conductive film of the display electrode exposed from the first insulating film; a semiconductor film doped with impurities so that the surface of the insulating substrate includes the opening and the display electrode; By an exposure mask having a step of sequentially depositing and forming a metal film, a pattern for a source or drain electrode arranged in the opening, and a pattern in which one of the electrodes is extended to the display electrode. And a step of patterning the metal film and the semiconductor film doped with the impurities.
（ホ） 作用 本発明のTFTの製造方法によれば、半導体膜を保護す
る為の第２の絶縁膜は、半導体膜のパターンニング用露
光マスクとゲート絶縁膜になる第１の絶縁膜のパターン
ニング用露光のマスクとの２枚のマスクを用いてパター
ンニングできるので、第２の絶縁膜専用のマスクを個別
に用意しておく必要がない。(E) Function According to the manufacturing method of the TFT of the present invention, the second insulating film for protecting the semiconductor film is the exposure mask for patterning the semiconductor film and the pattern of the first insulating film to be the gate insulating film. Since patterning can be performed by using two masks, that is, a mask for exposure for polishing, it is not necessary to separately prepare a mask dedicated to the second insulating film.
（ヘ） 実施例 本発明のTFTの製造方法を第１図（イ）〜（リ）の製
造工程図に基づき以下に説明する。(F) Example A method of manufacturing a TFT according to the present invention will be described below with reference to the manufacturing process diagrams of FIGS.
同図（イ）に示す如く、ガラス、石英などの透明基板
（Ｂ）上に透明導電膜（11）、不透明導電膜（12）を連
続して形成する。この時の透明導電膜（11）材料として
はITO、SnO2があり、不透明導電膜（12）材料としてはA
u、Cr、Al、Ｗ、Mo、Ta、Ti及びそれ等のシリサイドが
用いられる。As shown in FIG. 9A, a transparent conductive film (11) and an opaque conductive film (12) are continuously formed on a transparent substrate (B) such as glass or quartz. At this time, ITO and SnO 2 are used as the transparent conductive film (11) material, and A is used as the opaque conductive film (12) material.
u, Cr, Al, W, Mo, Ta, Ti and silicides thereof are used.
次にこの２層膜（11）（12）に対してレジスト（R1）
を塗布し第１の露光マスクを用いたパターンニング処理
を行なって、TFTのゲート電極（Ｇ）と表示電極（Ｅ）
とを形成する〔同図（ロ）〕。Next, resist (R 1 ) against the two-layer film (11) (12)
Is applied and patterning processing is performed using the first exposure mask to form a TFT gate electrode (G) and a display electrode (E).
Are formed [(B) in the figure].
その後CVD法により窒化シリコン（SiN）からなる第１
の絶縁膜（21）、及びアモルファスシリコンからなる半
導体膜（22）、さらに第１の絶縁膜（21）と同じくSiN
からなる第２の絶縁膜（23）を連続的に堆積する〔同図
（ハ）〕。After that, the first layer made of silicon nitride (SiN) by the CVD method
Insulating film (21), semiconductor film (22) made of amorphous silicon, and SiN like the first insulating film (21)
A second insulating film (23) consisting of is deposited continuously [FIG.
次にこれ等３層膜（21）（22）（23）上にレジスト
（R2）を塗布し、第２の露光マスクを用いたパターニン
グ処理を最上の第２の絶縁膜（23）、及び半導体膜（2
2）に対して順次行ないTFTの半導体膜（Ａ）と、この半
導体膜（Ａ）の為の保護膜（Ｐ）とを得る。Next, a resist (R 2 ) is applied on the three-layer film (21) (22) (23), and a patterning process using a second exposure mask is performed, and the uppermost second insulating film (23) and Semiconductor film (2
The semiconductor film (A) of the TFT and the protective film (P) for this semiconductor film (A) are obtained by sequentially performing the step 2).
尚、第１の絶縁膜（23）は半導体膜（Ａ）とゲート電
極（Ｇ）間でゲート絶縁膜（Ｉ）を形成している〔同図
（ニ）〕。The first insulating film (23) forms a gate insulating film (I) between the semiconductor film (A) and the gate electrode (G) [FIG.
その後、さらに上記第２の絶縁膜（23）からなる保護
膜（Ｐ）とその他の位置で露出している上記第１の絶縁
膜（21）からなるゲート絶縁膜（Ｉ）上にレジスト
（R3）を塗布し、第３の露光マスクを用いたパターニン
グ処理を行なう。これに依って、表示電極（Ｅ）上のゲ
ート絶縁膜（Ｉ）を除去すると共に、保護膜（Ｐ）に半
導体膜（Ａ）へのコンタクトホール（Ｃ）（Ｃ）を形成
する〔同図（ホ）〕。この場合光透過形の液晶表示を行
なう為に、透明な表示電極（Ｅ）を得る目的で露出した
上層の不透明導電膜（12）をエッチング除去して透明導
電膜（11）のみからなる表示電極（Ｅ）を得る〔同図
（ヘ）〕。After that, a resist (R) is further formed on the gate insulating film (I) made of the protective film (P) made of the second insulating film (23) and the first insulating film (21) exposed at other positions. 3 ) is applied, and a patterning process using a third exposure mask is performed. As a result, the gate insulating film (I) on the display electrode (E) is removed, and contact holes (C) and (C) to the semiconductor film (A) are formed in the protective film (P) [FIG. (E)]. In this case, in order to perform a light-transmissive liquid crystal display, the upper opaque conductive film (12) exposed for the purpose of obtaining a transparent display electrode (E) is removed by etching to form a display electrode composed of only the transparent conductive film (11). (E) is obtained [FIG.
次に不純物半導体膜（31）、アルミニウム等の金属膜
（32）を連続的に堆積する〔同図（ト）〕。この場合の
不純物半導体膜（31）は例えば燐ドープしたアモルファ
スシリコン膜からなり、半導体と金属とのオーミックコ
ンタクトを得る目的で設けていられている。Next, the impurity semiconductor film (31) and the metal film (32) of aluminum or the like are successively deposited [FIG. In this case, the impurity semiconductor film (31) is made of, for example, a phosphorus-doped amorphous silicon film, and is provided for the purpose of obtaining ohmic contact between the semiconductor and the metal.
さらに、これ等両層（31）（32）上にレジスト（R4）
を塗布し、さらに第４の露光マスクを用いて、ソース電
極（Ｓ）、及び、ドレイン電極（Ｄ）を得る〔同図
（チ）〕。Furthermore, a resist (R 4 ) is formed on both layers (31) (32).
Is applied, and a source electrode (S) and a drain electrode (D) are obtained by using a fourth exposure mask [FIG.
以上のように４枚のマスク工程によって、同図（リ）
に示す如く表示電極（Ｅ）がソース（Ｓ）に結合したTF
Tが製造できる。As shown above, by the mask process of four sheets,
TF in which the display electrode (E) is coupled to the source (S) as shown in
T can be manufactured.
上述の実施例工程では、第１図（ヘ）の工程で表示電
極（Ｅ）の透明化の為のエッチング処理を行なっている
が、例えば第２図（ヘ′）乃至（リ′）に示すようにソ
ース電極（Ｓ）並びにドレイン電極（Ｄ）のパターンニ
ング〔同図（ト′）〕の後に表示電極（Ｅ）の上層の不
透明導電膜（12）をエッチング除去〔同図（チ′）〕し
てもよい。In the process of the above-described embodiment, the etching process for making the display electrode (E) transparent is performed in the process of FIG. 1 (f), but it is shown in, for example, FIG. After the patterning of the source electrode (S) and the drain electrode (D) [FIG. (G '), the opaque conductive film (12) above the display electrode (E) is removed by etching [d. ] You may.
（ト） 発明の効果 本発明のTFTの製造方法によれば、半導体膜を保護す
る為の第２の絶縁膜は、半導体膜のパターンニング用露
光マスクとゲート絶縁膜になる第１の絶縁膜のパターン
ニング用露光マスクとの２枚のマスクを保護膜用のマス
クとして兼用してパターンニングできるので、第２の絶
縁膜専用のマスクを個別に用意しておく必要がなく、し
かもマスク工程数の削減ができ、これによって、製造歩
留りの大巾な向上が望める。(G) Effect of the Invention According to the manufacturing method of the TFT of the present invention, the second insulating film for protecting the semiconductor film is the first insulating film which becomes the exposure mask for patterning the semiconductor film and the gate insulating film. Since the patterning can be performed by using the two masks as the patterning exposure mask also as the mask for the protective film, it is not necessary to separately prepare a mask dedicated to the second insulating film, and the number of mask steps is increased. It is possible to reduce the production cost, which can greatly improve the production yield.
第１図（イ）乃至（リ）は本発明の薄膜トランジスタの
製造方法の一実施例を示す工程順断面図、第２図（ヘ）
乃至（リ）は本発明方法の他の実施例を示す工程断面
図、第３図は従来の薄膜トランジスタの断面図である。 （11）……透明導電膜、（12）……不透明導電膜、（2
1）……第１の絶縁膜、（22）……半導体膜、（23）…
…第２の絶縁膜。1 (a) to (i) are sectional views in order of steps showing one embodiment of the method of manufacturing a thin film transistor according to the present invention, and FIG. 2 (f).
6 to 9 are process sectional views showing another embodiment of the method of the present invention, and FIG. 3 is a sectional view of a conventional thin film transistor. (11) …… Transparent conductive film, (12) …… Opaque conductive film, (2
1) ... first insulating film, (22) ... semiconductor film, (23) ...
… Second insulating film.
Claims (1)
堆積形成する工程と、 前記透明導電膜と導電膜を、ゲート電極と表示電極との
パターンを兼ねる露光マスクを用いて、夫々パターニン
グする工程と、 絶縁基板上のゲート電極形成面側に第１の絶縁膜、半導
体膜、第２の絶縁膜を順次堆積形成する工程と、 前記第２の絶縁膜と前記半導体膜のパターンを兼ねる露
光マスクを用いて、第２の絶縁膜の外形と半導体膜を夫
々パターニングする工程と、 前記第１の絶縁膜の、上記の表示電極の少なくとも一部
露出するパターンと、第２の絶縁膜のソースあるいはド
レインのコンタクト用開口のパターンを兼ねる露光マス
クを用いて、これら絶縁膜をパターニングする工程と、 前記第１の絶縁膜から露出した前記表示電極の前記導電
膜を、エッチング除去する工程と、 上記絶縁基板の表面に、上記開口と上記表示電極を含む
ように、不純物がドーピングされた半導体膜、及び金属
膜を順次堆積形成する工程と、 前記開口に配置されるソースあるいはドレイン電極のた
めのパターン及び、上記電極のうちいずれか一方を前記
表示電極にまで延出せしめたパターンを備えた露光マス
クによって、上記金属膜及び上記不純物がドーピングさ
れた半導体膜をパターニングする工程と、 からなる薄膜トランジスタの製造方法。1. A step of sequentially depositing and forming a transparent conductive film and a conductive film on an insulating substrate, and using the exposure mask which also serves as a pattern of the gate electrode and the display electrode, respectively. A step of patterning, a step of sequentially depositing and forming a first insulating film, a semiconductor film, and a second insulating film on a gate electrode formation surface side on an insulating substrate, and a pattern of the second insulating film and the semiconductor film. Patterning the outer shape of the second insulating film and the semiconductor film, respectively, using a double exposure mask; a pattern of the first insulating film exposing at least a portion of the display electrode; and a second insulating film Patterning these insulating films using an exposure mask that also serves as a pattern of source or drain contact openings, and the conductive film of the display electrode exposed from the first insulating film And a step of sequentially depositing and forming an impurity-doped semiconductor film and a metal film on the surface of the insulating substrate so as to include the opening and the display electrode, and a source arranged in the opening. Alternatively, a step of patterning the metal film and the semiconductor film doped with the impurity with an exposure mask having a pattern for a drain electrode and a pattern in which one of the electrodes is extended to the display electrode. A method of manufacturing a thin film transistor, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29092387A JP2527579B2 (en) | 1987-11-18 | 1987-11-18 | Method for manufacturing thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29092387A JP2527579B2 (en) | 1987-11-18 | 1987-11-18 | Method for manufacturing thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01132165A JPH01132165A (en) | 1989-05-24 |
| JP2527579B2 true JP2527579B2 (en) | 1996-08-28 |
Family
ID=17762255
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29092387A Expired - Lifetime JP2527579B2 (en) | 1987-11-18 | 1987-11-18 | Method for manufacturing thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2527579B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3424618B2 (en) * | 1999-09-14 | 2003-07-07 | 日本電気株式会社 | Method of manufacturing thin film transistor array substrate |
-
1987
- 1987-11-18 JP JP29092387A patent/JP2527579B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01132165A (en) | 1989-05-24 |
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