JPH01202823A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01202823A JPH01202823A JP63027932A JP2793288A JPH01202823A JP H01202823 A JPH01202823 A JP H01202823A JP 63027932 A JP63027932 A JP 63027932A JP 2793288 A JP2793288 A JP 2793288A JP H01202823 A JPH01202823 A JP H01202823A
- Authority
- JP
- Japan
- Prior art keywords
- gas
- hydrogen
- transparent conductive
- conductive film
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 239000010408 film Substances 0.000 claims abstract description 34
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 claims abstract description 18
- 239000007789 gas Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 17
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 12
- 239000001257 hydrogen Substances 0.000 claims abstract description 12
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 11
- 238000000059 patterning Methods 0.000 claims abstract description 8
- 229910052736 halogen Inorganic materials 0.000 claims abstract description 7
- 150000002367 halogens Chemical class 0.000 claims abstract description 7
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 claims abstract description 6
- 239000010409 thin film Substances 0.000 claims abstract description 5
- 150000002431 hydrogen Chemical class 0.000 claims abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 6
- -1 hydrogen Chemical class 0.000 claims 1
- 239000011229 interlayer Substances 0.000 abstract description 5
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 abstract description 3
- 239000000203 mixture Substances 0.000 abstract description 3
- 229910017604 nitric acid Inorganic materials 0.000 abstract description 3
- XTEGARKTQYYJKE-UHFFFAOYSA-N chloric acid Chemical compound OCl(=O)=O XTEGARKTQYYJKE-UHFFFAOYSA-N 0.000 abstract 1
- 229940005991 chloric acid Drugs 0.000 abstract 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000003384 imaging method Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は多結晶シリ゛コンもしくは非晶質シリコンより
成る薄膜トランジスタ（以下Ｔ？Ｔと示す）及び透明導
電膜（例えば工ＴＯ）による配線パターンを同一基板上
に有する半導体装置の製造方法に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a thin film transistor (hereinafter referred to as T?T) made of polycrystalline silicon or amorphous silicon and a wiring pattern made of a transparent conductive film (for example, TO). The present invention relates to a method of manufacturing a semiconductor device having on the same substrate.
従来の、多結晶もしくは非晶質シリコン’Ｉ’ｌＦＴを
用いた半導体装置は、配線に透明導電膜を有する場合、
水素ガスもしくは水素を含有するガスもしくはハロゲン
元素を含有するガスのプラズマ雰囲気中に基板を浸す工
程を行う場合は、透明導電膜の形成以前に該工程を行っ
ていた。なぜなら、透明導電膜形成以降に該工程を行え
ば、透明導電膜（例えば′ｘＴＯ）が還元されたり、エ
ツチングされたりする為である。When a conventional semiconductor device using polycrystalline or amorphous silicon 'I'lFT has a transparent conductive film in the wiring,
When performing a step of immersing the substrate in a plasma atmosphere of hydrogen gas, a gas containing hydrogen, or a gas containing a halogen element, this step is performed before forming the transparent conductive film. This is because if this step is performed after the transparent conductive film is formed, the transparent conductive film (for example, 'xTO) will be reduced or etched.
前記プラズマ状態のガス雰囲気中に基板を浸す理由は、
多結晶もしくは非晶質シリコン中の未結合手に水素もし
くはハロゲン元素を結合させる為であり、この様にすれ
Ｉｄ Ｔ ？ Ｔの特性が向上（オン電流増大、オフ電
流減少）する事は周知の事実である。The reason for immersing the substrate in the gas atmosphere in the plasma state is as follows.
This is to bond hydrogen or halogen elements to dangling bonds in polycrystalline or amorphous silicon, and in this way Id T ? It is a well-known fact that the characteristics of T improve (increase on-state current, decrease in off-state current).
上記従来例においては、プラズマ状態のガス雰囲気中に
基板を浸す工程と、透明導電膜をパターニングする工程
は別々であった。透明導電膜が工ＴＯの場合、バターニ
ングにはウェットエツチング（塩酸と硝酸の混合液等を
用いる）とドライエツチング（アルコールガス、もしく
は四塩化炭素等を用いる）の方法があるが、前述のガス
プラズマ工程と合わせて考えれば２度手間であった。In the conventional example described above, the step of immersing the substrate in a gas atmosphere in a plasma state and the step of patterning the transparent conductive film were separate. When the transparent conductive film is processed TO, there are two methods of buttering: wet etching (using a mixture of hydrochloric acid and nitric acid, etc.) and dry etching (using alcohol gas or carbon tetrachloride, etc.). Considering this together with the plasma process, it was twice as much work.
本発明は以上の問題点を解決するもので、その目的とす
るところは、高性能なＴＩＦＴを用いた半導体装置の、
工程数を軽減することにある。The present invention is intended to solve the above problems, and its purpose is to provide a semiconductor device using high performance TIFT.
The goal is to reduce the number of steps.
以上の問題点を解決するため、本発明はｄ間溝電膜のバ
ターニングの際、プラズマ状態の水素ガスもしくはメタ
ノールの如き水素を含有するガス、もしくは塩素ガスも
しくは四塩化炭素の如き／）ロゲン元素を含むガス雰囲
気中に基板を浸す工程を有することを特徴とする。In order to solve the above problems, the present invention uses hydrogen gas in a plasma state, a hydrogen-containing gas such as methanol, or a chlorine gas such as chlorine gas or carbon tetrachloride, when buttering a d-groove electrical film. The method is characterized by a step of immersing the substrate in a gas atmosphere containing elements.
第１図に本発明の製造方法を用いた半導体装置の断面図
を示す。同図（α）は眉間絶縁膜形成時、同図（ｂ）は
透明導電膜上のレジスト形成時、同図（Ｃ）は透明導電
膜のバターニング終了時の半導体装置の断面図である。FIG. 1 shows a cross-sectional view of a semiconductor device using the manufacturing method of the present invention. FIG. 5(α) is a cross-sectional view of the semiconductor device when the glabella insulating film is formed, FIG. 2(b) is when the resist is formed on the transparent conductive film, and FIG.
同図（α）において、１０１は絶縁基板、１０２はＴＰ
Ｔのソース・ドレイン電極部、１０３はＴＰＴのチャネ
ル部℃あり、１ｄ２及び１０３は多結晶もしくは非晶質
シリコンで形成される。１０４は酸化シリコン等による
ゲート絶縁膜、１０５は多結晶シリコン等により形成さ
れるゲート電極、１０６は酸化シリコン等による層間絶
縁膜である。ここまでの製造方法の一例を示すと、絶縁
基板１０１上に多結晶（非晶質）シリコン薄膜を形成し
、バターニングし、熱酸化法でゲート絶縁＠１０４を形
成する。In the same figure (α), 101 is an insulating substrate, 102 is a TP
A source/drain electrode portion 103 of the TPT is a channel portion of the TPT, and 1d2 and 103 are formed of polycrystalline or amorphous silicon. 104 is a gate insulating film made of silicon oxide or the like, 105 is a gate electrode made of polycrystalline silicon or the like, and 106 is an interlayer insulating film made of silicon oxide or the like. To show an example of the manufacturing method up to this point, a polycrystalline (amorphous) silicon thin film is formed on an insulating substrate 101, buttered, and a gate insulator @104 is formed by a thermal oxidation method.
そしてゲート電極１０５を形成した後、イオン打込法で
ソース・ドレイン＊極１０２を形成し、ＣＶＤ法で眉間
絶縁膜１０６を形成する。第１図（ｂ）において１０７
は透明導電膜（例えば工ＴＯ）、１０８はレジストであ
る。層間絶縁＠１０６上にスパッタ法等で透明溝を膜１
０７を形成し、パターニング用にレジスト１０８を形成
する。そして、本発明に於いては、ここでプラズマ状態
の水素ガスもしくはメタノール等の水素を含有するガス
、もしくは塩素ガスもしくは四塩化炭素等のハロゲン元
素を含有するガスの雰囲気中に第１図（ｂ）の状態の半
導体装置を浸す。例えばプラズマ状態の水素ガス中に基
板を浸した場合は、レジスト１０８に覆われていない部
分の透明導電膜Ｓ工Ｔｏ）１０７は還元され、黒変する
。これと同時に水素は１０２及び１０４で構成される多
結晶もしくは非晶質シリコン内部に浸透する。そして黒
変した工ＴＯ１０７を、塩酸と硝酸の混合液で取シ除き
、レジスト１０８を剥離すれば第１図（Ｃ）の如き構造
が形成され、多結晶もしく昏ま非晶質シリコン中に充分
水素が添加されｔこＴＩＦＴが実現される。水素プラズ
マ状態の条件によって＆家しジスト１０８が損傷し、透
明導電膜１０７が残らない状態となるが、レジスト１０
８の代わりに金属（例えばクロムの如きもの）を用いれ
ば、完全に第１図（Ｃ）の如き構造が形成される。プラ
ズマ状態のガスにメタノールを用いた場合は工Ｔ。After forming the gate electrode 105, the source/drain electrode 102 is formed by ion implantation, and the glabellar insulating film 106 is formed by CVD. 107 in Figure 1(b)
108 is a transparent conductive film (eg, TO), and 108 is a resist. Transparent grooves are formed on the interlayer insulation @106 by sputtering method etc. Film 1
07 is formed, and a resist 108 for patterning is formed. In the present invention, in an atmosphere of hydrogen gas in a plasma state, a hydrogen-containing gas such as methanol, or a gas containing a halogen element such as chlorine gas or carbon tetrachloride, as shown in FIG. ) immerse the semiconductor device in the condition. For example, when the substrate is immersed in hydrogen gas in a plasma state, the portion of the transparent conductive film 107 not covered with the resist 108 is reduced and turns black. At the same time, hydrogen penetrates into the polycrystalline or amorphous silicon formed by 102 and 104. Then, the blackened TO 107 is removed with a mixture of hydrochloric acid and nitric acid, and the resist 108 is peeled off to form a structure as shown in Figure 1 (C). Sufficient hydrogen is added to realize TIFT. Depending on the conditions of the hydrogen plasma state, the resist 108 is damaged and no transparent conductive film 107 remains.
If a metal (for example, chromium) is used in place of 8, the structure as shown in FIG. 1(C) is completely formed. If methanol is used as the gas in the plasma state, it is T.
がエツチングされる為、その後レジスト１０８を剥離す
るだけでＴＩＦＴに十分水素が添加された、第１図（Ｃ
）の如き構造が実現される。プラズマ状態のガスにハロ
ゲン元素を含む物質を用いた場合も同様で、多結晶もし
くは非晶質シリコンに充分ハロゲン元素が添加されたＴ
ＰＴをもつ、第１図ＣＣ）の構造が実現される。As shown in Figure 1 (C
) is realized. The same is true when a substance containing a halogen element is used as the gas in the plasma state.
The structure of FIG. 1 CC) with PT is realized.
第１図の構造から光電変換素子を形成した、固体撮像装
置の断面図を第２図に示す。同図において、第１図と同
一の記号は第１図と同一のものを表わす。２０１は非晶
質シリコン等の光電変換材料、２０２はアルミニウム等
の配線材料である。FIG. 2 shows a cross-sectional view of a solid-state imaging device in which a photoelectric conversion element is formed from the structure shown in FIG. In this figure, the same symbols as in FIG. 1 represent the same things as in FIG. 1. 201 is a photoelectric conversion material such as amorphous silicon, and 202 is a wiring material such as aluminum.
第１ｍ＜ｃ＞の構造から非晶質シリコンを堆積及びパタ
ーニングし、眉間絶縁膜１０６にスルーホールを開け、
アルミニウムを蒸着及びパターニングすれば、第２図の
如き構造の、絶縁基板側から光を入射する型の固体撮像
装置が実現される。Depositing and patterning amorphous silicon from the structure of the first m<c>, opening a through hole in the glabella insulating film 106,
By vapor-depositing and patterning aluminum, a solid-state imaging device of the type shown in FIG. 2, in which light enters from the insulating substrate side, can be realized.
第３図に、本発明の製造方法を用いた液晶表示装置用基
板の断面図を示す。同図において第１図と同一の記号は
第１図と同一のものを表わす。まずＴＮＴを形成し、眉
間絶縁膜１０６にスルーホールを形成した後、透明導電
膜を形成する。そして第１図における実施例と同様に、
パターニング時のレジスト形成後、プラズマガス雰囲気
中に浸し、レジスト剥離すれば第３図の如き構造が形成
出来る。FIG. 3 shows a cross-sectional view of a substrate for a liquid crystal display device using the manufacturing method of the present invention. In this figure, the same symbols as in FIG. 1 represent the same things as in FIG. 1. First, TNT is formed, a through hole is formed in the glabella insulating film 106, and then a transparent conductive film is formed. And similar to the embodiment in FIG.
After forming a resist during patterning, the structure as shown in FIG. 3 can be formed by immersing it in a plasma gas atmosphere and peeling off the resist.
また本発明は、第１〜５図における絶縁基板１０１を、
絶縁体薄膜を介して素子のある半導体装置に置き換える
ことにより、３次元ＩＣにも適用出来る。Further, the present invention provides that the insulating substrate 101 in FIGS. 1 to 5 is
It can also be applied to a three-dimensional IC by replacing it with a semiconductor device with elements through an insulating thin film.
この様に、本発明は多結晶もしくは非晶質シリコンより
成るＴＮＴと、透明導電膜による配線を康ね備えたあら
ゆる半導体装置に適用出来る。In this way, the present invention can be applied to any semiconductor device equipped with TNT made of polycrystalline or amorphous silicon and wiring made of a transparent conductive film.
以上述べた如く本発明を用いることにより、高性能なＴ
ＩＦＴを用いた半導体装置の製造工程数が軽減される。As described above, by using the present invention, high-performance T
The number of manufacturing steps for a semiconductor device using IFT is reduced.
第１図（α）〜ＣＣ）は本発明の製造方法を用いた半導
体装置の断面図。同図（α）（Ａ）（Ｃ）はそれぞれ層
間絶縁膜形成時、透明導電膜上のレジスト形成時、透明
導電膜のパターニング終了時の断面図。
第２図は、第１図の構造から光電変換素子を形成した、
固体撮像装置の断面図。
第３図は本発明の製造方法を用いた液晶表示装置用基板
の断面図。
１０１・・・・・・絶縁基板
１０２・・・・・・ＴＩＦＴのソース・ドレイン電極部
１０３・・・・・・ＴＰＴのチャネル部１０４・・・・
・・ゲート絶縁膜
１０５・・・・・・ＴＩＦＴのゲート電極１０６・・・
・・・層間絶縁膜
１０７・・・・・・透明導電膜
１０８・・・・・・レジスト
／＃＃ ・−・ レジ゛スト
第１図FIGS. 1(α) to CC) are cross-sectional views of a semiconductor device using the manufacturing method of the present invention. (α), (A), and (C) are cross-sectional views at the time of forming an interlayer insulating film, the time of forming a resist on a transparent conductive film, and the end of patterning of a transparent conductive film, respectively. FIG. 2 shows a photoelectric conversion element formed from the structure shown in FIG.
A cross-sectional view of a solid-state imaging device. FIG. 3 is a sectional view of a substrate for a liquid crystal display device using the manufacturing method of the present invention. 101... Insulating substrate 102... TIFT source/drain electrode part 103... TPT channel part 104...
...Gate insulating film 105...Gate electrode 106 of TIFT...
...Interlayer insulating film 107...Transparent conductive film 108...Resist/## ---Resist Fig. 1
Claims (1)
晶質シリコンより成る薄膜トランジスタ及び透明、導電
膜による配線パターンを有する半導体装置の製造方法に
おいて、前記透明導電膜のパターニングの際プラズマ状
態の、水素ガスもしくはメタノールの如き水素を含有す
るガス、もしくは塩素ガスもしくは四塩化炭素の如きハ
ロゲン元素を含有するガス雰囲気中に基板を浸す工程を
有することを特徴とする、半導体装置の製造方法。In a method for manufacturing a semiconductor device having at least a thin film transistor made of polycrystalline silicon or amorphous silicon and a wiring pattern made of a transparent conductive film on the same substrate, hydrogen gas or methanol in a plasma state is used during patterning of the transparent conductive film. 1. A method for manufacturing a semiconductor device, comprising the step of immersing a substrate in a gas atmosphere containing hydrogen, such as hydrogen, or a gas atmosphere containing a halogen element, such as chlorine gas or carbon tetrachloride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2793288A JP2646614B2 (en) | 1988-02-09 | 1988-02-09 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2793288A JP2646614B2 (en) | 1988-02-09 | 1988-02-09 | Method for manufacturing semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1290897A Division JP2692678B2 (en) | 1997-01-27 | 1997-01-27 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01202823A true JPH01202823A (en) | 1989-08-15 |
| JP2646614B2 JP2646614B2 (en) | 1997-08-27 |
Family
ID=12234667
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2793288A Expired - Lifetime JP2646614B2 (en) | 1988-02-09 | 1988-02-09 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2646614B2 (en) |
-
1988
- 1988-02-09 JP JP2793288A patent/JP2646614B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2646614B2 (en) | 1997-08-27 |
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