JPS62221159A - Formation of thin film transistor matrix - Google Patents

Formation of thin film transistor matrix

Info

Publication number
JPS62221159A
JPS62221159A JP6532286A JP6532286A JPS62221159A JP S62221159 A JPS62221159 A JP S62221159A JP 6532286 A JP6532286 A JP 6532286A JP 6532286 A JP6532286 A JP 6532286A JP S62221159 A JPS62221159 A JP S62221159A
Authority
JP
Japan
Prior art keywords
thin film
conductive film
gate
resist
film transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6532286A
Other languages
Japanese (ja)
Inventor
▲梁▼井 健一
Kenichi Yanai
Michiya Oura
大浦 道也
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6532286A priority Critical patent/JPS62221159A/en
Publication of JPS62221159A publication Critical patent/JPS62221159A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78636Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with supplementary region or layer for improving the flatness of the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Abstract

PURPOSE:To reduce the short-circuit defects of a transistor and to obtain a highly reliable thin film transistor matrix by a method wherein, before formation of a gate insulating film and an operating semiconductor layer, the substrate provided with a gate and a gate bus line is flattened. CONSTITUTION:A pattern corresponding to the pattern, which will be turned to a gate electrode, is formed on a conductive film 2 using a resist 3, and besides, a resist mask pattern 5 corresponding to a matrix driving bus line is formed. The conductive film 2, excluding the part where the resist 3 is coated, is directly exposed to an electrolyte, and an Al2O3 oxide film 8 is grown. After a selective oxidation has been performed, the resist 3 mask pattern on a flat glass substrate 1 is exfoliated, silicon nitride is formed as an insulating film 6 and hydrogenated, silicon nitride is formed as an insulating film 6 and hydrogenated amorphous silicon is formed as an operating semiconductor layer 7 (active layer) on a gate electrode 4 successively by performing a plasma CVD (chemical vapor deposition) method, and the source electrode 9 and the drain electrode 10, consisting of N-type hydrogenated amorphous silicon, titanium Ti and aluminum A1, are formed.

Description

【発明の詳細な説明】 〔概要〕 本発明は、平面型の、所謂能動マトリックスパネルと呼
ばれるパネル基板に形成される薄膜トランジスタに係り
、その意図するところはゲート絶縁膜/動作半導体層の
形成前、ゲートとゲートバスラインが作製された基板を
平坦化することによりトランジスタの短絡欠陥を低減し
、信頼性の高い薄膜トランジスタマトリックスを提供す
ることである。
[Detailed Description of the Invention] [Summary] The present invention relates to a thin film transistor formed on a planar panel substrate, so-called an active matrix panel. The purpose of the present invention is to reduce short-circuit defects in transistors by planarizing a substrate on which gates and gate bus lines are formed, thereby providing a highly reliable thin film transistor matrix.

〔産業上の利用分野〕[Industrial application field]

本発明は平面型ディスプレイパネルに一体的に組み込む
薄膜トランジスタマトリックスの形成方法に関する。
The present invention relates to a method of forming a thin film transistor matrix that is integrally incorporated into a flat display panel.

例えば液晶ディスプレイパネルなど大面積の表示デバイ
スは、一般的にm x nの格子状配列の画素セルを形
成し1画素セルの駆動を、たがいに直交するm本および
1本のパスラインを設けて行うマトリックス駆動方式が
採られている。
For example, large-area display devices such as liquid crystal display panels generally form pixel cells in an m x n lattice arrangement, and each pixel cell is driven by providing m and one pass lines orthogonal to each other. A matrix drive method is used.

しかして、マトリック駆動されるそれぞれの画素セルは
該セル電極と直結して例えば水素化アモルファスシリコ
ンからなる半導体膜を活性層とする薄膜トランジスタを
設けることが一般的におこなわれている。
Generally, each pixel cell driven in a matrix manner is provided with a thin film transistor directly connected to the cell electrode, the active layer of which is a semiconductor film made of, for example, hydrogenated amorphous silicon.

本発明は、前記薄膜トランジスタの形成方法に係り、特
にトランジスタのゲート絶縁膜部分の段差を無くして耐
圧性能を向上することにより、安定なディスプレイパネ
ルを形成することである。
The present invention relates to a method of forming the thin film transistor, and in particular, to forming a stable display panel by eliminating steps in the gate insulating film portion of the transistor and improving voltage resistance performance.

〔従来の技術〕[Conventional technology]

第3図は、逆スタガード構成になる薄膜トランジスタの
構造と形成プロセスを図示するトランジスタ要部の断面
図である。
FIG. 3 is a cross-sectional view of a main part of a thin film transistor having an inverted staggered configuration, illustrating the structure and formation process of the thin film transistor.

同図(a)はガラス等の絶縁基板20の表面に導電膜を
形成し、該導電膜を通常のエツチング法あるいはリフト
オフ法を用いてゲート電極21が形成された図である。
FIG. 2A shows a diagram in which a conductive film is formed on the surface of an insulating substrate 20 such as glass, and a gate electrode 21 is formed on the conductive film using a normal etching method or lift-off method.

同図(blはプラズマガス空間内の化学的気相成長法(
CVD法)もしくは熱CVD法によって前記ゲート電極
21上に順次、ゲート絶縁膜22と例えば水素化アモル
ファスシリコンの半導体活性層23が連続的に形成され
た図である。
The same figure (bl is chemical vapor deposition method in plasma gas space (
2 is a diagram in which a gate insulating film 22 and a semiconductor active layer 23 of, for example, hydrogenated amorphous silicon are successively formed on the gate electrode 21 by a CVD method or a thermal CVD method.

また同図(C1は半導体活性層23の上にトランジスタ
のソース電極24及びドレイン電極25のそれぞれがパ
ターン形成された図である。
The figure (C1 is a diagram in which a source electrode 24 and a drain electrode 25 of a transistor are each patterned on the semiconductor active layer 23).

しかしながら、前記の如き方法で形成された薄膜トラン
ジスタのゲート絶縁膜22は、下地のゲート電極21の
厚さに該当する電極端部26で段差となるため、該段差
部の絶縁膜27は膜質の電気的耐圧が低下するため問題
がある。
However, since the gate insulating film 22 of the thin film transistor formed by the method described above has a step at the electrode end 26 corresponding to the thickness of the underlying gate electrode 21, the insulating film 27 at the step has a film quality of electrical This poses a problem because the physical withstand voltage decreases.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

薄膜トランジスタのゲート絶縁膜22における前記段差
部27は平坦部に比べて膜内ピンホール等が生じやすく
、これにともない短絡欠陥や、電気的耐圧が低下する原
因となる。特に大面積のディスプレイパネルでは2マト
リツクス配置の薄膜トランジスタが前記耐圧の低下や短
絡欠陥があるとパネル形成の歩留りが顕著に低下するこ
ととなる。
The stepped portion 27 of the gate insulating film 22 of the thin film transistor is more likely to have pinholes in the film than a flat portion, which causes short circuit defects and a reduction in electrical breakdown voltage. Particularly in large-area display panels, if thin film transistors arranged in a two-matrix arrangement have the aforementioned drop in breakdown voltage or short-circuit defects, the yield of panel formation will drop significantly.

〔問題点を解決するための手段〕[Means for solving problems]

第1図と第2図は前記の問題点を解決する本発明の薄膜
トランジスタの形成方法実施例とする断面図である。
FIGS. 1 and 2 are cross-sectional views illustrating an embodiment of the method for forming a thin film transistor of the present invention, which solves the above-mentioned problems.

平坦な基板1全面に導電膜2を形成した後、前記導電膜
2上のレジストマスク3により導電膜2を選択酸化して
、ゲート電極4.及び該電極4と同レベルに設ける一方
のマトリックス駆動線とするパスライン5とを同時形成
する工程と、続いてゲート絶縁膜6及び半導体活性層7
を順次形成する工程を含んでマトリックス配列の薄膜ト
ランジスタを形成することとしたものである。
After forming a conductive film 2 on the entire surface of a flat substrate 1, the conductive film 2 is selectively oxidized using a resist mask 3 on the conductive film 2 to form a gate electrode 4. and a step of simultaneously forming a pass line 5 as one matrix drive line provided at the same level as the electrode 4, followed by a step of forming a gate insulating film 6 and a semiconductor active layer 7.
In this method, a thin film transistor in a matrix arrangement is formed by sequentially forming the following steps.

〔作 用〕[For production]

薄膜トランジスタのゲート絶縁膜形成前に行う前記導電
膜の選択酸化法は、以下実施例に示される陽極酸化法に
してもまた熱酸化法にしても、導電性の膜厚さ維持して
膜質を絶縁性に替えることから基板の平坦性が保持され
た伏態でゲート絶縁膜、及び半導体活性層が積み重ねら
れ、短絡欠陥のない高い薄膜トランジスタマトリックス
が形成されることになる。
The method of selectively oxidizing the conductive film before forming the gate insulating film of the thin film transistor may be an anodic oxidation method as shown in the examples below or a thermal oxidation method, which maintains the conductive film thickness and insulating film quality. Since the gate insulating film and the semiconductor active layer are stacked in a down state while the flatness of the substrate is maintained, a high thin film transistor matrix without short circuit defects is formed.

〔実施例〕〔Example〕

以下、第1図と第2図を参照して本発明トランジスタの
構成と形成方法の実施例を説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the structure and method of forming a transistor of the present invention will be described below with reference to FIGS. 1 and 2.

第1図(a)は、平坦基板例えばガラス基板1にアルミ
ニウムAlの導電膜2を基板全面に例えば蒸着手段によ
り被着した断面図(偽)〜(e)図も断面図)である。
FIG. 1(a) is a cross-sectional view (false) to (e) is also a cross-sectional view of a flat substrate, for example, a glass substrate 1, and a conductive film 2 of aluminum is deposited over the entire surface of the substrate by, for example, vapor deposition means.

同図0)においては先づ、導電膜2上にゲート電極とな
るパターンと対応するパターンをレジスト3により形成
したものである。但し1図示されないが該レジストパタ
ーン形成時、併せてマトリックス駆動パスラインに対す
るレジストマスクパターン5も形成される。かかる基板
は1次いで、蓚酸電解液に浸しカーボン陰極を用いて適
宜電流密度で陽極酸化すれば、レジスト3被着の部分を
除いた導電膜2は直接電解液にさらされA1)O,の酸
化膜が生成される。
In FIG. 0), first, a pattern corresponding to a pattern to be a gate electrode is formed on a conductive film 2 using a resist 3. However, although not shown in the drawings, at the time of forming the resist pattern, a resist mask pattern 5 for the matrix drive pass line is also formed. This substrate is then immersed in an oxalic acid electrolyte and anodized using a carbon cathode at an appropriate current density, so that the conductive film 2 except for the portion where the resist 3 is adhered is directly exposed to the electrolyte, resulting in the oxidation of A1) O, A film is produced.

同図(C1は前記選択酸化後、基板上のレジスト3マス
クパターンを剥離した図である。図中、8は導電膜2の
At20.電解酸化部分である。
In the same figure (C1 is a diagram in which the resist 3 mask pattern on the substrate is peeled off after the selective oxidation. In the figure, 8 is the At20.electrolytically oxidized portion of the conductive film 2.

同図(d+は同図(C1のゲート電極4上に絶縁膜6と
して窒化シリコン、動作半導体層7 (活性層)として
水素化アモルファスシリコン、のそれぞれを順次、プラ
ズマCVD法により連続的に成膜したものである。
In the same figure (d+ is the same figure) silicon nitride as the insulating film 6 and hydrogenated amorphous silicon as the active semiconductor layer 7 (active layer) are sequentially formed on the gate electrode 4 of C1 by plasma CVD method. This is what I did.

更に、同図(e)は、n量水素化アモルファスシリコン
/チタンTi/アルミニウムAIからなるソース電極9
とドレイン電極10とを形成して薄膜トランジスタが完
成した図である。
Furthermore, the same figure (e) shows a source electrode 9 made of n-hydrogenated amorphous silicon/titanium Ti/aluminum AI.
FIG. 3 is a diagram in which a thin film transistor is completed by forming a drain electrode 10 and a drain electrode 10. FIG.

次に前記電解化成による導電膜の選択酸化に替わって導
電膜の熱酸化による本発明の他の実施例を第2図のプロ
セスに従って説明する。
Next, another embodiment of the present invention in which a conductive film is thermally oxidized instead of the selective oxidation of the conductive film by electrolytic chemical formation will be described according to the process shown in FIG.

第1図と相異する点は、(a)図の平坦基板1として石
英基板を用い、該基板1全面に被着する導電膜1)とし
てn型ポリシリコンが使用される。前記石英基板は高温
度の酸化プロセスに耐えうる。
The difference from FIG. 1 is that a quartz substrate is used as the flat substrate 1 in FIG. 1A, and n-type polysilicon is used as the conductive film 1) deposited on the entire surface of the substrate 1. The quartz substrate can withstand high temperature oxidation processes.

またTb)図にn型ポリシリコン導電膜1)に対する選
択酸化のためのマスク12として窒化シリコンを用いる
ことである。
Furthermore, Tb) silicon nitride is used as a mask 12 for selective oxidation of the n-type polysilicon conductive film 1) shown in the figure.

(C)〜(81図に示す基本的プロセスは第1図と略同
じである。即ち、窒化シリコンによるマスク12を剥離
除去した(C1は段差のない平坦な基板面が確保されて
なり、この上にプラズマCVD法による。窒化シリコン
のゲート絶縁膜6と水素化アモルファスシリコンの動作
半導体N7を連続的に形成する。
(C) - (The basic process shown in Figure 81 is almost the same as in Figure 1. That is, the mask 12 made of silicon nitride is peeled off and removed. A gate insulating film 6 of silicon nitride and an active semiconductor N7 of hydrogenated amorphous silicon are successively formed thereon by plasma CVD.

(C)〜(e)図中の13は前記導電膜1)の熱酸化膜
である。
13 in the figures (C) to (e) is a thermally oxidized film of the conductive film 1).

次いで、ソース電極9とドレイン電極10を形成すれば
、短絡欠陥が少なく素子耐圧の高い薄膜トランジスタマ
トリックスが形成されることとなる。
Next, by forming the source electrode 9 and the drain electrode 10, a thin film transistor matrix with few short circuit defects and high device breakdown voltage will be formed.

〔発明の効果〕〔Effect of the invention〕

以上、詳細に説明したゲート絶縁膜の成膜前。 Before forming the gate insulating film described in detail above.

導電膜の選択酸化手段を用いてゲート絶縁膜とパスライ
ンをパターン形成した本発明の薄膜トランジスタマトリ
ックスによれば、短絡欠陥の少ない素子耐圧の高い薄膜
トランジスタアレイが形成されると共にパネル組立の歩
留りが向上するため安価なディスプレイパネルを提供す
ることが出来る。
According to the thin film transistor matrix of the present invention in which a gate insulating film and a pass line are patterned using selective oxidation of a conductive film, a thin film transistor array with fewer short circuit defects and high element withstand voltage can be formed, and the yield of panel assembly can be improved. Therefore, an inexpensive display panel can be provided.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の薄膜トランジスタの形成方法実施例断
面図。 第2図は本発明の薄膜トランジスタの形成方法実施例断
面図。 第3図は従来の薄膜トランジスタの構造と形成プロセス
図である。 図中、lは平坦な基板、  2と1)は導電膜。 3と12はレジストマスク。 4はゲート電極、  5はパスライン。 6はゲート絶縁膜、7は半導体活性層。 8は陽極酸化膜、13は熱酸化膜。 9はソース電極、lOはドレイン電極 である。 代理人 弁理士 井 桁 貞 − ネ」圏日月薄片」トランジスタ刑り文万j直史if列圃
躬 1 口 ! #海J月薄1便Fランン゛スタ形へ方法爽兇例口窮 Z
 図 U (C) 芝釆斗うンジ又9の構丘1椛叛プロ仁ス回第3 口
FIG. 1 is a cross-sectional view of an embodiment of the method for forming a thin film transistor of the present invention. FIG. 2 is a cross-sectional view of an embodiment of the method for forming a thin film transistor of the present invention. FIG. 3 is a diagram showing the structure and formation process of a conventional thin film transistor. In the figure, l is a flat substrate, and 2 and 1) are conductive films. 3 and 12 are resist masks. 4 is a gate electrode, 5 is a pass line. 6 is a gate insulating film, and 7 is a semiconductor active layer. 8 is an anodic oxide film, and 13 is a thermal oxide film. 9 is a source electrode, and lO is a drain electrode. Agent Patent Attorney Sada Igata - Ne ``Block Sun Moon Thin Piece'' Transistor Punishment Bun Manj Naofumi If Line Farm 1 Mouth! #How to get to the F-run star form on the first flight of Kai J Getsuki Z
Figure U (C) Shiba Kamato Uunjimata 9 no Kikaku 1 Banban Proinsu Episode 3

Claims (1)

【特許請求の範囲】 (1)平坦な基板(1)全面に導電膜(2)を形成した
後、前記導電膜(2)上のレジストマスク(3)により
導電膜(2)を選択酸化してゲート電極(4)とゲート
バスライン(5)を同時形成する工程と、続いてゲート
絶縁膜(6)及び半導体活性層(7)を順次形成する工
程を含んでなることを特徴とする薄膜トランジスタマト
リックスの形成方法。(2)前項記載の導電膜(2)が
ポリシリコンで形成され選択酸化のレジストマスク(3
)が窒化シリコンであることを特徴とする特許請求の範
囲第(1)項記載の薄膜トランジスタマトリックスの形
成方法。 (3)導電膜(2)を選択酸化する工程が陽極酸化もし
くは熱酸化の何れかであることを特徴とする特許請求の
範囲第(1)項記載の薄膜トランジスタマトリックスの
形成方法。
[Claims] (1) After forming a conductive film (2) on the entire surface of a flat substrate (1), the conductive film (2) is selectively oxidized using a resist mask (3) on the conductive film (2). A thin film transistor comprising the steps of simultaneously forming a gate electrode (4) and a gate bus line (5), and then sequentially forming a gate insulating film (6) and a semiconductor active layer (7). How to form a matrix. (2) The conductive film (2) described in the previous section is formed of polysilicon and the selective oxidation resist mask (3)
2. The method for forming a thin film transistor matrix according to claim 1, wherein said material is silicon nitride. (3) The method for forming a thin film transistor matrix according to claim (1), wherein the step of selectively oxidizing the conductive film (2) is either anodic oxidation or thermal oxidation.
JP6532286A 1986-03-24 1986-03-24 Formation of thin film transistor matrix Pending JPS62221159A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6532286A JPS62221159A (en) 1986-03-24 1986-03-24 Formation of thin film transistor matrix

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6532286A JPS62221159A (en) 1986-03-24 1986-03-24 Formation of thin film transistor matrix

Publications (1)

Publication Number Publication Date
JPS62221159A true JPS62221159A (en) 1987-09-29

Family

ID=13283555

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6532286A Pending JPS62221159A (en) 1986-03-24 1986-03-24 Formation of thin film transistor matrix

Country Status (1)

Country Link
JP (1) JPS62221159A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0506117A2 (en) * 1991-03-29 1992-09-30 Casio Computer Company Limited Thin-film transistor
US5899711A (en) * 1996-10-11 1999-05-04 Xerox Corporation Method for enhancing hydrogenation of thin film transistors using a metal capping layer and method for batch hydrogenation
JP2004311962A (en) * 2003-03-24 2004-11-04 Konica Minolta Holdings Inc Thin film transistor element, thin film transistor element sheet and its manufacturing method
US7317206B2 (en) 2003-03-12 2008-01-08 Samsung Sdi Co., Ltd. Conductive elements for thin film transistors used in a flat panel display

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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JP2004311962A (en) * 2003-03-24 2004-11-04 Konica Minolta Holdings Inc Thin film transistor element, thin film transistor element sheet and its manufacturing method
JP4581423B2 (en) * 2003-03-24 2010-11-17 コニカミノルタホールディングス株式会社 Thin film transistor element, element sheet and method for manufacturing the same

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