JPH0918007A - Thin film transistor and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve an ON-state current and to obtain a high ON-state current and a low OFF-state current. SOLUTION: A silicon thin film 5 is polycrystal, a gate electrode 3 is opposing to a channel 6 pinching a gate insulating film 4, and a drain electrode 10 and a source electrode 11 are connected to a drain region 7 and a source region 8 respectively. The silicon thin film 5 is obtained by crystallization by the growth of a solid face after deposition in thin film state of amorphous Si on the gate insulating film 4. Moreover, the rate of (311) orientation is increased next to (111) orientation by the conduction of oxidizing treatment and an RTA after crystallization. Consequently, as the mobility of the silicon thin film 5 is high and the interface level between the silicon thin film 5 and an oxide film is small, an ON-curent becomes high and an OFF-current becomes low.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a method for manufacturing the same, and more particularly to an improvement for increasing on-current and reducing off-current.

[0002]

_2. Description of the Related Art A transistor in which a semiconductor thin film is formed on an insulating substrate such as a quartz (SiO ₂ ) substrate and a channel or the like is formed in the film to make an active region is known as a thin film transistor. . The crystal structure of a semiconductor thin film is
Usually, it is either polycrystalline or amorphous. Among these, a transistor in which a semiconductor thin film has a polycrystalline structure, that is, a polycrystalline thin film transistor is known to have superior characteristics to those having an amorphous structure, such as high mobility and thermal stability. There is.

A conventional polycrystalline thin film transistor has been manufactured by the following method. First, by performing CVD (Chemical Vapor Deposition) on a SiO ₂ substrate or a substrate having SiO ₂ deposited on the upper surface while supplying silane gas as a reaction gas, amorphous silicon is formed on the substrate. (Hereinafter, abbreviated as “a-Si”) is deposited. After that, SPC (Solid Phase Crystallization;
Solid phase growth) is performed to convert a-Si into polycrystalline silicon. As a result, a polycrystalline silicon thin film formed on the substrate is obtained. This SPC is
This is accomplished by annealing the a-Si.

Thereafter, a polycrystalline thin film transistor is obtained through steps such as introducing a predetermined impurity into the polycrystalline silicon thin film and connecting electrodes.

[0005]

Since the conventional polycrystalline thin film transistor is manufactured by the manufacturing method described above, (1)
It had a polycrystalline silicon thin film having the 11) plane as the main plane orientation (main orientation). That is, of the many crystal grains forming the polycrystalline silicon thin film, the majority have the (111) plane as the plane orientation. Moreover, the (220) plane had the second largest plane orientation after the (111) plane.

However, as is well known, (11
A silicon crystal having a plane orientation of (1) has a lower mobility than a crystal having a plane orientation of the most ideal (100) plane, and also has an interface state generated with an oxide film of (10).
0) Larger than that of plane orientation. Also,
The same applies to a silicon crystal having a (220) plane as a plane orientation. Therefore, the conventional thin film transistor has a problem that the on-current (main current during conduction) is small because the mobility of the polycrystalline silicon thin film is low. In addition, there is a problem that the off-state current (leakage current at the time of interruption) is large because the interface level of the polycrystalline silicon thin film is large.

The present invention has been made to solve the above-mentioned problems in the conventional device, and an object thereof is to obtain a thin film transistor having a high on-current and a low off-current, and further suitable for manufacturing this thin film transistor. The purpose is to provide a method.

[0008]

The device of the first invention is a thin film transistor having an active region formed of a polycrystalline semiconductor thin film, and in the plane orientation ratio of the semiconductor thin film, the device is next to the (111) plane. It is characterized in that the (311) plane is the highest.

According to a second aspect of the present invention, in the thin film transistor of the first aspect, the semiconductor thin film includes a channel region facing the gate electrode with an insulating film interposed therebetween, and a source region and a drain region sandwiching the channel region. In addition, a P-type impurity is introduced into the source region and the drain region.

The manufacturing method of the third invention is a method for manufacturing a thin film transistor in which an active region is composed of a polycrystalline semiconductor thin film, wherein (a) an amorphous semiconductor is deposited in a thin film on an insulator. And (b) converting the amorphous semiconductor into a thin film polycrystalline semiconductor by performing solid phase growth on the amorphous semiconductor,
(c) a step of forming the polycrystalline semiconductor thin film from the polycrystalline semiconductor, the step (c), (c-1) the polycrystalline semiconductor, an oxide film is formed on the surface layer To the extent that it is heated in a gas containing oxygen in a temperature range of approximately 700 ° C to 1000 ° C, and (c-2) the polycrystalline semiconductor is R
Heating to a temperature of about 950 ° C. or higher by applying TA.

The manufacturing method of the fourth invention is the method of manufacturing a thin film transistor of the third invention, wherein the step (c-2)
Is performed after impurities of a predetermined conductivity type have been introduced into the polycrystalline semiconductor.

[0012]

In the thin film transistor of the first invention, the (311) plane close to the (100) plane has the highest plane orientation ratio next to the (111) plane in the plane orientation ratio of the polycrystalline semiconductor thin film forming the active region. The mobility is high and the interface state formed with the oxide film is small.

The thin film transistor of the second invention is constructed as a P-channel type field effect transistor (FET). Since the mobility of holes is particularly high in the semiconductor having the (311) plane orientation, the on-current is significantly improved in the device of the second invention in which holes are the main carriers as compared with the conventional device.

In the manufacturing method of the third invention, after the thin film amorphous semiconductor is made polycrystalline by solid phase growth,
Since both the oxidation treatment and the RTA are performed, the polycrystalline semiconductor thin film to be formed has good characteristics (3
The ratio of the (11) plane orientation is the highest next to the (111) plane orientation. Moreover, the ratio of the (111) plane orientation is lower than that in the case where only the oxidation treatment is performed,
The ratio of (311) plane orientation is higher.

In the manufacturing method of the fourth aspect of the invention, RTA is carried out after impurities of a predetermined conductivity type have been introduced into the polycrystalline semiconductor, so that RTA simultaneously achieves not only improvement of the plane orientation but also activation of the impurities. be able to. That is, there is no need to perform a separate heat treatment to activate the impurities.

[0016]

EXAMPLES <Device Configuration> FIG. 1 is a front sectional view showing a configuration of a thin film transistor of an example. In FIG. 1, 1 is a substrate such as a glass substrate, 2 is an interlayer insulating film formed on the substrate 1, 3 is a gate electrode selectively formed on the interlayer insulating film 2, and 4 is an interlayer insulating film. 2 is a gate insulating film formed to cover the gate electrode 3, 5 is a polycrystalline silicon thin film formed on the gate insulating film 4, and 6 is a region of the silicon thin film 5 facing the gate electrode 3. Are the regions sandwiching the channel 6 in the silicon thin film 5, and the drain region 7 and the source regions 8 and 9 introduced with P-type impurities are formed so as to cover the silicon thin film 5, respectively. Another interlayer insulation film,
Reference numeral 10 is a contact hole 12 formed in the interlayer insulating film 9.
The drain electrode 11 is connected to the drain region 7 through the source electrode 11, and the source electrode 11 is connected to the source region 8 through the contact hole 13 formed in the interlayer insulating film 9.

That is, the thin film transistor of FIG. 1 is an example of a bottom gate type FET. The interlayer insulating film 2 and the gate insulating film 4 are made of, for example, SiO ₂ , and the gate electrode 3 is made of, for example, polysilicon (polycrystalline silicon) having impurities introduced. The interlayer insulating film 9 is made of, for example, SiO ₂ , and the drain electrode 10 and the source electrode 11 are made of, for example, aluminum.

FIG. 2 shows the structure of another thin film transistor. In FIG. 2, the same or corresponding parts as those of the device shown in FIG. 1 are designated by the same reference numerals and detailed description thereof is omitted. In the device of FIG. 2, the gate electrode 3
Is characteristically different from the device of FIG. 1 in that it is provided on the gate insulating film 4 formed on the silicon thin film 5. That is, the thin film transistor of FIG. 2 is an example of a top gate type FET.

In these devices, the polycrystalline silicon thin film 5 has the (111) plane as the first-largest plane orientation, and then the (311) plane as the second-largest plane orientation. It is characteristically different from the conventional device.
The direction of the (311) plane is similar to that of the (100) plane. The angle θ between the (311) plane and the (100) plane is
Can be calculated from Then, as shown in Expression 2, a value of 25 ° is obtained as the angle θ.

[0020]

[Equation 1]

[0021]

[Equation 2]

That is, the (311) plane is only slightly inclined with respect to the (100) plane. Therefore, (3
A silicon crystal having a (11) plane as a plane orientation has (1
It is similar to a silicon crystal whose plane orientation is the (00) plane,
It has the characteristics of high mobility and small interface state with the oxide film.

Therefore, the device of this embodiment has an advantage that the ON current is larger than that of the conventional device because the mobility of the polycrystalline silicon thin film is high. In addition, since the interface state of the polycrystalline silicon thin film is small, there is an advantage that the off current, that is, the leak current is smaller than that of the conventional device.

Further, since the silicon crystal having the (311) plane as the plane orientation has a characteristic that the mobility of holes is particularly high, the P-type impurity such as boron is introduced into the drain region 7 and the source region 8. In the channel type thin film transistor, the difference from the conventional device is particularly remarkable.

<Manufacturing Method of Device> Next, the manufacturing method of the device of this embodiment will be described by taking the device of FIG. 1 as an example. 3 to 9 are manufacturing process diagrams showing an example of a method of manufacturing the device of FIG. In order to manufacture this device, first, as shown in FIG. 3, a substrate 1 such as a glass substrate is prepared, and then an interlayer insulating film 2 is formed by depositing SiO ₂ on the substrate 1, The gate electrode 3 is formed on the interlayer insulating film 2. The technique of forming the gate electrode 3 is well known in the art. The gate electrode 3 is composed of, for example, polysilicon doped with impurities or polycide forming a multi-layer structure with silicide.

Next, as shown in FIG. 4, the gate electrode 3
Then, the gate insulating film 4 is formed by depositing SiO ₂ so as to cover the interlayer insulating film 2. Then, the a-Si thin film 14 is formed on the gate insulating film 4 by performing CVD while supplying, for example, silane gas as a reaction gas.

Next, as shown in FIG. 5, a-Si is subjected to SPC in the same manner as in the conventional method of manufacturing a device, and a-S is used.
The i thin film 14 is converted into a polycrystalline silicon thin film 15.
Further, the silicon thin film 15 is subjected to an oxidation treatment to form an oxide film 16 on its surface layer. The oxidation treatment is
The heat treatment is performed in an oxygen atmosphere (in the case of dry oxidation) or in an atmosphere of oxygen and water vapor (in the case of wet oxidation). The temperature of the heat treatment is about 700
Set to a value in the range of ° C to 1000 ° C, for example 82
It is set to 0 ° C. The heating time is set to such an extent that an oxide film is formed on the surface layer of the silicon thin film 15.

Further, as shown in FIG. 6, the silicon thin film 15 is subjected to RTA (Rapid Thermal Aneal). RTA
In this method, the target silicon thin film 15 is instantaneously annealed at a high temperature by irradiating strong infrared rays for a short time. This RTA is carried out, for example, in a nitrogen atmosphere to prevent oxidation, and is carried out at a temperature of approximately 950 ° C. or higher, for example, 1050 ° C., for example, for 30 seconds. As described above, the point that the oxidation treatment and the RTA are performed on the silicon thin film 15 is the most important feature point in the manufacturing method of this embodiment. Then, as will be described later, the plane orientation of the silicon thin film 15 is improved by these oxidation treatments and RTA.

Next, as shown in FIG. 7, the silicon thin film 15 is patterned into a predetermined shape by selectively etching the silicon thin film 15.

Subsequently, as shown in FIG. 8, a resist film 17 patterned so as to selectively cover the region located above the gate electrode 3 is formed on the silicon thin film 15. Then, by using this resist film 17 as a shield, N-type or P-type impurities are selectively introduced into the silicon thin film 15. As a result, the drain region 7 and the source region 8 are formed in the region where the impurities are introduced. That is, the silicon thin film 5 having the drain region 7, the source region 8 and the channel 6 sandwiched between them and facing the gate electrode 3 is obtained. afterwards,
The resist film 17 is removed.

Next, as shown in FIG. 9, the interlayer insulating film 9 is formed by depositing, for example, SiO ₂ so as to cover the silicon thin film 5 and the interlayer insulating film 2. In FIG. 9, the interlayer insulating film 9 is drawn so as to include the oxide film 16. When the interlayer insulating film 9 is made of SiO ₂ , the interlayer insulating film 9 and the oxide film 16 are made of the same material and are virtually indistinguishable.

Next, returning to FIG. 1, by selectively etching the interlayer insulating film 9 (including the oxide film 16 located therebelow), the upper surfaces of the drain region 7 and the source region 8 are respectively etched. Open contact holes 12 and 13 are formed. Then, for example, aluminum is deposited so as to fill these contact holes 12 and 13 and cover the upper surface of the interlayer insulating film 9. Then, the deposited aluminum is patterned into a predetermined wiring shape by selective etching.
The apparatus shown in FIG. 1 is completed through the above steps.

In the above description, the RTA is applied after the SPC process shown in FIG. 5 and before the patterning of the silicon thin film 15 shown in FIG. Alternatively, however, the RTA may be performed after the process of FIG. 8 is completed and before the process of FIG. 9 is performed. Alternatively, FIG.
This step may be performed after the step (1) and before the aluminum deposition in FIG.

When the RTA is performed after the predetermined impurities are introduced into the silicon thin film 15, both the activation of the impurities and the improvement of the plane orientation are simultaneously achieved by the RTA. That is, there is an advantage that it is not necessary to perform a separate heat treatment for activating the impurities.

<Demonstration Data> Next, the results of a demonstration test conducted on the P-channel thin film transistor manufactured by the above manufacturing method will be described. 10 and 11 are graphs showing measurement results regarding the ratio of the plane orientation of the manufactured thin film transistor. The measurement was performed using the X-ray diffraction technique known in the art. FIG. 10 and FIG.
1, the horizontal axis corresponds to various plane orientations, and the vertical axis represents the area ratio occupied by crystal grains having each plane orientation.

FIG. 11 is drawn including data regarding plane orientations higher than that in FIG. The higher the plane orientation,
Although the detection sensitivity decreases due to the decrease in the X-ray diffraction intensity, FIGS. 10 and 11 depict data in which the difference in detection sensitivity is corrected. Therefore, it is possible to compare the area ratios between the plane orientations based on these figures.

Among the four types of codes, the white circles are aS.
The data on the device in which only the SPC is applied to the i thin film 14, that is, the data on the conventional device are shown. The black triangle indicates the device subjected to oxidation treatment in addition to SPC, and the black square indicates RTA in addition to SPC.
And the black circles represent data on the device of the example obtained by performing both oxidation treatment and RTA in addition to SPC.

In the device (S) obtained by performing only SPC, the ratio of the (111) plane orientation is the highest at about 64%,
Next, the (220) plane orientation is the second highest at 20%,
11) The plane orientation is the third highest at around 16%.
And, except for these plane orientations, they are hardly found.

On the other hand, in the device (S + O) obtained by further oxidizing SPC, the ratio of the (111) plane orientation and the (220) plane orientation both decreased,
Instead, the ratio of the (311) plane orientation has risen to about 23%. The ratio of the (311) plane orientation is (1
It is the second highest after 11). Further, plane orientations higher than (311) are hardly found. Thus, S
In the device (S + O) that has been subjected to PC and oxidation treatment, the ratio of unfavorable plane orientations is reduced and the ratio of desirable plane orientations is higher than in the conventional device. That is, the plane orientation is improved as compared with the conventional device.

Further, in the device (S + R) obtained by further subjecting SPC to RTA, the ratios of the (111) plane orientation and the (220) plane orientation are both reduced, and instead of the (331) plane orientation, The ratio has risen to around 34%. Then, the ratio of the (311) plane orientation is limited to the identification degree with the device provided with only SPC, and (33
1) The ratio of the plane orientation is the second highest after the (111) plane orientation.

Since the (331) plane is close to the (110) plane, the silicon crystal having the (331) plane as the plane orientation is characteristically similar to the silicon crystal having the (110) plane as the plane orientation. Both the mobility and the interface state with the oxide film are
It is inferior to the one having the (311) plane as the plane orientation. Therefore, in the device (S + R) obtained by performing only SPC and RTA, neither the on-current nor the off-current is necessarily improved as compared with the conventional device.

Next, in the device (S + O + R) obtained by subjecting SPC to both oxidation treatment and RTA, (111)
The ratios of the plane orientation and the (220) plane orientation both decrease, and instead, the proportion of the (311) plane orientation rises to about 28%. Then, the ratio of the (311) plane orientation is the second highest after (111). In addition, (31
Almost no higher plane orientations than 1) are found.

As described above, in this apparatus (S + O + R), the apparatus (S + O + R) obtained by adding only the oxidation treatment to SPC was used.
In addition, the ratio of unfavorable plane orientations is lower than that of + O), and the ratio of preferable plane orientations is improved. That is,
The device (S + O + R) has a more improved plane orientation than the device (S + O). As a result, this device (S + O
+ R) provides even better on and off currents than the device (S + O).

FIG. 12 shows an apparatus (S) in which only SPC was applied, and an apparatus (S +) obtained by adding oxidation treatment to SPC.
O), and three types of devices (S + O + R) obtained by adding both oxidation treatment and RTA to SPC,
Drain current is a graph showing the results of measuring the relationship between (main current) I _D and the gate voltage V _G. In FIG.
Gate voltage V _G is the drain current I _D of the left-half plane is a negative value corresponds to the on-current, the gate voltage V _G is the drain current I _D of the right half plane is a positive value corresponds to the off-state current.

As shown in FIG. 12, the on-current is SPC.
It is higher in the device obtained by adding the oxidation treatment to SPC than in the device subjected to only oxidation, and is even higher in the device obtained by adding both the oxidation treatment and RTA to SPC. On the contrary, the off-current is lower in the device obtained by adding SPC to the oxidation treatment than in the device subjected to SPC only.
It is even lower in the device obtained by adding both of TA.

That is, in the device to which the oxidation treatment is added as compared with the conventional device in which only SPC is applied, the on-current,
Improvement in both off current was observed, and oxidation treatment and R
A further improvement is seen with the device where both TAs were added. That is, the result as expected from the measured data of FIGS. 10 and 11 is obtained.

<Manufacturing Method of Top Gate Type Device> The manufacturing method described above is based on the manufacturing method of the bottom gate type device of FIG. 1 as an example, but the manufacturing method of the top gate type device of FIG. , SPC, it is possible to perform the same treatment, that is, the oxidation treatment and the RTA, and the same effect is obtained.

[0048]

In the thin film transistor of the first aspect of the invention, in the plane orientation ratio of the polycrystalline semiconductor thin film forming the active region, the (311) plane close to the (100) plane is (11)
1) Since it is the highest next to the surface, the mobility is high and the interface state formed with the oxide film is small. Therefore, there is an effect that the on-current is high and the off-current is low.

The thin film transistor of the second invention is formed as a P-channel type field effect transistor (FET). Since the mobility of holes is particularly high in the semiconductor having the (311) plane orientation, the on-current is significantly improved in the device of the second invention in which holes are the main carriers as compared with the conventional device.

In the manufacturing method of the third invention, after the thin film amorphous semiconductor is made polycrystalline by solid phase growth,
Since both the oxidation treatment and the RTA are performed, in the formed polycrystalline semiconductor thin film, the ratio of the (311) plane orientation is the highest after the (111) plane orientation. Moreover, compared with the case where only the oxidation treatment is applied, (11
The ratio of 1) plane orientation is lower, and the ratio of (311) plane orientation is higher. Therefore, compared to the conventional device, the mobility,
A semiconductor thin film having an improved interface state with the oxide film can be obtained. That is, a thin film transistor with high on-current and reduced off-current can be obtained.

In the manufacturing method of the fourth aspect of the invention, RTA is carried out after impurities of a predetermined conductivity type have been introduced into the polycrystalline semiconductor, so that RTA achieves both improvement of the plane orientation and activation of the impurities. Therefore, it is not necessary to perform a separate heat treatment for activating the impurities, so that the manufacturing process is simplified accordingly.

[Brief description of the drawings]

FIG. 1 is a front cross-sectional view of a thin film transistor of an example.

FIG. 2 is a front cross-sectional view of another thin film transistor of the example.

FIG. 3 is a manufacturing process diagram of the thin film transistor of FIG. 1.

FIG. 4 is a manufacturing process diagram of the thin film transistor of FIG.

5 is a manufacturing process diagram of the thin film transistor of FIG. 1. FIG.

6A to 6C are manufacturing process diagrams of the thin film transistor of FIG.

FIG. 7 is a manufacturing process diagram of the thin film transistor of FIG. 1.

FIG. 8 is a manufacturing process diagram of the thin film transistor of FIG. 1.

FIG. 9 is a manufacturing process diagram of the thin film transistor of FIG. 1.

10 is a graph showing measurement results of the thin film transistor of FIG.

11 is a graph showing measurement results of the thin film transistor of FIG.

FIG. 12 is a graph showing measurement results of the thin film transistor of FIG.

[Explanation of symbols]

3 gate electrode, 4 gate insulating film (insulating film), 5 silicon thin film (semiconductor thin film), 6 channel (channel region), 7 drain region, 8 source region, 2 interlayer insulating film (insulator), 14 a-Si thin film (Amorphous semiconductor), 15 silicon thin film (polycrystalline semiconductor), 16 oxide film.

Claims (4)

[Claims] 1. A thin film transistor having an active region formed of a polycrystalline semiconductor thin film, wherein a ratio of plane orientations of the semiconductor thin film is highest in a (311) plane after a (111) plane. Thin film transistor. 2. The thin film transistor according to claim 1, wherein the semiconductor thin film has a channel region facing the gate electrode with an insulating film interposed therebetween, and a source region and a drain region sandwiching the channel region, A thin film transistor, wherein P-type impurities are introduced into the source region and the drain region. 3. A method for manufacturing a thin film transistor in which an active region is composed of a polycrystalline semiconductor thin film, the method comprising: (a) depositing an amorphous semiconductor in a thin film on an insulator; and (b) A step of converting the amorphous semiconductor into a thin film polycrystalline semiconductor by performing solid phase growth on the amorphous semiconductor; and (c) forming the polycrystalline semiconductor thin film from the polycrystalline semiconductor. In the step (c), (c-1) heating the polycrystalline semiconductor in a temperature range of about 700 ° C to 1000 ° C in a gas containing oxygen to the extent that an oxide film is formed on the surface layer. And a step (c-2) of heating the polycrystalline semiconductor to a temperature of about 950 ° C. or higher by performing RTA on the polycrystalline semiconductor. 4. The method of manufacturing a thin film transistor according to claim 3, wherein the step (c-2) is performed after impurities of a predetermined conductivity type are introduced into the polycrystalline semiconductor. Production method.