JPS5940307B2 - Manufacturing method of insulated gate field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate type field effect transistor, particularly an insulated gate type field effect transistor in which a semiconductor surface in a parasitic part is passivated with a semi-insulating polycrystalline silicon film SIPOSVC in order to prevent the generation of parasitic MOS. Relates to the manufacturing method of field effect transistors.

Insulated gate field effect transistor integrated circuit (commonly known as M
It is known that in an OS-IC, if a semi-insulating polycrystalline silicon film is used for passivation of the parasitic portion, the parasitic threshold voltage Vth increases. The easiest manufacturing method for introducing such a semi-insulating polycrystalline silicon film into an integrated circuit of an insulated gate field effect transistor is the manufacturing method shown in FIG. That is, S is formed on the main surface of the silicon semiconductor substrate 1 of the first conductivity type, for example, the N type.
After forming a source region 3 and a drain region 4 of the second conductivity type, that is, P type, by diffusion through a diffusion mask 2 made of an iO2 film or the like, the diffusion mask 2 is removed and a semi-insulating film is formed over the entire main surface of the substrate 1. A polycrystalline silicon film 5 and a SiO2 film 6 are sequentially deposited by CVD (chemical vapor deposition) (FIGS. 1A and 1B). Next, the portions of the films 5 and 6 corresponding to the gate portions are selectively removed by photo-etching, that is, gate windows are opened, and then a gate insulating layer (SiO2 film) T of a predetermined thickness is formed by thermal oxidation. After that, electrode windows are opened to form a source electrode s, a gate electrode G, and a drain electrode D, respectively (FIG. 1C and D). Although such a manufacturing method is simple, it causes defects in characteristics.

That is, a semi-insulating polycrystalline silicon film 5 is deposited on the entire surface in contact with the substrate 1, and the interface between the film 5 and the substrate 1 is made clear in the subsequent gate window opening process, that is, selective etching process for the film 5.
It is difficult to accurately etch only the film 5.
The surface charge density Qss of the etched gate portion increases, and the threshold voltage Vth of the gate portion fluctuates. Further, during the thermal oxidation process during the formation of the gate insulating layer T, impurities from the substrate 1 are re-diffused into the semi-insulating polycrystalline silicon film 5, or oxygen from the upper SiO2 film 6 is re-diffused. The properties of 5 change. The present invention provides a method for manufacturing an insulated gate field effect transistor that avoids these drawbacks, is easy to manufacture, and has stable characteristics.

Hereinafter, a method for manufacturing an insulated gate field effect transistor according to the present invention will be explained with reference to examples. FIG. 2 is a cross-sectional view showing an embodiment of the present invention in the order of steps. First, a first conductive layer semiconductor substrate 11 having a specific resistance of 2 to 3 Ωcm, that is, an N-type silicon semiconductor substrate 11 is provided, and a gate insulating layer with a thickness of about 1000 A is formed on one principal surface by thermal oxidation. S of
An iO2 film 12 is deposited (FIG. 2A). Next, on this SiO2 film 12, a polycrystalline silicon layer 13 with a thickness of, for example, about 5000λ, which will be used as a gate conductive layer, is deposited using carbon dioxide.
Adhesion is formed by VD method (Fig. 2B).

Next, the SiO2 film 12 and the polycrystalline silicon layer 13 are photo-etched to form source and drain diffusion windows 14S and 14D. Diffuse P-type impurities,
A source region 15 and a drain region 16 are formed.

In this step, P is also applied to the polycrystalline silicon layer 13 at the same time.
The polycrystalline silicon layer 13 is made conductive by doping with a type impurity. In this step, a gate insulating layer 17 made of an SiO2 film 12 and a gate conductive layer 18 made of an impurity-doped polycrystalline layer 13 are formed, and this gate conductive layer 18 serves as a self-aligning source for the source region 15 and drain region 16. , gate insulating layer 17 and source and tray 7 regions 1
5 and 16 is reduced, and stray capacitance can be reduced (FIG. 2C). Next, the unnecessary SiO2 film 12 and polycrystalline silicon layer 13 are removed leaving the gate insulating layer 17 and the gate conductive layer 18, and then the entire surface of the semiconductor including the top of the gate conductive layer 18 is coated with a thick layer by CVD. 1000A
semi-insulating polycrystalline silicon film with a thickness of 19 and a thickness of 8000 mm
A SiO2 film 20 having a thickness of about X is deposited (FIG. 2 D and E).

The semi-insulating polycrystalline silicon film 19 has a concentration of 14 to 35 at 0 m%
It is made of a polycrystalline silicon film containing oxygen, and has a specific resistance of 107ΩCm to 10110cm, and can be grown at 650°C using a reaction system of SiH4-N2O-N2 by the CVD method (Fig. 2E). ). After that, Si
Gate, source, and drain electrode windows are formed in the O2 film 20 and the semi-insulating polycrystalline silicon film 19, respectively, and a gate electrode G is formed in contact with the gate conductive layer 18VC through the multiple windows.
, a source electrode S in contact with the source region 15 and a drain electrode D in contact with the drain region 16 are formed, and a back electrode 21 is formed on the back surface of the substrate 11. Each electrode G, S, D
and 21 may be formed, for example, by aluminum vapor deposition. In this way, a so-called silicon gate insulated field effect transistor having a parasitic portion covered with a semi-insulating polycrystalline silicon film 19 is obtained as shown in FIG. 2F. In this example, impurity-doped polycrystalline silicon 13 is used as the gate conductive layer 19, but instead, for example, a vapor deposited layer of molybdenum may be used to configure a so-called molybdenum gate type insulated gate field effect transistor. You can also do it.

According to this manufacturing method, since the semi-insulating polycrystalline silicon film 19 is formed after forming the gate insulating layer 17 and the gate conductive layer 18, the semi-insulating polycrystalline silicon film 19 does not come into direct contact with the silicon substrate 11. .

However, since there is no gate window opening process for the semi-insulating polycrystalline silicon film 19VC, the surface charge density at the gate part Qss
There is no change in , therefore the threshold voltage Vth does not change and is as designed b
The following characteristics are obtained. In addition, thermal oxidation of the gate insulating layer 17 is performed in the first step, and there is no high-temperature treatment after the formation of the semi-insulating polycrystalline silicon layer 19. , or a semi-insulating polycrystalline silicon layer 19 that does not allow oxygen etc. to enter from the SiO2 film 20.
It is possible to increase the parasitic threshold voltage Th in the parasitic portion without altering itself. Further, the gate conductive layer 18 is self-aligned with the source region 15 and drain region 16, so that there is less overlap between the gate insulating layer 17 and the source and drain regions 15 and 16, and stray capacitance can be reduced. FIG. 3 is another embodiment of the invention.

First, an N-type silicon semiconductor substrate 11 having a resistivity of, for example, 2 to 3 ΩCm is prepared, and an SiO2 film 22 having a thickness of about 4000 Å is formed on one main surface thereof by thermal oxidation (FIG. 3A). Source and drain diffusion windows 23S and 23D are formed in this SiO2 film 22 by photo-etching, P-type impurities are diffused through these diffusion windows 23S and 23D, and sheet resistors are formed within the base 11 at predetermined intervals. A source region 1 and a drain region 16 having a ρs of about 50Ω/hole are formed (FIG. 3B).

Next, after removing the SiO2 film 22, thermal oxidation is applied to the entire main surface of the base 11 to form a gate insulating layer with a thickness of 1000 Å.
A SiO2 film 12 of about
A molybdenum layer 24, which becomes a gate conductive layer, is deposited on the film 12 (FIGS. 3C and 3D).

Next, selective etching is performed on the molybdenum layer 24 and the SiO2 film 12, leaving only a portion corresponding to the gate portion between the source region 15 and drain region 16, and removing the rest by etching. For example, hydrochloric acid/hydrogen (HCt+H2O2 mixture) is used as the etching solution for the molybdenum layer 24. After the molybdenum layer 24 is selectively etched, the SiO2 film 12 under the octave is selectively etched using the remaining molybdenum layer as a mask. In this step, a gate insulating layer 17 made of the SiO2 film 12 is formed on the gate portion, and a gate conductive layer 25 made of a molybdenum layer 24 is formed on this gate insulating layer 17 (FIG. 3E). Next, the gate conductive layer 25
A semi-insulating polycrystalline silicon film 19 with a thickness of 1000 Å and an SiO 2 film 20 with a thickness of 8000 Å are deposited over the entire surface of the substrate 11 including the substrate 11 by CVD. The semi-insulating polycrystalline silicon film 19 is made of VCl 4 to 35 as explained in FIG.
A polycrystalline silicon film containing atomic percent oxygen is used (FIG. 3F). After that, windows for taking out the electrodes are formed in the semi-insulating polycrystalline silicon film 19 and the SiO2 film 20VC by ordinary selective etching (FIG. 3G), and each window hole 2 is opened.
A source electrode S, a gate electrode G and a drain electrode D are deposited through 6S, 26G and 26D, and a back electrode 21 is deposited.

Thus, as shown in FIG. 3H, a so-called molybdenum gate type insulated gate field effect transistor whose parasitic portion is covered with a semi-insulating polycrystalline silicon film 19VC is obtained. In the example shown in FIG. 3, a molybdenum vapor deposited layer is used as the gate conductive layer 25, but impurity-doped polycrystalline silicon may be used instead to form a silicon gate structure. Even with such a manufacturing method, the gate insulating layer 17 and the gate conductive layer 2
After forming 5, a semi-insulating polycrystalline silicon film 19 is formed, so that the semi-insulating polycrystalline silicon film 19 does not directly contact the silicon substrate 11VC, and a gate window is opened for the semi-insulating polycrystalline silicon film 19. Since there is no process, there is no change in the surface charge density Qss at the gate, and therefore the threshold voltage T
Characteristics as designed can be obtained without fluctuation of h.

At the same time, since thermal oxidation of gate insulating layer 17 is performed before forming semi-insulating polycrystalline silicon layer 19, the film quality of semi-insulating polycrystalline silicon layer 19 is maintained. In the above example of FIGS. 2 and 3, a thermally oxidized SiO2 film was used as the insulated gate structure, but other SiO2 and Si3O4
It can also be applied to a multilayer insulated gate structure including a uniform oxide film, a non-volatile memory gate structure, etc.

As described above, the present invention enables easy manufacturing and coating of parasitic parts with a semi-insulating polycrystalline silicon film having excellent properties for preventing the generation of parasitic MOS without impairing the characteristics of the device. A highly reliable insulated gate field effect transistor and its integrated circuit can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing an example of a manufacturing method of an insulated gate field effect transistor according to the present invention, FIG. 2 is a cross-sectional view showing an example of a manufacturing method of the present invention, and FIG. 3A and 3B are cross-sectional views illustrating another embodiment of the manufacturing method of the present invention in the order of steps. 11 is a semiconductor substrate; 12 is a SiO2 film; 13 is a polycrystalline silicon layer; 15 and 16 are source and drain regions; 17 is a gate insulating layer; A semi-insulating polycrystalline silicon film, 20 a SiO2 film, and 25 a gate conductive layer made of molybdenum.

Claims (1)

[Claims] 1. A step of forming a source and a drain, a step of forming a gate insulating layer and a gate conductive layer at least between the source and the drain, and after the above two steps, forming a part of the surface of the source and the drain and a parasitic part. A method for manufacturing an insulated gate field effect transistor, which includes the steps of depositing a semi-insulating layer on a semiconductor surface and forming a predetermined electrode.