JPS6132830B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a vertical junction field effect transistor.

A conventional vertical junction field effect transistor (hereinafter referred to as V-FET) has a structure as shown in FIG. 1d, and is manufactured as follows. The first drain
An underlying oxide film 1 is formed on the surface of a semiconductor substrate 1 having a conductivity type.
1. After sequentially depositing the nitride film 12, as shown in FIG.
1 is sequentially removed and impurities having a second conductivity type are diffused to form a gate region 2. At this time, a channel region 3 contributing to electrical properties is also formed. Subsequently, as shown in FIG. 1b, the nitride film 12 is
is removed, and a thermal oxide film 13 is formed. At this time, as is well known, the thermal oxide film 13 is not formed at the position where the nitride film 12 remains. Next, as shown in FIG. 1c, the remaining nitride film 12 and this nitride film 12 are
The underlying oxide film 11 is sequentially removed, and impurities having the first conductivity type are diffused to form the source region 4. Thereafter, a gate electrode outlet is opened in the thermal oxide film 13, and electrode wirings 5 and 6 are formed to form a V-FET with a surface gate structure as shown in FIG. 1d.
is manufactured.

However, this V-FET manufacturing method has the following drawbacks.

(1) Since the coefficients of thermal expansion of the nitride film 12 and the semiconductor substrate 1 are different, defects are likely to occur on the surface of the semiconductor substrate due to the difference in expansion between the nitride film and the semiconductor during high-temperature treatment in the diffusion process, resulting in poor breakdown voltage yield.

(2) It is difficult to form a passivation film on the surface of the semiconductor substrate between the source and gate regions to prevent impurities from entering from the outside, and the oxide film 13 is likely to be contaminated and the withstand voltage will be deteriorated.

(3) The center position of each source region 4 is determined by gate photolithography, but its width is determined by the underlying oxide film 1.
Since it is determined by the side etching of No. 1 and the digging of the thermal oxide film 13 under the nitride film 12, reproducibility is poor and the distance between the source region 4 and the gate region 2 tends to vary. For this reason, there is usually a large variation in the source/gate breakdown voltage determined by reach-through.

(4) In the selective oxidation method using the nitride film 12, as is well known, at the end of oxidation, in the source region 4 formed at the position where the nitride film 12 remained, A digs deeply into the Si during alloying. As a result, A easily penetrates the shallow source region 4, resulting in poor source/gate breakdown voltage yield.

(5) When removing the nitride film 12 and the underlying oxide film 11 below it to form the source region 4, the thermal oxide film 13 on the gate region 2 is also etched and the film thickness is reduced. Gate area 2
The MOS capacitance between the source electrode and the gate region 2 which also extends upward increases, making it unsuitable for high frequency applications.

The present invention provides a novel V-FET that can overcome the drawbacks of the conventional V-FET structure and manufacturing method.
-Provides a structure of an FET and a method for manufacturing the same.

An embodiment of the present invention will be described below with reference to FIGS. 2a to 2e.

The method for manufacturing the V-FET of the present invention is, for example, as shown below. First, as shown in FIG. 2a, a first oxide film 21 with a thickness of 5000 Å is formed on the surface of an N-type semiconductor substrate 1 that will become a drain, and a phosphorous-doped oxide film 22 (first insulating film P.S.・G film) is sequentially formed to a thickness of 2000 Å.

Next, as shown in FIG. 2b, the P/S/G film 22 and the oxide film 21 on the positions where the gate region and the source region are to be formed are sequentially removed by photolithography to expose the surface of the semiconductor substrate 1. A polycrystalline silicon film 23 and a second oxide film 24 are sequentially deposited to a thickness of 5000 Å and 4000 Å on the surface of the semiconductor substrate 1 including the P.S.G film 22, respectively. This second oxide film 24 may be formed by depositing the polycrystalline silicon film 23 to a thickness of 7000 Å and then oxidizing 2000 Å on the surface side.
Subsequently, the second oxide film 24 on a predetermined region including a position where a gate region is to be formed is removed by photolithography.

The gate window opening width of the mask for selectively removing the second oxide film 24 is the gate window opening width of the mask for selectively removing the P/S/G film 22 and the oxide film 21 (hereinafter referred to as the first mask). If it is made larger, the P/S/G film 22 and the oxide film 21 are removed to form a gate region using the first mask, and the second mask is removed on the area where the surface of the semiconductor substrate 1 is exposed.
Mask alignment for removing the oxide film 24 does not require precision.

Next, as shown in FIG. 2c, a second oxide film 24 is formed.
After removing the polycrystalline silicon film 23 using as a mask,
A predetermined amount of P-type impurity is ion-implanted, and then heat treatment is applied to form the gate region 2. At this time, a channel region 3 contributing to electrical characteristics is also formed. Next, on the surface of the semiconductor substrate 1 including the gate region 2, a third oxide film 25 with a thickness of 6000 Å and a second P/S/G film (second insulating film) 26 with a thickness of 4000 Å are sequentially deposited. The P・S・on the position where the source region is formed
The G film 26, the third oxide film 25, and the second oxide film 24 are sequentially removed by photolithography, and then as shown in FIG.
As shown in FIG. 2, N-type impurities are diffused through the polycrystalline silicon film 23 to form the source region 4. If the source window opening width of the mask used in photolithography is made wider than the source window opening width of the first mask, it is possible to Second P/S/G film 26, third oxide film 25, and second oxide film 24
Mask alignment to remove does not require precision. Note that by diffusing N-type impurities, the polycrystalline silicon film 23 becomes conductive. Subsequently, a window for gate contact is formed in the second P/S/G film 26 and the third oxide film 25, and the A electrode wirings 5 and 6 are formed, as shown in FIG. 2e. A V-FET having the structure of the present invention is obtained.

V-FET and V-FET having the structure of the present invention
The manufacturing method has the following advantages.

(1) The positions where the source region 4 and gate region 2 are to be formed are determined by one mask, and this photolithography is performed without any step in the insulating film, so reproducibility is good. Therefore, the obtained characteristics have very good reproducibility.

(2) All over the device surface except for the electrode extraction area.
It is possible to form a passivation film typified by P/S/G films, which is highly resistant to external contamination and requires little voltage resistance.

(3) A layer of a multilayer insulating film formed on the surface of the semiconductor substrate 1 between the source region 4 and the gate region 2 has an impurity doped between the layers, and as a result has become conductive. Since the polycrystalline silicon film 23 is fixed at the source potential, the charges in the insulating film do not easily move, and there is little deterioration in breakdown voltage.

(4) The source region 4 and gate region 2 can be self-aligned without using a nitride film, which has a coefficient of thermal expansion different from that of a semiconductor and therefore tends to cause defects on the semiconductor substrate surface during the diffusion process. The occurrence of defects is reduced, and the breakdown voltage yield is significantly improved.

(5) Since the source impurity is diffused through the polycrystalline silicon film 23, the diffusion depth of the source region 4 can be made shallow even if the source impurity is deposited at a high concentration.
As a result, the distance between the source and gate can be increased,
Surface gate type V- usually determined by reach-through
FET source/gate breakdown voltage can be increased.

(6) The source electrode 5 is placed on the polycrystalline silicon film 23.
Since it is formed by depositing A, the penetration of A into the Si in the source region 4 during alloying is less than A.
This is suppressed by alloying with polycrystalline silicon, reducing the penetration of A into the shallow source region 4, and increasing the source-to-gate breakdown voltage yield.

(7) Since the gate oxide film can be formed by CVD, it is possible to increase the thickness of the gate oxide film.

Therefore, the MOS capacitance between the source electrode 5 extending over the predetermined gate region 2 via the oxide film and the gate region 2 can be reduced, making it suitable for higher frequencies.

Although the above embodiment has been described using an N-channel V-FET as an example, there is no problem in applying it to a P-channel V-FET. Furthermore, it is clear that the passivation film is not limited to a phosphorus-doped oxide film, and the same effect can be achieved even if a lead-doped oxide film or the like is used.

As described above, according to the present invention, first and second insulating films having a passivation effect are formed over the entire surface of the device except for the electrode extraction region, and
A polycrystalline silicon film is formed in a portion between the source region and the gate region between the first and second insulating films so as to continuously cover the source region on the main surface of the substrate. The material is made conductive by impurity diffusion to stabilize the surface potential of the substrate between the source region and the gate region, so a reliable passivation effect can be obtained and breakdown voltage deterioration can be significantly reduced. Since no nitride film is used during manufacturing, the occurrence of defects on the substrate surface during high-temperature treatment in the diffusion process is reduced, and the withstand voltage yield is significantly improved.

[Brief explanation of the drawing]

Figures 1 a to d are schematic cross-sectional views of the main steps of the conventional V-FET manufacturing method, and Figure 2 a
-e are schematic cross-sectional views showing main steps of an embodiment of the V-FET manufacturing method according to the present invention. In the figure, 1 is a semiconductor substrate, 2 is a gate region, 4 is a source region, 5 is a source electrode, 6 is a gate electrode, 21 is a first oxide film, 22 is a P.S.G.
film (first oxide film), 23 is a polycrystalline silicon film,
24 is a second oxide film, 25 is a third oxide film, 26
is the second P/S/G film (second insulating film).
Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A step of sequentially depositing a first insulating film consisting of a first oxide film and an oxide film doped with an impurity such as phosphorus or lead on one principal surface of a semiconductor substrate having a first conductivity type; a step of sequentially and selectively removing the first insulating film and the first oxide film on a predetermined surface area where a gate region is to be formed; step 2 of sequentially depositing oxide films;
a step of sequentially removing the second oxide film and the polycrystalline silicon film on a predetermined surface region including a region where a gate region is to be formed, and introducing an impurity having a second conductivity type to form a gate region; A step of sequentially depositing a third oxide film and a second insulating film made of an oxide film doped with impurities such as phosphorus or lead on the surface of the semiconductor substrate containing the oxide film No. 2, on the region where the source region is to be formed. selectively removing the second insulating film, the third oxide film, and the second oxide film in sequence;
A method for manufacturing a vertical junction field effect transistor, including the step of introducing an impurity having a first conductivity type through the polycrystalline silicon film to form a source region.