JPH04370956A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the diffusion of impurity ions by a barrier film, to obviate the generation of a parasitic diode and to maintain excellent junction characteristics by interposing the barrier film for preventing the diffusion of impurity ions on the junction interface of a first conductive film and a second conductive film. CONSTITUTION:Polycrystalline silicon films as the foundations of a wiring 9a and an electrode 9b are deposited on the main surface of a silicon substrate 1 through a CVD method, and N-type impurity ions are implanted to the polycrystalline silicon films. Tungsten silicide films as the foundations of barrier films 11a, 11b are deposited through a sputtering method. P-type polycrystalline silicon films as the source-drain 15a, 15b of a thin-film transistor are joined with the polycrystalline silicon films, into which N-type impurities are implanted, as the wiring 9a and the electrode 9b through the barrier films 11a, 11b as the tungsten silicide films. Accordingly, the barrier films 11a, 11b function as the stoppers of the diffusion of impurity ions.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices including thin film transistors that have been improved to have good contact without generating parasitic diodes. It is something.

0002

2. Description of the Related Art FIG. 3 shows, for example, the IEEE Ele
ctron Device Letters (vol.
EDL-4, No. 8, P. 272-274, 1989
) and IEICE technical research report (Vol.89
, No. 67, P. 1-6, 1989), etc., is a cross-sectional view of a conventional manufacturing process of a semiconductor device having a thin film transistor.

The structure of a conventional semiconductor device having a thin film transistor will be explained below while explaining the manufacturing process shown in FIG.

Referring to FIG. 3(a), an element isolation oxide film 2 is formed on the main surface of a P-type silicon substrate 1. MOS field effect transistors 100 and 101 are formed in the element region surrounded by the element isolation oxide film 2. MOS field effect transistor 100 includes an N-type source/drain region 7a provided on the main surface of semiconductor substrate 1, and a MOS gate electrode 4a provided on semiconductor substrate 1 via MOS gate oxide film 3a. .

MOS field effect transistor 101 includes an N-type source/drain region 7b provided on the main surface of semiconductor substrate 1, and a MOS gate electrode 4b provided on silicon substrate 1 via MOS gate oxide film 3b. including.

[0006] On the main surface of silicon substrate 1, there is also an N-type impurity layer 8 connected to one of source/drain regions 7b for bonding silicon substrate 1 and a polycrystalline silicon film to be formed later. It is provided.

An interlayer oxide film 10 is formed on the silicon substrate 1 by chemical vapor deposition (CVD) so as to cover the MOS field effect transistor 100 and the MOS field effect transistor 101.
The film is deposited by a CVD method (hereinafter referred to as a CVD method). Interlayer oxide film 1
An opening 10a for exposing the surface of the N-type impurity layer 8 is formed in the 0.

Referring to FIGS. 3(a) and 3(b), the bases of wiring 9a and wiring 9b are placed on the surface of silicon substrate 1 so as to be in contact with the surface of N-type impurity layer 8 exposed through opening 10a. A polycrystalline silicon film is deposited by CVD. After that, N-type impurities are implanted into the polycrystalline silicon film. This polycrystalline silicon film is selectively patterned by photolithography and etching to form interconnections 9a and electrodes 9b.
form.

Referring to FIG. 3(b), wiring 9a and electrode 9
A second interlayer oxide film 10 is deposited on silicon substrate 1 by CVD so as to cover layer b. Interlayer oxide film 10
On top of the thin film transistor gate electrode (hereinafter referred to as TFT)
A polycrystalline silicon film serving as the basis of the gate electrode (12) is deposited by CVD, and P-type impurities are implanted into this polycrystalline silicon film. The TFT gate electrode 12 is formed by selectively patterning the polycrystalline silicon film by photolithography and etching. Subsequently, a TFT gate oxide film 13 covering the TFT gate electrode 12 is deposited by CVD. A contact hole 1 is formed in the interlayer insulating film 10 to expose the surfaces of the wiring 9a and the electrode 9b.
6a and 16b are opened.

Referring to FIG. 3(c), wiring 9a and electrode 9
b and in contact with the surface of the TFT gate electrode 12.
A thin polycrystalline silicon film, which will become the basis of the channel part 14 and source/drains 15a and 15b, is deposited on the silicon substrate 1 by the CVD method so as to cover the silicon substrate 1, and then patterned into a predetermined shape by photolithography. do.

Referring to FIGS. 3(c) and 3(d), the channel portion 14 of the thin polycrystalline silicon film is masked, and P-type impurity ions are implanted into the thin polycrystalline silicon film at low energy to form the source 15a. / form the drain 15b.

0012

[Problems to be Solved by the Invention] Since a conventional semiconductor device having a thin film transistor is constructed as described above, referring to FIG. A certain polycrystalline silicon film has a wiring 9a/electrode 9 implanted with N-type impurity ions.
A PN junction was formed between the capacitor and the capacitor, and a parasitic diode was generated.

The generation of this parasitic diode has the problem of deteriorating device characteristics, such as not being able to supply the necessary power supply voltage and causing fluctuations in the threshold voltage of the MOS transistor.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor device having a thin film transistor that is improved so as not to generate a parasitic diode.

[0015]

[Means for Solving the Problems] A semiconductor device according to the present invention includes a semiconductor substrate, a MOS field effect transistor provided on the semiconductor substrate, and a first MOS field effect transistor electrically connected to the MOS field effect transistor. and a thin film transistor provided above the MOS field effect transistor. The thin film transistor includes a second conductive film that is connected to the first conductive film and serves as a source/drain of the thin film transistor. In order to solve the above problems,
A barrier film for preventing diffusion of impurity ions is interposed at the bonding interface between the first conductive film and the second conductive film.

According to a preferred embodiment of the present invention, the barrier film is preferably a high melting point metal film or a high melting point metal compound film, particularly a titanium-tungsten film,
Titanium nitride films are preferred.

[0017] Also, a high melting point silicide film is preferably used as the barrier film, and a tungsten silicide film and a titanium silicide film are particularly preferred.

Furthermore, the barrier film is preferably an insulating film with a thickness of about 3 nm or less, particularly 3 nm or less.
A silicon nitride film or a silicon oxide film with a thickness of about nm or less is preferable.

The silicon oxide film is preferably formed by lamp annealing.

[0020]

[Operation] According to the semiconductor device according to the present invention, since a barrier film for preventing diffusion of impurity ions is interposed at the bonding interface between the first conductive film and the second conductive film, This barrier film serves as a stopper for diffusion of impurity ions in the first conductive film and the second conductive film.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 1 is a manufacturing process diagram of a semiconductor device having a thin film transistor according to an embodiment of the present invention.

The structure will be explained below while explaining the manufacturing process shown in FIG. Referring to FIG. 1(a),
An element isolation oxide film 2 is formed on the main surface of a P-type silicon substrate 1. In the element region surrounded by the element isolation oxide film 2, M
OS field effect transistors 100 and 101 are formed. The MOS field effect transistor 100 has an LDD structure, and has a low concentration of N formed on the main surface of the semiconductor substrate 1.
A source/drain region consisting of a type impurity diffusion layer 5a and a high concentration N type impurity diffusion layer 7a, and an MO layer on the semiconductor substrate 1.
MOS gate electrode 4a provided through S gate oxide film 3a.

The MOS field effect transistor 101 has an L
It has a DD structure, and includes a source/drain region consisting of a low concentration N-type impurity diffusion layer 5b and a high concentration N-type impurity diffusion layer 7b provided on the main surface of the semiconductor substrate 1, and a MOS gate on the silicon substrate 1. MOS gate electrode 4b provided through oxide film 3b.

On the main surface of the silicon substrate 1, there are also a low concentration N type impurity diffusion layer 5b and a high concentration N type impurity diffusion layer 7b.
An N-type impurity layer 8 is formed to be connected to one of the source/drain regions consisting of and for bonding silicon substrate 1 and a polycrystalline silicon film to be formed later.

An interlayer oxide film 10 is deposited on silicon substrate 1 by CVD so as to cover MOS field effect transistor 100 and MOS field effect transistor 101. An opening is formed in interlayer insulating film 10 to expose the surface of N-type impurity layer 8 .

Thereafter, a polycrystalline silicon film, which will become the basis of wiring 9a and electrode 9b, is deposited by CVD on the main surface of silicon substrate 1 so as to be in contact with the surface of N-type impurity layer 8 exposed through opening 10a. After that, N-type impurity ions are implanted into this polycrystalline silicon film. Thereafter, a tungsten silicide film, which becomes the basis of barrier films 11a and 11b, is deposited by sputtering. Subsequently, the tungsten silicide film and the polycrystalline silicon film are simultaneously patterned by photolithography and etching to form the wiring 9a and the electrode 9 on which the barrier films 11a and 11b are formed.
form b.

An interlayer oxide film 10 is deposited again by the CVD method so as to cover the barrier films 11a and 11b, and then a polycrystalline silicon film, which will become the basis of the TFT gate electrode 12, is deposited on the interlayer insulating film 10 by CVD. A P-type impurity is implanted into this. Next, the polycrystalline silicon film is patterned by photolithography and etching to form a TFT gate electrode 12. Subsequently, a gate oxide film 13 is deposited by CVD to cover the TFT gate electrode 12. After that, barrier films 11a and 11 are formed in the interlayer oxide film 10.
A contact hole 16a for exposing the surface of b.
16b is opened.

Referring to FIG. 1(b), barrier films 11a,
11b and in contact with the TFT gate electrode 12.
A channel 14,
A thin polycrystalline silicon film, which will become the basis of source/drains 15a and 15b, is deposited by CVD.

The channel portion 14 of the thin polycrystalline silicon film is masked, and P-type impurity ions are implanted into the thin polycrystalline silicon film at low energy.
5a and 15b are formed, and the thin film transistor 102 is completed.

According to this embodiment, the P-type polycrystalline silicon film which is the source/drain 15a, 15b of the thin film transistor is replaced by the barrier film 11 which is a tungsten silicide film.
N, which is the wiring 9a and the electrode 9b, via a and 11b.
It is in contact with a polycrystalline silicon film into which type impurities have been implanted. Therefore, barrier films 11a and 11b act as stoppers for diffusion of impurity ions in P-type polycrystalline silicon films (15a, 15b) and N-type polycrystalline silicon films (9a, 9b). As a result, the generation of parasitic diodes is prevented,
In addition, good bonding properties are maintained.

Example 2 In the above example, the case where a tungsten silicide film is used as the barrier film is exemplified, but the present invention is not limited to this, and the same effect can be obtained even if a titanium nitride film is used. Realize the effect. The titanium nitride film is prepared as follows. Referring to FIG. 1, after depositing a polycrystalline silicon film that will become the basis of wiring 9a and electrode 9b, a titanium film is deposited by sputtering, and then this titanium film is deposited at about 800° C. in an N2 atmosphere. , annealing is performed using a lamp annealing method. Thereafter, these are patterned to form wiring (9a, 11a) and electrodes (9b, 11b) in predetermined shapes. The following steps are the same as in Example 1.

Example 3 In this example, a silicon nitride film is used as the barrier film. Although the thickness of the barrier film was not described in the above embodiments, when a silicon nitride film is used as the barrier film, the film thickness is preferably about 3 nm or less.

In order to form such a thin silicon nitride film, referring to FIG. At about 1000℃, in NH3 atmosphere,
This is obtained by annealing using a lamp annealing method, and a silicon nitride film of about 3 nm or less is formed. By patterning these films by photolithography and etching, wiring (10a, 11a)
and electrodes (9b, 11b) are formed. The following process is
This is the same as in Example 1.

Embodiment 4 FIG. 2 is a manufacturing process diagram of a semiconductor memory device having a thin film transistor according to still another embodiment of the present invention.

MOS field effect transistor 100, 10
The steps up to the formation of Example 1 are the same as in Example 1, so the same or corresponding parts are given the same reference numerals and the description thereof will not be repeated.

Referring to FIG. 2(a), a polycrystalline silicon film serving as the basis of wiring 9a and electrode 9b is deposited by CVD, and N-type impurity ions are implanted into this polycrystalline silicon film. Thereafter, patterning is performed by photolithography and etching to form wiring 9a and electrode 9b. Next, the interlayer oxide film 10 is coated with C again so as to cover the wiring 9a and the electrode 9b.
A polycrystalline silicon film is deposited by the VD method, and then a polycrystalline silicon film, which will become the basis of the TFT gate electrode 12, is deposited thereon by the CVD method, and P-type impurity ions are implanted into this. Thereafter, the polycrystalline silicon film is patterned by photolithography and etching to form the THT gate electrode 12. Subsequently, a gate oxide film 13 is deposited by the CVD method so as to cover the TFT gate electrode 12. After that, contact holes 16a and 16b are opened in the interlayer insulating film 10 to expose the surfaces of the wiring 9a and the electrode 9b.

Referring to FIG. 2(b), 800 to 1000
A silicon nitride film or silicon oxide film 17 with a thickness of about 3 nm or less is formed on the upper layer of the wiring 9a and the electrode 9b by heating to about .degree. C. and using a lamp annealing method in an NH3 or O2 atmosphere. In contact with the silicon nitride film or silicon oxide film 17, and the TFT
A thin polycrystalline silicon film, which will become the basis of the channel section 14 and the sources/drains 15a and 15b, is deposited by CVD so as to cover the gate electrode 12. Through photoengraving,
Channel portion 14 is masked and P-type impurity ions are implanted at low energy to form sources and drains 15a and 15b. At this time, the TFT implanted with P-type impurity ions
The polycrystalline silicon film, which is the source/drain 15a, 15b of
It is bonded to a polycrystalline silicon film.

According to this embodiment, the polycrystalline silicon film (including the amorphous silicon film) forming the channel and source/drain of the TFT and the polycrystalline silicon film used for other wiring, electrodes, etc. It becomes possible to flow a direct tunneling current through the junction between the two.

[0040]

As explained above, according to the semiconductor device of the present invention, a barrier film for preventing diffusion of impurity ions is provided at the bonding interface between the first conductive film and the second conductive film. is interposed, the barrier film serves as a stopper for diffusion of impurity ions in the first conductive film and the second conductive film. As a result, it is possible to prevent the generation of parasitic diodes and maintain good junction characteristics.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a manufacturing process of a semiconductor device having a thin film transistor according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the manufacturing process of a semiconductor memory device having a thin film transistor according to another embodiment of the present invention.

FIG. 3 is a cross-sectional view of a conventional manufacturing process of a semiconductor device having a thin film transistor.

[Explanation of symbols]

1 Silicon substrate 9a Wiring 9b Electrode 11a Barrier film 12a Barrier film 14 Channel portion 15a Source/drain 15b Source/drain 100 MOS field effect transistor 101 MO
S field effect transistor 102 thin film transistor

Claims (1)

[Claims] 1. A semiconductor substrate, a MOS field effect transistor provided on the semiconductor substrate, a first conductive film electrically connected to the MOS field effect transistor, and a MOS field effect transistor comprising: a semiconductor substrate; a thin film transistor provided above the first conductive film, and the thin film transistor includes a second conductive film that is connected to the first conductive film and serves as a source/drain of the thin film transistor. A semiconductor device comprising: a bonding interface between the first conductive film and the second conductive film;
A semiconductor device characterized by interposing a barrier film to prevent diffusion of impurity ions.