JPH01100971A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01100971A JPH01100971A JP25885387A JP25885387A JPH01100971A JP H01100971 A JPH01100971 A JP H01100971A JP 25885387 A JP25885387 A JP 25885387A JP 25885387 A JP25885387 A JP 25885387A JP H01100971 A JPH01100971 A JP H01100971A
- Authority
- JP
- Japan
- Prior art keywords
- silicon layer
- polycrystalline silicon
- forming
- film
- impurity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 55
- 239000012535 impurity Substances 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 239000012212 insulator Substances 0.000 claims description 6
- 229910021419 crystalline silicon Inorganic materials 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 40
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 19
- 239000000377 silicon dioxide Substances 0.000 abstract description 18
- 238000010438 heat treatment Methods 0.000 abstract description 8
- 238000009279 wet oxidation reaction Methods 0.000 abstract description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 3
- 239000011574 phosphorus Substances 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 38
- 238000009792 diffusion process Methods 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- 238000001259 photo etching Methods 0.000 description 8
- 239000010409 thin film Substances 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- XWROUVVQGRRRMF-UHFFFAOYSA-N F.O[N+]([O-])=O Chemical compound F.O[N+]([O-])=O XWROUVVQGRRRMF-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置、特に透明絶縁体基板上に形成さ
れる薄膜トランジスタ（−ＴＰＴ）と称される電界効果
トランジスタの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, particularly a field effect transistor called a thin film transistor (-TPT) formed on a transparent insulator substrate.
従来の薄膜トランジスタの構造及び製造方法の一例とし
て、ｎチャンネルシリコンゲート！！薄膜トランジスタ
の製造方法を第２図を用いて説明する。透明絶縁体基板
として石英ガラス２０１を用い、その、上に酸化膜（Ｓ
ｉｎｓ）２０２を形成する。その上に多結晶シリコン層
２０３を形成し、その後、熱酸化によりゲート酸化膜（
Ｓｉｎ、）２０４を形成する。さらにその上に多結晶シ
リコン層２０５を周知の方法で形成後、熱拡散などで不
純物を拡散し、ゲート電極とする。次にフォトエッチ工
程により、選択的に開孔部を設け、イオン打ち込みなど
を行ない、セルファラインでソース領域２０６、ドレイ
ン領域２０７を形成する。An example of the structure and manufacturing method of a conventional thin film transistor is an n-channel silicon gate! ! A method for manufacturing a thin film transistor will be explained with reference to FIG. A quartz glass 201 is used as a transparent insulator substrate, and an oxide film (S
ins) 202. A polycrystalline silicon layer 203 is formed thereon, and then a gate oxide film (
Sin, ) 204 is formed. Further, a polycrystalline silicon layer 205 is formed thereon by a well-known method, and then impurities are diffused by thermal diffusion or the like to form a gate electrode. Next, a photo-etching process is performed to selectively form openings, and ion implantation is performed to form a source region 206 and a drain region 207 with self-alignment lines.
パッジベージ、ン膜２０８を全面につけた後、熱−拡散
を行ない、ソース、ドレイン領域の、抵抗値を下げる。After applying the padding film 208 to the entire surface, thermal diffusion is performed to lower the resistance value of the source and drain regions.
最後に、フォトエッチによりコンタクトホールを開け、
配線材料２０９．２１０を付けて、フォトエッチでバタ
ーニング−を行ない、最終保護膜を全面に付ける。Finally, open a contact hole by photo-etching,
Wiring materials 209 and 210 are applied, patterning is performed by photo-etching, and a final protective film is applied to the entire surface.
（発明が解決しようとする問題点）
上記の従来の製造工程では、コンタクトを形成するのに
、２度のフォトエッチ工程があり、この際に、エツチン
グされるパブシベーシ２ン１１２０８の膜厚の精度によ
り、パフシベーシ２ン膜２０８のエツチング時間に著し
い確度が要求される。(Problems to be Solved by the Invention) In the conventional manufacturing process described above, there are two photo-etching steps to form a contact, and at this time, the accuracy of the thickness of the etched pubsibasic 2 layer 11208 is Therefore, extremely high precision is required for the etching time of the puffed base film 208.
例えば、エツチング時間が短ければ、コンタクトは形成
されず、反対に、エツチング時間が長く、オーバーエッ
チになれば、多結晶シリコン層２０８．２０７までもエ
ツチングされる。For example, if the etching time is short, no contact will be formed; on the other hand, if the etching time is long and over-etching occurs, even the polycrystalline silicon layers 208 and 207 will be etched.
′ＩＩＥ２の欠点は、ゲート酸化膜２０４の形成、多結
晶シリコン層２０５の熱拡散、ソース領域２０Ｂ、ドレ
イ領域２０７を形成するための熱拡散など熱処理工程が
多くなり、工程が複雑となる。The disadvantage of 'IIE2 is that it requires many heat treatment steps such as formation of the gate oxide film 204, thermal diffusion of the polycrystalline silicon layer 205, and thermal diffusion for forming the source region 20B and the drain region 207, making the process complicated.
本発明の目的は、以上の如き欠点をな（シ、従来コンタ
クトを形成する際に、コンタクト部分の多結晶シリコン
届が薄く、また、パフシベーシ９ン膜の膜厚によりエツ
チング時間が左右される為に、正確なコンタクトの形成
が困−難であったことを、予め不純物を拡散した多結晶
シリコン層をコンタクト部分に設けることにより、上記
の困難を解決することを目的とする。The purpose of the present invention is to overcome the above-mentioned drawbacks (in order to overcome the problems described above), when forming a conventional contact, the polycrystalline silicon layer at the contact part is thin, and the etching time is affected by the thickness of the puffed base film. Another object of the present invention is to solve the difficulty in forming accurate contacts by providing a polycrystalline silicon layer in which impurities have been diffused in advance at the contact portions.
本発明の他の目的は、予め不純物を拡散した多結晶シリ
コン層をコンタクト部分に設けることにより、ゲート酸
化膜形成時に、同時にソース領域ドレイン領域への不純
物の拡散を行ない、熱処理工程を少なくすると共に、熱
処理温度を下げることである。また、本発明の他の目的
は、上記２つの目的を達成しながら、工程を簡易にする
ことである。Another object of the present invention is to provide a polycrystalline silicon layer in which impurities have been diffused in advance in the contact portion, thereby simultaneously diffusing impurities into the source and drain regions when forming the gate oxide film, thereby reducing the number of heat treatment steps. , to lower the heat treatment temperature. Another object of the present invention is to simplify the process while achieving the above two objects.
本発明の半導体装置は、透明絶縁体基板表面に第１の酸
化膜を形成する工程、前記第１の酸化膜表面に不純物を
含んだ第１の多結晶シリコン層を形成する工程、前記第
１の多結晶シリコン層を、島状にバターニングする工程
、前記第１の多結晶シリコン層表面及び前記開孔部を覆
って不純物を含まない、第２の多結晶シリコン層を形成
する工程、熱処理により前記第１の多結１シリコン層か
ら前記第２の、多結晶シリコン層へ不純物を拡散して、
ソース領域、ドレイン領域を形成すると共に、前記第２
の多結晶シリコン層表面に第２の酸化膜を形成する工程
、前記第２の酸化膜上にゲート電極を形成する、工程か
らなることを特徴とする。The semiconductor device of the present invention includes a step of forming a first oxide film on the surface of a transparent insulator substrate, a step of forming a first polycrystalline silicon layer containing impurities on the surface of the first oxide film, and a step of forming a first polycrystalline silicon layer containing impurities on the surface of the first oxide film. a step of buttering the polycrystalline silicon layer into an island shape, a step of forming a second polycrystalline silicon layer containing no impurities covering the surface of the first polycrystalline silicon layer and the opening, and heat treatment. Diffusing impurities from the first polycrystalline silicon layer to the second polycrystalline silicon layer,
While forming a source region and a drain region, the second
The method is characterized by comprising the steps of forming a second oxide film on the surface of the polycrystalline silicon layer, and forming a gate electrode on the second oxide film.
（実施例〕
本発明の実施例における半導体装置は、基本的には第１
図で示す構造をしている。(Embodiment) A semiconductor device in an embodiment of the present invention basically consists of a first
It has the structure shown in the figure.
１０１は透明絶縁体基板、１０２は二酸化硅素ＩＩ、１
０３は不純物を含む多結晶シリコン層、１０４は多結晶
シリコン層、１０５はソース領域、１０６はドレイン領
域、１０７はゲート絶縁膜、１０８はゲート電極、１０
９は二酸化硅素膜、１１０はソース電極、１１１はドレ
イン電極、１１２はパフシベーシ３ン膜である。101 is a transparent insulator substrate, 102 is silicon dioxide II, 1
03 is a polycrystalline silicon layer containing impurities, 104 is a polycrystalline silicon layer, 105 is a source region, 106 is a drain region, 107 is a gate insulating film, 108 is a gate electrode, 10
9 is a silicon dioxide film, 110 is a source electrode, 111 is a drain electrode, and 112 is a puffed substrate film.
以下、詳細に説明する。This will be explained in detail below.
まず透明絶縁体基板１０１、例えば石英ガラス基板上に
、二酸化硅素膜からなる絶縁膜１０２を通常の常圧気相
良法によって形成後、窒素雰囲気で熱処理する。First, an insulating film 102 made of a silicon dioxide film is formed on a transparent insulating substrate 101, for example, a quartz glass substrate, by a normal atmospheric pressure vapor deposition method, and then heat-treated in a nitrogen atmosphere.
そして、二酸化硅素１１１０２全面を覆って、不純物を
含む多結晶シリコンｍ１０３を形成する。Then, polycrystalline silicon m103 containing impurities is formed to cover the entire surface of silicon dioxide 11102.
不純物としては燐ＣＰ）が適当である。多結晶シリコン
層１０３は例えばモノシラ７（ＳｉＨａ）を減圧下で熱
分解して形成される。不純物を含んだ多結晶シリコン層
１０３を通常フォトエツチング法によって島状にバター
ニングする。As the impurity, phosphorus (CP) is suitable. The polycrystalline silicon layer 103 is formed, for example, by thermally decomposing monosilica 7 (SiHa) under reduced pressure. The impurity-containing polycrystalline silicon layer 103 is patterned into island shapes by a normal photoetching method.
次に、二酸化硅素ａ１０２及び不純物を含む多結晶シリ
コン層１０３の表面全体に多結晶シリコン層１０４を形
成する。多結晶シリコン履１０４の形成は前記多結晶シ
リコ／層１０３と同様に、モノシランを減圧下で熱分解
する気相成長法により行なわれ、膜形成時の温度は６０
０℃前後が適当である０次に、多結晶シリコン層１０４
は、フオドエツチング法により、素子として必要な部分
を残してエツチングされる。ここで、多結晶シリコン届
１０４のエツチング液としては、硝酸−弗酸系エツチン
グ液が用いられる。Next, a polycrystalline silicon layer 104 is formed over the entire surface of the polycrystalline silicon layer 103 containing silicon dioxide a102 and impurities. Similar to the polycrystalline silicon/layer 103, the polycrystalline silicon layer 104 is formed by a vapor phase growth method in which monosilane is thermally decomposed under reduced pressure, and the temperature during film formation is 60°C.
The polycrystalline silicon layer 104 is formed at a temperature of approximately 0° C.
is etched by a photo-etching method, leaving only the parts necessary for the element. Here, as the etching solution for the polycrystalline silicon report 104, a nitric acid-hydrofluoric acid based etching solution is used.
その後、ソース領域１０５、ドレイン電極１０６の形成
及びゲート絶縁膜１０７の形成のための熱処理、例えば
ウェット酸化がなされる。このウェット酸化により、多
結晶シリコン層１０４の表面にはゲート絶縁膜としての
二酸化硅素膜１０７が形成される。しかも不純物を含む
多結晶シリコン層１０３中より、多結晶シリコン層１０
４へ不純物が熱拡散され、ソース領域１０５及びドレイ
ン領域１０６が形成される。Thereafter, heat treatment, such as wet oxidation, is performed to form the source region 105, the drain electrode 106, and the gate insulating film 107. This wet oxidation forms a silicon dioxide film 107 as a gate insulating film on the surface of the polycrystalline silicon layer 104. In addition, the polycrystalline silicon layer 10 from the polycrystalline silicon layer 103 containing impurities
Impurities are thermally diffused into 4 to form a source region 105 and a drain region 106.
次に、二酸化硅素膜１０７の全表面に多結晶シリコン層
１０８が形成される。多結晶シリコン層１０８の形成に
は前述の如きモノシランの熱分解法が適用される。そし
て、この多結晶シリコン層１０８に燐（Ｐ）を熱拡散し
て比抵抗を下げる。Next, a polycrystalline silicon layer 108 is formed on the entire surface of the silicon dioxide film 107. To form the polycrystalline silicon layer 108, the monosilane thermal decomposition method described above is applied. Then, phosphorus (P) is thermally diffused into this polycrystalline silicon layer 108 to lower the specific resistance.
その後、多結晶シリコン５１０８は、フォト・エツチン
グ法により、必要な部分を残して他の部分が除去され、
残された多結晶シリコンはゲートｆｆ電極１０ｇとして
用られる。Thereafter, the polycrystalline silicon 5108 is removed by photo-etching, leaving only the necessary portions.
The remaining polycrystalline silicon is used as the gate ff electrode 10g.
次に、ゲート電極１０８を覆って、全面に二酸化硅素膜
からなる絶縁膜を前述の常圧気相成長法により形成する
。Next, an insulating film made of a silicon dioxide film is formed over the entire surface, covering the gate electrode 108, by the above-mentioned normal pressure vapor deposition method.
それから、二酸化硅素１ｉ１０７及び二酸化硅素膜に孔
をフォト・エツチング法により形成し、透明Ｓ電膜をス
パッタにより孔を含んで被着させ、不要部分を選択的に
除去してドレイン電極１１１を形成する。同様に、アル
ミニウムをスパッタにより孔を含んで被着させ、不要部
分を選択的に除去してソース電極１１０を形成する。そ
して、外部雰囲気からの汚染を防止するため、二酸化硅
素からなるパッシベーション１１１１２をスパッタによ
り形成する。Then, holes are formed in the silicon dioxide 1i107 and the silicon dioxide film by photo-etching, a transparent S conductive film is deposited including the holes by sputtering, and unnecessary portions are selectively removed to form the drain electrode 111. . Similarly, aluminum is deposited including holes by sputtering, and unnecessary portions are selectively removed to form the source electrode 110. Then, in order to prevent contamination from the external atmosphere, passivation 11112 made of silicon dioxide is formed by sputtering.
以上の工程を経て、電界効果型薄膜トランジスタの素子
が形成される。ゲート電極としては前述の多結晶シリコ
ンに限らず、モリブデン、タングステン等の高融点金属
及びその硅化物、つまりンリサイド等も使用可能である
。また、ゲート酸化膜はウェット酸化に限らず、ドライ
酸化等でも可能である。Through the above steps, a field effect thin film transistor element is formed. The gate electrode is not limited to the above-mentioned polycrystalline silicon, but also high melting point metals such as molybdenum and tungsten, and their silicides, ie, silicides, etc. can be used. Further, the gate oxide film is not limited to wet oxidation, but may also be formed by dry oxidation.
以上述べたように本発明によれば、予め島状に形成した
不純物を含む、多結晶シーリコン層をソースドレイン領
域形成のための、拡散源とすることができ、さらにコン
タクトホール下の多結晶シリコン層の膜厚が、ある程度
厚くできることから、コンタクト晦エツチングの時間に
、余裕をとることができる。これにより、コンタクトの
正確さが増し、素子の信頼性を向上することができる。As described above, according to the present invention, the polycrystalline silicon layer containing impurities formed in an island shape in advance can be used as a diffusion source for forming the source/drain region, and the polycrystalline silicon layer under the contact hole can be used as a diffusion source. Since the thickness of the layer can be made thicker to some extent, it is possible to take more time for contact etching. This increases the accuracy of the contact and improves the reliability of the device.
また、不純物を含む多結晶シリコン層を拡散源とするこ
とから、従来のゲート酸化膜に、イオン打ち込み等のた
めの窓を明ける工程が省略され、しかもゲート酸化とソ
ース領域、ドレイン領域形成のための熱拡散という、従
来、別々の熱処理工程を同時に行なうことができる。こ
のように、工程を簡易化できるという効果もをする。In addition, since the polycrystalline silicon layer containing impurities is used as the diffusion source, the conventional process of opening a window for ion implantation in the gate oxide film is omitted, and in addition, it is possible to eliminate the process of opening a window in the gate oxide film for ion implantation, etc. The conventionally separate heat treatment steps of thermal diffusion can be performed simultaneously. In this way, it also has the effect of simplifying the process.
第１５ＩＪは、本発明の実施例による半導体ＨＩの断面
図である。
第２図は、従来の半導体装置の構造を示す断面図である
。
１０１・・・透明絶縁体基板（石英）
１０２・・・二酸化硅素膜
１０３・・・不純物を含む多結晶シリコン層１０４・・
・多結晶シリコン層
１０５・・・ソース領域
１０６・・・トンイン領域
１０７・・・ゲート絶縁膜
１０８・・・ゲート電極
１０９・・・二酸化硅素膜
１１０・・・ソース電極（Ａ１）
１１１・・・ドレイン電極（Ｉ Ｔｏ）１１２・・・パ
ッシベーション膜
２０１・・・石英ガラス
２０２・・・二酸化硅素膜
２０３・・・多結晶シリコン層
２０４・・・ゲート酸化膜
２０５・・・ゲート電極
２０６・・・ソース領域
２０７・・・ドレイン領域
２０８・・・二酸化硅素膜
２０９・・・ドレイン電極
２１０・・・ソース電極
２１１・・・パフシベーシ讐ン膜
以 上
出願人 セイコーエプソン株式会社
Ｍ１図
粥 ２図15th IJ is a cross-sectional view of a semiconductor HI according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing the structure of a conventional semiconductor device. 101...Transparent insulator substrate (quartz) 102...Silicon dioxide film 103...Polycrystalline silicon layer 104 containing impurities...
- Polycrystalline silicon layer 105...source region 106...ton-in region 107...gate insulating film 108...gate electrode 109...silicon dioxide film 110...source electrode (A1) 111... Drain electrode (I To) 112... Passivation film 201... Quartz glass 202... Silicon dioxide film 203... Polycrystalline silicon layer 204... Gate oxide film 205... Gate electrode 206... Source region 207...Drain region 208...Silicon dioxide film 209...Drain electrode 210...Source electrode 211...Puffed silicon dioxide film Applicant Seiko Epson Corporation M1 Figure 2 Figure
Claims (1)
前記第１の酸化膜表面に不純物を含んだ第１の多結晶シ
リコン層を形成する工程、前記第１の多結晶シリコン層
を形成する工程、前記第１の多結晶シリコン層を、島状
にパターニングする工程、前記第１の多結晶シリコン層
表面及び前記開孔部を覆って不純物を含まない第２の多
結晶シリコン層を形成する工程、熱処理により前記第１
の多結晶シリコン層から前記第２の多結晶シリコン層へ
不純物を拡散して、ソース領域、ドレイン領域を形成す
ると共に、前記第２の結晶シリコン層表面に第２の酸化
膜を形成する工程、前記第２の酸化膜上にゲート電極を
形成する工程からなることを特徴とする半導体装置の製
造方法。forming a first oxide film on the surface of the transparent insulator substrate;
forming a first polycrystalline silicon layer containing impurities on the surface of the first oxide film; forming the first polycrystalline silicon layer; forming the first polycrystalline silicon layer in an island shape; a step of patterning, a step of forming a second polycrystalline silicon layer containing no impurities covering the surface of the first polycrystalline silicon layer and the opening, and a step of heat-treating the first polycrystalline silicon layer.
a step of diffusing impurities from the polycrystalline silicon layer to the second polycrystalline silicon layer to form a source region and a drain region, and forming a second oxide film on the surface of the second crystalline silicon layer; A method for manufacturing a semiconductor device, comprising the step of forming a gate electrode on the second oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25885387A JPH01100971A (en) | 1987-10-14 | 1987-10-14 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25885387A JPH01100971A (en) | 1987-10-14 | 1987-10-14 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01100971A true JPH01100971A (en) | 1989-04-19 |
Family
ID=17325945
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25885387A Pending JPH01100971A (en) | 1987-10-14 | 1987-10-14 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01100971A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07183520A (en) * | 1993-12-24 | 1995-07-21 | Nec Corp | Thin film transistor |
-
1987
- 1987-10-14 JP JP25885387A patent/JPH01100971A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07183520A (en) * | 1993-12-24 | 1995-07-21 | Nec Corp | Thin film transistor |
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