JPS58118158A - 電界効果トランジスタの形成方法 - Google Patents

電界効果トランジスタの形成方法

Info

Publication number
JPS58118158A
JPS58118158A JP57183016A JP18301682A JPS58118158A JP S58118158 A JPS58118158 A JP S58118158A JP 57183016 A JP57183016 A JP 57183016A JP 18301682 A JP18301682 A JP 18301682A JP S58118158 A JPS58118158 A JP S58118158A
Authority
JP
Japan
Prior art keywords
layer
forming
field effect
drain
doped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57183016A
Other languages
English (en)
Japanese (ja)
Other versions
JPH045265B2 (enExample
Inventor
ヤコブ・ライズマン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS58118158A publication Critical patent/JPS58118158A/ja
Publication of JPH045265B2 publication Critical patent/JPH045265B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0273—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming final gates or dummy gates after forming source and drain electrodes, e.g. contact first technology
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1408—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1408—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
    • H10P32/141—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers the applied layer comprising oxides only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1408—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
    • H10P32/1414—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
JP57183016A 1981-12-30 1982-10-20 電界効果トランジスタの形成方法 Granted JPS58118158A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/335,892 US4419810A (en) 1981-12-30 1981-12-30 Self-aligned field effect transistor process
US335892 1994-11-08

Publications (2)

Publication Number Publication Date
JPS58118158A true JPS58118158A (ja) 1983-07-14
JPH045265B2 JPH045265B2 (enExample) 1992-01-30

Family

ID=23313657

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57183016A Granted JPS58118158A (ja) 1981-12-30 1982-10-20 電界効果トランジスタの形成方法

Country Status (4)

Country Link
US (1) US4419810A (enExample)
EP (1) EP0083785B1 (enExample)
JP (1) JPS58118158A (enExample)
DE (1) DE3277342D1 (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6370572A (ja) * 1986-09-12 1988-03-30 Nec Corp Ｍｏｓ電界効果トランジスタの製造方法
JPS6451665A (en) * 1987-08-24 1989-02-27 Hitachi Ltd Semiconductor device
JPH02312244A (ja) * 1989-05-26 1990-12-27 Mitsubishi Electric Corp 半導体装置の製造方法

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US4521952A (en) * 1982-12-02 1985-06-11 International Business Machines Corporation Method of making integrated circuits using metal silicide contacts
FR2549293B1 (fr) * 1983-07-13 1986-10-10 Silicium Semiconducteur Ssc Transistor bipolaire haute frequence et son procede de fabrication
JPS6063961A (ja) * 1983-08-30 1985-04-12 Fujitsu Ltd 半導体装置の製造方法
US4532697A (en) * 1983-12-02 1985-08-06 At&T Bell Laboratories Silicon gigabit metal-oxide-semiconductor device processing
US4546535A (en) * 1983-12-12 1985-10-15 International Business Machines Corporation Method of making submicron FET structure
US4636834A (en) * 1983-12-12 1987-01-13 International Business Machines Corporation Submicron FET structure and method of making
US4584761A (en) * 1984-05-15 1986-04-29 Digital Equipment Corporation Integrated circuit chip processing techniques and integrated chip produced thereby
US5098854A (en) * 1984-07-09 1992-03-24 National Semiconductor Corporation Process for forming self-aligned silicide base contact for bipolar transistor
US4641420A (en) * 1984-08-30 1987-02-10 At&T Bell Laboratories Metalization process for headless contact using deposited smoothing material
US4666557A (en) * 1984-12-10 1987-05-19 Ncr Corporation Method for forming channel stops in vertical semiconductor surfaces
US4612258A (en) * 1984-12-21 1986-09-16 Zilog, Inc. Method for thermally oxidizing polycide substrates in a dry oxygen environment and semiconductor circuit structures produced thereby
US5227316A (en) * 1985-01-22 1993-07-13 National Semiconductor Corporation Method of forming self aligned extended base contact for a bipolar transistor having reduced cell size
KR890004962B1 (ko) * 1985-02-08 1989-12-02 가부시끼가이샤 도오시바 반도체장치 및 그 제조방법
KR900000065B1 (ko) * 1985-08-13 1990-01-19 가부시끼가이샤 도오시바 독출전용 반도체기억장치와 그 제조방법
GB8527062D0 (en) * 1985-11-02 1985-12-04 Plessey Co Plc Mos transistor manufacture
US4752589A (en) * 1985-12-17 1988-06-21 Siemens Aktiengesellschaft Process for the production of bipolar transistors and complementary MOS transistors on a common silicon substrate
EP0227971A1 (de) * 1985-12-17 1987-07-08 Siemens Aktiengesellschaft MOS-Transistor mit kurzer Gatelänge für hochintegrierte Schaltungen und Verfahren zu seiner Herstellung
US4735911A (en) * 1985-12-17 1988-04-05 Siemens Aktiengesellschaft Process for the simultaneous production of bipolar and complementary MOS transistors on a common silicon substrate
US4737472A (en) * 1985-12-17 1988-04-12 Siemens Aktiengesellschaft Process for the simultaneous production of self-aligned bipolar transistors and complementary MOS transistors on a common silicon substrate
US4701423A (en) * 1985-12-20 1987-10-20 Ncr Corporation Totally self-aligned CMOS process
US4707457A (en) * 1986-04-03 1987-11-17 Advanced Micro Devices, Inc. Method for making improved contact for integrated circuit structure
US4689869A (en) * 1986-04-07 1987-09-01 International Business Machines Corporation Fabrication of insulated gate gallium arsenide FET with self-aligned source/drain and submicron channel length
US4677736A (en) * 1986-04-17 1987-07-07 General Electric Company Self-aligned inlay transistor with or without source and drain self-aligned metallization extensions
WO1987006764A1 (en) * 1986-04-23 1987-11-05 American Telephone & Telegraph Company Process for manufacturing semiconductor devices
US4974046A (en) * 1986-07-02 1990-11-27 National Seimconductor Corporation Bipolar transistor with polysilicon stringer base contact
US5063168A (en) * 1986-07-02 1991-11-05 National Semiconductor Corporation Process for making bipolar transistor with polysilicon stringer base contact
US4707218A (en) * 1986-10-28 1987-11-17 International Business Machines Corporation Lithographic image size reduction
US4885617A (en) * 1986-11-18 1989-12-05 Siemens Aktiengesellschaft Metal-oxide semiconductor (MOS) field effect transistor having extremely shallow source/drain zones and silicide terminal zones, and a process for producing the transistor circuit
US4939154A (en) * 1987-03-25 1990-07-03 Seiko Instruments Inc. Method of fabricating an insulated gate semiconductor device having a self-aligned gate
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US5285094A (en) * 1987-08-24 1994-02-08 Hitachi, Ltd. Vertical insulated gate semiconductor device with less influence from the parasitic bipolar effect
US5179034A (en) * 1987-08-24 1993-01-12 Hitachi, Ltd. Method for fabricating insulated gate semiconductor device
US4786609A (en) * 1987-10-05 1988-11-22 North American Philips Corporation, Signetics Division Method of fabricating field-effect transistor utilizing improved gate sidewall spacers
US4907048A (en) * 1987-11-23 1990-03-06 Xerox Corporation Double implanted LDD transistor self-aligned with gate
US5272100A (en) * 1988-09-08 1993-12-21 Mitsubishi Denki Kabushiki Kaisha Field effect transistor with T-shaped gate electrode and manufacturing method therefor
US5543646A (en) * 1988-09-08 1996-08-06 Mitsubishi Denki Kabushiki Kaisha Field effect transistor with a shaped gate electrode
US5089863A (en) * 1988-09-08 1992-02-18 Mitsubishi Denki Kabushiki Kaisha Field effect transistor with T-shaped gate electrode
US5175118A (en) * 1988-09-20 1992-12-29 Mitsubishi Denki Kabushiki Kaisha Multiple layer electrode structure for semiconductor device and method of manufacturing thereof
JP2508818B2 (ja) * 1988-10-03 1996-06-19 三菱電機株式会社 半導体装置の製造方法
US4945070A (en) * 1989-01-24 1990-07-31 Harris Corporation Method of making cmos with shallow source and drain junctions
US5223914A (en) * 1989-04-28 1993-06-29 International Business Machines Corporation Follow-up system for etch process monitoring
EP0394597A1 (en) * 1989-04-28 1990-10-31 International Business Machines Corporation Follow-up System for Monitoring the Etching Process in an RIE Equipment and its Application to Producing High-resolution and Reproducible Patterns
US5238857A (en) * 1989-05-20 1993-08-24 Fujitsu Limited Method of fabricating a metal-oxide-semiconductor device having a semiconductor on insulator (SOI) structure
US5208471A (en) * 1989-06-12 1993-05-04 Hitachi, Ltd. Semiconductor device and manufacturing method therefor
KR940005729B1 (ko) * 1989-06-13 1994-06-23 삼성전자 주식회사 디램셀의 제조방법 및 구조
JP2746289B2 (ja) * 1989-09-09 1998-05-06 忠弘 大見 素子の作製方法並びに半導体素子およびその作製方法
US5012306A (en) * 1989-09-22 1991-04-30 Board Of Regents, The University Of Texas System Hot-carrier suppressed sub-micron MISFET device
US5093275A (en) * 1989-09-22 1992-03-03 The Board Of Regents, The University Of Texas System Method for forming hot-carrier suppressed sub-micron MISFET device
US5116778A (en) * 1990-02-05 1992-05-26 Advanced Micro Devices, Inc. Dopant sources for cmos device
US5175606A (en) * 1990-08-27 1992-12-29 Taiwan Semiconductor Manufacturing Company Reverse self-aligned BiMOS transistor integrated circuit
US5235204A (en) * 1990-08-27 1993-08-10 Taiwan Semiconductor Manufacturing Company Reverse self-aligned transistor integrated circuit
US5071780A (en) * 1990-08-27 1991-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Reverse self-aligned transistor integrated circuit
US5028557A (en) * 1990-08-27 1991-07-02 Taiwan Semiconductor Manufacturing Co., Ltd. Method of making a reverse self-aligned BIMOS transistor integrated circuit
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JPH0574806A (ja) * 1991-09-13 1993-03-26 Hitachi Ltd 半導体装置及びその製造方法
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US5466615A (en) * 1993-08-19 1995-11-14 Taiwan Semiconductor Manufacturing Company Ltd. Silicon damage free process for double poly emitter and reverse MOS in BiCMOS application
US5409853A (en) * 1994-05-20 1995-04-25 International Business Machines Corporation Process of making silicided contacts for semiconductor devices
US5464782A (en) * 1994-07-05 1995-11-07 Industrial Technology Research Institute Method to ensure isolation between source-drain and gate electrode using self aligned silicidation
US6608205B1 (en) 1995-09-08 2003-08-19 University Of Puerto Rico Organic crystalline films for optical applications and related methods of fabrication
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JPS5567166A (en) * 1978-11-15 1980-05-21 Fujitsu Ltd Preparation of mos type semiconductor device

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Publication number Priority date Publication date Assignee Title
JPS6370572A (ja) * 1986-09-12 1988-03-30 Nec Corp Ｍｏｓ電界効果トランジスタの製造方法
JPS6451665A (en) * 1987-08-24 1989-02-27 Hitachi Ltd Semiconductor device
JPH02312244A (ja) * 1989-05-26 1990-12-27 Mitsubishi Electric Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
US4419810A (en) 1983-12-13
EP0083785A2 (en) 1983-07-20
JPH045265B2 (enExample) 1992-01-30
EP0083785B1 (en) 1987-09-16
DE3277342D1 (en) 1987-10-22
EP0083785A3 (en) 1985-01-23

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