JPS58102540A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To facilitate the circuit design and stabilize the operation, by allowing the potential to be taken from a semiconductor substrate. CONSTITUTION:The numeral 11 represents a P type semiconductor substrate, and the numeral 12 an N<+> buried layer, and this N<+> buried layer region is formed over the entire island region wherein a transistor is formed. Next, after an N type epitaxial layer 14 is etched in a fixed amount, an oxide film 15 is formed by a selective oxidation. Thereafter, a collector wall 16 to decrease series resistance is formed. Then, in the island region wherein a transistor is formed, a base layer 17 is formed down to the depth of approx. 0.45mum, and, in the island region wherein a P type diffused region 13' is formed, a P type diffused region 17' is formed down to the depth of 0.45mum in the same process as the base layer 17' to take the potential of the semiconductor substrate. Thus, the P type diffused region 17' is joined to the P type diffused region 13' and the P type semiconductor substrate 11 in continuity, accordingly the potential of the P type semiconductor substrate 11 can be taken from the surface.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and in particular to an insulation-separated semiconductor integrated circuit.In conventional insulation-separated semiconductor integrated circuits, the potential of the semiconductor substrate is normally taken from the back side.
The present invention makes it possible to remove the knife from the surface, making it possible to easily design the circuit and stabilize the operation.

In recent years, semiconductor integrated circuits have been required to have higher density and higher speed, and research on semiconductor integrated circuits using insulation isolation has been actively conducted. In general, bipolar semiconductor integrated circuits mainly use vertical σNP)iTr (transistors), so when configuring the circuit, the semiconductor substrate is used at the lowest potential. Normally, the potential of the semiconductor substrate is lowered to earth, and it is widely used as emitter grounding.

FIG. 1 shows how to take a semiconductor substrate potential in a conventional semiconductor integrated circuit with insulation isolation. In FIG. 1, 1 is, for example, a p-type semiconductor substrate, 2 is an n+ buried layer, and 3 is a p-type diffusion region for a channel stopper. It has the effect of preventing leakage. 4 is an n-type epitaxial layer, and 6 is an isolation oxide film, which insulates and isolates the island region. 6 is a collector wall for lowering the collector series resistance, 7 is a base layer of the transistor, 8 is an emitter, 9 is an oxide film for opening a contact portion, and 1o is a mu1 wiring.

As is clear from FIG. 1, in the conventional semiconductor integrated circuit with insulation isolation, in order to take the potential of the semiconductor substrate from the surface,
A p-type diffusion region that connects the p-type semiconductor substrate to the surface is not formed. Therefore, the potential of the semiconductor substrate usually had to be taken from the back side. When attempting to take the potential of a p-type semiconductor substrate from the surface, there is a p
Unless a new mold diffusion region is formed, the process will be complicated and the number of steps will increase significantly. In other words, insulation isolation refers to the diffusion region that is formed from the surface to the semiconductor substrate in order to separate the islands in pn junction isolation.
Since this is an isolation method in which an insulator is used, the structure inevitably does not include a diffusion region that reaches the semiconductor substrate from the surface. Therefore, in conventional insulation isolation, the potential of the semiconductor substrate had to be taken from the back side.

Having to take the potential of the p-type semiconductor substrate from the back side causes a serious problem in circuit design and often causes malfunction of the circuit. Generally, when mounting a chip with a semiconductor integrated circuit into a package,
It is bonded to the back surface of the semiconductor substrate using a Mu-Si eutectic alloy. Therefore, the potential of the semiconductor substrate can be taken from the back side. However, when the chip is bonded to the package, the contact on the back side is very poor, and the contact resistance may become abnormally large. For this reason, when connecting a certain circuit section to a semiconductor substrate in circuit design,
It became necessary to connect the package with the chip glued to the necessary locations. At this time, if the contact between the chip and the package is poor, the contact resistance will increase, so the current will not flow through the contact area but through the semiconductor substrate, causing a voltage drop instead of the semiconductor substrate being at the same potential. become. In this case, the potential of the semiconductor substrate in the semiconductor integrated circuit will be different, which may cause malfunction of the circuit. Therefore, in circuit design, it becomes necessary to wire a certain specific circuit section and the semiconductor substrate over a short distance. In addition, latch-up may occur due to the influence of parasitic transistors, etc., so it is essential in general-purpose circuit design to take the potential of the semiconductor substrate from the surface.

In consideration of these problems, the present invention overcomes the drawback that conventional insulation isolation cannot take the potential of the semiconductor substrate from the surface, makes it possible to take the potential of the semiconductor substrate from the surface, and improves circuit design. An object of the present invention is to provide a semiconductor integrated circuit that operates easily and accurately without malfunction.

The present invention will be described in detail below with reference to FIG.

FIGS. 2(m) to 2(jc) schematically show the manufacturing process of a bipolar semiconductor integrated circuit according to an embodiment of the present invention.

In FIG. 2(A), 11 indicates a p-type semiconductor substrate. In (Mu), 12 is an n+ buried layer, and here MuS.

It is formed by diffusion using impurities such as sb.

This n+ buried layer region is formed over the entire island region where the transistor is formed. Reference numeral 13 and 13' denote p-type diffusion regions, which are formed by B ion implantation. 13 is formed to surround the n+ buried region 12 forming the transistor section, and is used as a channel stopper to prevent leakage between the island regions due to the n-type inversion layer generated when forming the oxide film for insulation isolation. There is. The region 13'' is formed in the same process as the region 13 over the entire island region in order to take the potential of the p-type semiconductor substrate 11 from the surface.
Form a mold epitaxial layer 14 with a thickness of 1.2 μm (■).

Next, in FIG. 2(C), after etching the n-type epitaxial layer 14 by a predetermined amount, selective oxidation is performed to 1.5
μ theory A thick oxide film 15 is formed. When high-pressure oxidation is used, at a temperature of 1000°C and 6.6 atm, 1
．． An oxide film 16 of 6 μm is formed. At this time, if the n+ buried region 12 is made of Mu ss and the P-type diffusion regions 13 and 131 are made of B, the diffusion coefficient of Mu 8 at 1000° C. is approximately 2×10 15 CI! /The diffusion coefficient of B is approximately 1.2×1o14C4/J! At c,
The diffusion coefficient of B is about 6 times that of Mu S. Therefore, in the selective oxidation process, the lift of the n+ buried region 12 was approximately 0.2 μm, and the lift of the p-type diffusion region 131 was approximately 0.8 μm. During this selective oxidation, the region 131 was greatly diffused. That's why.

After that, collector wall 1 to lower the series resistance.
form 6. It is desirable that this collector wall is formed by diffusion, etc., of p having a larger diffusion coefficient than those of S and B.

Thereafter, a base layer 17 is formed to a depth of approximately 0.46 μm in the island region where the transistor is to be formed. and,
In order to obtain the potential of the semiconductor substrate, a p-type diffusion region 17' is formed to a depth of 0.46 μl in the same step as the base layer 17 in the island region where the p-type diffusion region 13f is formed. Now, as shown in FIG. 2, the p-type diffusion region 17', the p-type diffusion region 13', and the p-type semiconductor substrate 11 are continuously connected.
This makes it possible to take the potential of the p-type semiconductor substrate 11 from the surface. Note that in order to lower the transistor's paste resistance and improve its high frequency characteristics, a highly concentrated p''! diffused region is often formed as a graft paste. It can also be formed in the same process as the formed p-type diffusion region 171.After that, the n+ type emitter 8 is formed, and the insulating film 19 on the surface is selectively removed to form the M1 wiring 20, 211, 2.
21 and 23 are formed to form the semiconductor integrated circuit shown in FIG. Tr is a transistor portion, V is a semiconductor substrate potential portion, and terminal S of the multilayer wiring 23 has a substrate potential.

As described above, as shown in FIG. 2, by forming a p-type diffusion region, which was used as a channel stopper in conventional insulation isolation, in a predetermined island region, subsequent epitaxial growth and selection are possible. In the step of forming an insulating isolation oxide film by oxidation, p is added to the n-type epitaxial layer.
It takes advantage of the fact that the shape diffusion area is raised greatly. Note that although the n+ buried region is formed in the entire island region where the transistor is formed, due to the difference in diffusion coefficient, the rise of the n+ buried region is small and does not affect the characteristics of the transistor much. By connecting this raised p-type diffusion region to the p-type diffusion region formed at the same time as the space region, the p-type semiconductor substrate and the p-type diffusion region are connected to the surface, and the potential of the semiconductor substrate can be taken from the surface. becomes possible. Therefore, the restriction that the potential of the semiconductor substrate is taken from the back surface as in conventional insulation isolation is removed, and circuit design can be made extremely easy. In addition, since the potential of the semiconductor substrate can be taken at any position in the semiconductor integrated circuit, it is possible to eliminate voltage drop in the semiconductor substrate.
It also has the effect of minimizing the effects of latch-up and the like caused by parasitic transistors, thereby preventing circuit malfunctions.

As described above, the present invention makes it possible to take the potential of the semiconductor five-piece substrate from the surface in insulation isolation, and facilitates circuit design.
Moreover, it greatly contributes to the production of accurate semiconductor integrated circuits without malfunctions, and is of extremely high industrial value.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part of a semiconductor integrated circuit using conventional insulation isolation, and FIGS. be. 11...p-type semiconductor substrate, 12...n
+Buried region, 13.13'...p-type diffusion region, 16...isolation oxide film, 17.17'...
- P-type diffusion region for base layer formation.

Claims (2)

[Claims] (1) A semiconductor layer of one conductivity type formed on a semiconductor substrate of the other conductivity type, and a first semiconductor layer separated from each other by an isolation insulating film selectively formed in the semiconductor layer. a second island region; a semiconductor element formed in the first island region;
a region of the one conductivity type formed in the second island region and reaching the semiconductor substrate from the surface of the second island region;
A semiconductor device comprising: a semiconductor substrate electrode formed on this region; (2) selectively forming a first region of the other conductivity type opposite to this substrate on a semiconductor substrate of one conductivity type; forming a second region of conductivity type; growing a semiconductor layer of the other conductivity type on the substrate; and growing a semiconductor layer of the second conductivity type from the surface of the semiconductor layer. An insulating film is selectively formed so as to reach the third region, and an insulating film is formed below the first region. A first region having a second region therebetween. forming a second island region, forming a semiconductor element in the first island region, and forming a third semiconductor element of the one conductivity type in contact with the second island region in the second island region;
A method for manufacturing a semiconductor device, comprising the steps of: forming a region; and forming the semiconductor substrate electrode on the third region.