JPS5870550A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device with high integration density not comprising parasitic elements by adjacently forming the P and N type regions on the Si substrate through the SiO2 film, sequentially forming the P layer and N layer at the surface except for a part of both regions and by extending conductive layers from the P type first region, second and fourth regions. CONSTITUTION:The O ion is implanted to the Si substrate with 0.1cm or less and the surface is then annealed in order to form the SiO2 thin layer 10. The P epitaxial layer 11 is then formed thereover and it is covered with the SiO2 layer 16. A window is opened on the film 16 and the N layer 12 is then formed in such a depth as reaching the layer 10. The layer other than the N layers 11, 11', 12 is converted to the SiO2 using the Si3N4 mask. Thereafter, the SiO2, Si3N4 on the quadrilateral A-D and the p epitaxial layer 13 is formed on such quardrilateral while the poly Si 22 in the periphery thereof. Moreover, the N layer 14 is formed on the layer 13 and the poly Si 23 on the layer 22, the poly-Si 23, 22 are mainly etched by the KOH liquid, thereby the cross-section of layers 13-15 becomes a trapozoid. Then SiO216'' is deposited on the surface of layers 13-15 and the A electrodes 17-19 are provided thereto. This transistor is surrounded by the SiO2 and shows a very low parasitic capacitance. In addition, a collector series resistance is small and there is no additional formation of collector lead out layer. Thereby, integration density can be improved drastically.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a semiconductor device, particularly to the structure of insulation in a semiconductor integrated circuit.

Insulation isolation using a PN junction, which is also widely used in the past, is not only limited by the frequency characteristic K11j due to the presence of junction capacitance between the element region and the semiconductor substrate, but also is used for PNP transistors, PNPN elements (thyristor elements), etc. This creates parasitic elements and causes various problems such as latch-up. Therefore, we decided to use insulator isolation by wrapping the surrounding area with 5iOse insulator, and air gap isolation (
Although methods such as the beam lead method have been proposed, there are various manufacturing difficulties and it is still difficult to say that they can be used inexpensively in mass production processes.

FIG. 1 shows a schematic cross section of a part of a semiconductor device using a conventional beam lead method. In this beam lead method, instead of the M wiring, a M-U beam-shaped lead is formed, and the individual elements that make up the integrated circuit are mutually supported by these leads. The Seki08i crystal of the device can be etched, and insulation separation can be achieved by voids. However, because the manufacturing method is difficult and expensive, this gap-based isolation is rarely used. This method is only used as a technology for connecting the case and the integrated circuit chip in hybrid ICs.

To explain a little more about FIG. 1, the diffusion for manufacturing the device may be the same as for normal transistor manufacturing.

The starting material is a silicon substrate 1 heavily doped with null impurities such as Sb and S. An N-type epitaxial layer 2 is grown on the substrate, and a P-type impurity is diffused to form a space region 3. Next, N-type impurities (P t A, etc.) are diffused at a high concentration to form the emitter 4 and the collector electrode extraction region 4'.
to form.

Then, 5-inch Sf selective openings and platinum silicide are formed to provide each contact portion, and platinum and gold are deposited on the wafer surface by vapor deposition or plating to form beam leads 6 and 7.8 k. Using these beam leads as supports, the 8
1 crystal is removed and the area around the element is 8ixN4 by KCVD method.
Or Stow's ms't-forming is used as a farm maintenance film. Beam leads 6, 7.8 are emitter, pace, and collector electrodes, respectively. Such a semiconductor element exhibits its power when used at a frequency of 100 MHz or higher, since the junction capacitance between the semiconductor substrate and the insulation isolation region is completely eliminated compared to the case of isolation using a PN junction. However, the beam lead formation process is complicated and expensive, and its subsequent handling is difficult, so it is rarely used.

An object of the present invention is to eliminate the above-mentioned drawbacks and provide a semiconductor device which is formed by very simple isolation of insulators, has no parasitic elements, has very small parasitic capacitance, and has high integration density. .

The semiconductor device of the present invention includes a semiconductor crystal thin layer surrounded by a dielectric thin layer on the surface of a semiconductor substrate via a dielectric thin film (for example, a 5-ins film), and the thin layer includes: - a first region of a conductivity type, a second region doped with an impurity of an opposite conductivity type to a high concentration so as to be adjacent to the first region; and a second region of the first region.

A third region of a conductive semiconductor crystal layer formed on the first and second regions except for the lead-out portion of the second region, and a semiconductor of an opposite conductivity type formed on the third region. a fourth region of the crystalline layer and said first region;

means for electrically connecting the second and fourth regions to the outside;
That is, openings are selectively formed in the insulating film on each region, and metal or polycrystalline semiconductor is bonded to each region through the openings to form electrodes for each region, and furthermore, electrodes for other elements are formed. It is formed by forming wiring.

The invention will now be explained in more detail with reference to one drawing.

FIG. 2 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention, and FIGS. be. The starting material is a silicon substrate 9 with a thickness of 250 to 500 μm,
The conductive material is suitable for both N type and pH, and the specific resistance is used when applying the potential of a part of the element to the substrate, or in order to lower the thermal resistance of the substrate as much as possible. Just use it. Subsequently, oxygen (or nitrogen) ions are implanted from the surface of the silicon substrate 9 with an implantation energy of 1s ojlceV.
Ion implantation is performed at a dose of 1.2×1G51 or more. Under these implantation conditions, the ions have an average range Rp=
It is driven mainly at positions above 3800A. The implanted 9 ion layer is then heat treated in an Ng gas atmosphere above 1000°C, and the implanted oxygen ions react with St to form a 5ins thin layer 1G.The silicon transition layer on the surface is heat treated. As a result, single crystallinity is restored (Figure 3 (a)).
.

After this, a single crystal silicon layer (0.1 to 0.01 Ω-a+) 11 with a thickness of 2 to S μmm OP ill is formed by epitaxial growth on the single crystal layer on the thin layer 10 of 81 (h). 1 g of 810m film on the surface (~5GGOA)
is deposited by thermal oxidation or CVD method (Fig. 3 (bl)). Next, the 810+ film 16' is selectively etched away, and N-type impurities (P, Muhatake, etc.) are deposited with high flkFitJs-2.
~5Ω/hole) and doped to reach 810sll [1G to form an N11l region 12t (Fig. 3(C))
.

Next, as shown in the plan view of FIG. 3(d), using the silicon nitride film as a mask, the surrounding single crystal layer tSiOz layer is oxidized so as to leave regions xt, tf, and tzt. Next, Figure 3 (
If the oxide film and nitride film on the quadrilaterals ■, ■, ■, and ■ in d) are removed and silicon is vapor-phase grown while doping with pH impurities (e.g., B), the quadrilaterals ■, ■, ■, and Above (2) is a P-type region 13 of single crystal silicon (specific resistance 0.
1 to 0.01 ohm and thickness of 1 to 5 .mu.m), but a polycrystalline silicon layer 22 is grown on the other regions of the film (FIG. 3(e)). The quadrilaterals ■, ■, ■, ■ are parts that become part of the transistor element. Furthermore, Nll impurities (e.g. p
hol.

When silicon is grown in vapor phase while being doped with t-type (Al, etc.), an N-type region 14 (specific resistance 0.5
~lsΩ-country, thickness 2 to 154 m), and a polycrystalline layer 23 is further grown on the polycrystalline silicon layer 22, respectively. Next, a high concentration of Nff1 impurity (Pil) is applied to the surface and sea surfaces.
= 1 to 10Ω/hole), a single crystal region 15 and a polycrystalline region 15' with high N-type impurity concentration are formed (third
Figure (f)).

Next, the polycrystalline region 2 layer 23 is coated with KOH liquid or HNOs.
(a small amount of HF) etc. and weave it away. In this case, polycrystalline portions are mainly removed due to the selectivity of the etching solution, and the etching end point can be easily found because the etching rate changes at the 8i0- film 16. Even for single crystal regions 13°14.15, the etching rate is approximately 1/1G compared to polycrystalline silicon, so the cross section of single crystal regions 13 and 14.15 is trapezoidal, as shown in Figure 3 (gl). becomes.

And single crystal regions 13, 14.1! Silicon oxide (or nitride) 16' is deposited on the surface of the region 11.
, 12.15 is provided with a round opening for electrode formation.

Metals such as AI and MQ are deposited and selectively removed to form wiring sections (Figure 2).

The NW region i &12' is an emitter extraction region of an NPN transistor. The Nll region 12' is Nll
The ff1 high concentration impurity region 12 has expanded to a region 13111 during subsequent heat treatment. pH range 13.11
is the pace and pace extraction region of the NPN transistor,
The N-type region 14.15 is the collector region of the NPN II transistor. Emitter region 12' and collector region 14
The distance between them is the pace width), and by adjusting this distance and the degree of impurity penetration of the NIOTS regions 1 &12', a desired current amplification factor can be obtained. Electrodes 17, 18.1
If 9' are formed as the emitter, paste, and collector electrodes of a transistor, respectively, the structure shown in FIG. 2 is obtained.

Since the transistor with this structure is entirely covered with an insulating film, the parasitic capacitance is extremely small and the transistor has excellent high frequency characteristics. Moreover, the electrodes in the collector region are different from the conventional example (Fig. 1), with emitter and pace electrodes 6 and 7.
Since the collector electrode is drawn out directly above the emitter and paste, rather than on the same plane as the emitter, the collector series resistance can be easily reduced. Further, since there is no need to separately provide a collector electrode lead-out area, the degree of integration can be greatly improved.

Resistance element 1-&! If it is desired to insert the electrode between the edge lines, as shown in FIG. 2, if a 20 ft electrode is provided, the electrode 18° 200 ft. (e) Pill thin layer 11 acts as a resistor. Next, if it is desired to insert a diode into the trout channel, as shown in FIG. 2, if an electrode 21 is provided, a diode formed by a PN junction between the regions 1r and tz can be used.

When viewed from the whole area of the above semiconductor device, it becomes as shown in FIG.

Next, as a 20th embodiment of the present invention, an improvement example of the first embodiment is shown in FIG. From the viewpoint of amplification factor, it is preferable not to have it, so as shown in Figure 5+1) and (b), a thin 810g (2 to 5μ-m) is placed at the boundary between the emitter region 1a and the pace region 11.
A region 22 is provided.

By providing the 51 oz region 22, the lateral capacitance between the engineer paces is eliminated and the frequency characteristics can be greatly improved. According to the present invention, the area of the effective emitter pace can be made infinitely small, so from this point of view, it is also possible to achieve high liquid volume, high integration, and also to obtain a sufficient current amplification rate with a small current, making it suitable for reducing power consumption. Nine semiconductor devices can be obtained.

The planar shape of the semiconductor device according to the present invention is shown in FIG.
) and explained using a round shape, but you are not limited to this and can also use a round shape,
It may have any shape, such as a polygon, and there are no restrictions. or,
Although the NPN type transistor has been described, a similar structure can be realized for a PNP II transistor by replacing N with Pt.

[Brief explanation of the drawing]

Fig. 1 is a schematic cross-sectional view of a nine-transistor section with air gap insulation and isolation using the conventional beam lead method, Fig. 2 is a schematic cross-sectional view of a semiconductor device according to the first embodiment of the present invention, and Fig. 3 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention.
(g) is a schematic cross-sectional view at each step of the process 1i for realizing the semiconductor device t-1i of the first embodiment of the present invention, and FIG. 4 is a diagram of the semiconductor device shown in FIG. 2 viewed from the surface. FIG. 5 (al is a schematic sectional view of the semiconductor device of the second embodiment of the present invention, and FIG. 5 (bl is a plan view of the horizontal plane 23 of FIG. 5). l... ...High concentration Nll region, 2...
・N-type epitaxial region, 3...Pal diffusion region, 4.4'...High concentration Nll diffusion region, 5
．． 5'...Dielectric thin film, 6,7.8...
・Platinum, gold electrode, 9... Semiconductor substrate, 10...
...Dielectric thin film, 11. ll'. 13... P temperature region, 1 &12'... High concentration N type region, 14... NW region 15...
...High concentration N-type region, 15'...High concentration N-type polycrystalline region, 16.16'...Dielectric thin film, 1
7, 18, 19, 20, 21.22... P-type polycrystalline region, 23... N-type polycrystalline region. Agent Patent Attorney Uchi * f H""j"f 1 fig. ]

Claims (1)

[Claims] a first region of the first conductive group formed on the surface of the semiconductor substrate via an insulating thin film and a second region of the second conductive type adjacent to the first region; a third region of the first conductivity type formed on the surface excluding a part of the second region; a fourth region of the second conductivity type formed on the third region of the scissors;
and a conductor layer led out from the second and fourth regions.