USRE26778E - Dielectric isolation for monolithic circuit - Google Patents

Dielectric isolation for monolithic circuit Download PDF

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USRE26778E
USRE26778E US26778DE USRE26778E US RE26778 E USRE26778 E US RE26778E US 26778D E US26778D E US 26778DE US RE26778 E USRE26778 E US RE26778E
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
    • H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
    • H01L27/0652—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/026—Deposition thru hole in mask
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/049—Equivalence and options
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/062—Gold diffusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/118—Oxide films
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/122—Polycrystalline
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/15—Silicon on sapphire SOS

Definitions

  • This invention relates to integrated circuits and more particularly to an improved semiconductor structure and method of providing the same.
  • the purest type is one in which an entire circuit function is provided within a monolithic block of silicon including both active and passive elements as well as interconnections between the various circuit elements.
  • This invention is primarily concerned with providing isolation of a [discreet] discrete electrical devices in an integrated circuit.
  • Another prior art process involves the use of an insulating buffer layer between the semiconductor substrate and the header of the package in which the integrated circuit is housed.
  • This isolation technique involves an additional number of manufacturing steps thereby increasing cost and decreasing yield. Further this technique can only achieve isolation between the device and the header, but not between [discreet] discrete electrical elements of a device from one another.
  • Another object of the present invention is to provide a technique for isolating the collector of a transistor.
  • a further object of the present invention is to provide an economical technique for providing isolation between circuit elements in an integrated circuit.
  • a further object of the present invention is to provide an integrated circuit in which all circuit elements terminate in a plane and wherein such elements are electrically isolated from each other and from the header of the package in which the integrated circuit is housed.
  • a still further object of the present invention is to provide an isolation technique for integrated circuits which results in high breakdown voltage, very low leakage, low parasitic capacitance and very low saturation voltage.
  • FIGURE 1 is a sectional view of an N type conductivity silicon body which is the starting material for the present invention integrated circuit
  • FIGURE 2 is a perspective view of the body of FIG URE 1 at an early stage of production of an integrated circuit constructed in accordance with the presently preferred embodiment of this invention
  • FIGURES 3-5 are sectional views of the silicon body of FIGURES l and 2 during later stages of manufacture;
  • FIGURE 6 is a sectional view of a portion of a completed integrated circuit constructed in accordance with this invention.
  • FIGURE 7 is a sectional view of an alternate construction of an integrated circuit made in accordance with this invention.
  • FIGURES 8-10 are sectional [view] views of a silicon block during an intermediate stage of production in carrying out [other] another alternate construction of this invention.
  • FIGURE 1 there is shown a sectional view of an N type conductivity single crystal silicon body.
  • This is the starting material for constructing an integrated circuit in accordance with the presently preferred embodiment of this invention.
  • the primary purpose of this invention is to provide a technique for constructing an integrated circuit in which the electrical elements provided within the circuit are electrically isolated one from the other and wherein all the circuit elements terminate in the same plane.
  • a typical resistivity for the starting crystal material of body 10 is from one to ten ohm-cm.
  • This body may be prepared by any conventional prior art method such as by slicing a wafer from Czochralski grown crystal which has an N type impurity, typically arsenic added to the melt prior to the withdrawal of the crystal therefrom.
  • the groove is designated by the numeral 12.
  • This groove may be established by a masking and etching process in accordance with well known prior art practices.
  • the purpose of the groove is to define at least one region within the body which is isolated from the remainder thereof.
  • an N+ diffused layer on the upper and lower surfaces 11 and 14.
  • the layer 15 which is typically 2 microns thick is preferably produced by the diffusion of an N type impurity such as phosphorus from a source of P 0 in order to produce a layer approximately 2 microns thick.
  • the thickness of the starting wafer 10 in FIGURES l and 2 in this example is 8 mils.
  • the depth of the groove 12 is approximately one mi].
  • the 2 micron diffused layer diffusion step is typically produced by heating the body 10 to a temperature of 1020 C. for three fourths hour in the presence of P 0
  • the formation of the N+ layer on the bottom surface 14 is of no concern.
  • the surface 14 may be removed to a depth greater than 2 microns by chemical etching using, for example, 2 parts HF, 15 parts HNO and 5 parts acetic acid.
  • Layer 20 is preferably formed of silicon in the following manner.
  • the body is placed into an epitaxial reactor of a type well known to the art for the deposition of a silicon semiconductor layer.
  • the present invention method employs a vapor phase co-deposition of both silicon and oxygen.
  • silicon is made available to the substrate by the thermal reduction of trichlorosilane by hydrogen and the oxygen is provided by the reaction of carbon dioxide with hydrogen.
  • the insulating layer formed by this method is preferably of the thickness of approximately 6 mils. This method is described in Some detail in an article entitled Successive Growth of SiO in Epitaxial Apparatus" by W. Steinmaier and J. Bloem in the February 1964 issue of Journal of the Electrochemical Society.
  • An alternate method for forming the dielectric layer is by cathodic sputtering. This is a process whereby a material which makes up the cathode of a high voltage gaseous discharge tube is transported to another portion of the system. Typically an atmosphere of inert gas such as argon at a pressure between 20 to 200 microns and a voltage of l0003000 v. is used.
  • the substrate or silicon body 10 is arranged so that the surface 11 is parallel to that of the cathode.
  • the inert gas becomes ionized and the gas ions bombard the cathode.
  • the energy of the ions is transferred to the cathodes and as a result particles of the cathode material are dislodged. These particles of atomic dimensions and greater, travel through the gas until they strike the surface 11.
  • oxygen with the gas in the discharge tube the deposit from the cathode instead of being a semiconductor material, becomes an insulating one.
  • dielectric constant of depositions made by the sputtering technique hereinabove described depends upon the oxygen content. Dielectric constants have ranged from 2 to 8. The latter figure was achieved by a deposit which container 4% SiO The maximum rate of deposition observed thus far has been 4 microns per hour.
  • the silicon body 10 is lapped to the cut line 25a as shown in FIGURE 4.
  • the cut line is just above the lower surface of the groove 12.
  • the body 10 will now appear as shown in FIGURE 6 wherein it is rotated at 180.
  • 3 insulated regions indicated by the numerals 23, 24 and 25 are separated by the insulating material 20. These 3 separate regions are but representative of any given number which may be desirable for forming a particular integrated circuit.
  • Following the lapping to cut line [25] 2511 further diffusion-masking operations are performed in accordance with well known prior art practices including photoresist, oxide masking and diffusion to produce the NPN transistor as shown in FIG- URE 6 in the central island 24.
  • the central island 24 constitutes an NPN transistor whose collector is isolated from the separated diffused elements and 31 which each include P and N regions thus serving as diodes.
  • the NPN transistor includes a plurality of electrodes including a collector region 35, a base region 36 and an emitter region 37. A rnetallized layer to make ohmic contact to each of these three regions is shown connecting to terminals labeled C. B and E standing for collector, base and emitter.
  • the collector electrode has a portion 38 deposited on the plane surface 39 of the insulating material substrate 20. to facilitate easier attachment of the terminal C by presenting a broader plane surface, similar to those attached to B and E. Because of the diffusion of the collector region 35 back along the plane 25 from the N+ region 15 with which it is associated.
  • FIGURE 7 there is shown a structure similar to that of FIGURE 6 which may be produced in a series of steps the same as those described in connection with FIGURES 1-6, The only difference is that instead of making the N+ dilfusion after the groove 12 is cut in the surface 11 of the substrate 20 the N-ldiffusion of the two micron thick layer 15 is carried out prior to the cutting of the groove 12.
  • the completed structure will in all regards be the same as that of the structure of FIGURE 6 except that the N-ldiffused region does not extend upwardly as does the N+ difiused region in the FIGURE 6 structure.
  • FIGURE 6 has a lower collector parasitic resistance. This is due to the fact that the N+ layer extends upward vertically and around to the contacting surface, thus permitting a much lower resistance [control] Contact to the adjacent N region in the FlGURE 6 structure than in the FIGURE 7 structure.
  • the transistor structure 24 forming part of the integrated circuit shown in FIGURE 6 has been found t result in very much improved electrical characteristics over that which typically result from the manufacture of a planar transistor in an integrated circuit in accordance with prior art practice.
  • the parasitic capacitance of the collector to the substrate in a prior art device is typically something greater than 2 picofarads while the present invention structure results in a parasitic capacitance of something less than 0.1 picofarad.
  • the reverse leakage of the PN junction in the prior art device is typically of the order of l0- amps; the present invention structure results in a reverse leakage of the PN junction of the order Of l l() amps.
  • the breakdown voltage in the present invention junction is typically greater than 200 volts while that of the prior art device is typically of the order of 20 volts. Further the collector parasitic resistance of the present invention device is typically of the order of 5 ohms while that of the prior art device is typically 20 ohms.
  • the starting material may be P type silicon or any other semiconductor material upon which an insulating layer may be deposited. It is believed for example, that germanium may he used, although in this instance GeO could not be substituted for Si as Ge0 is not stable, instead silicon with oxygen may again be co-deposited upon a germanium substrate.
  • plateau 80 may be deposited thereupon as shown in FIG- URE 8 to thus define isolated regions. Following the deposit of the silicon plateau 80 to define a structure similar to that shown in FIGURE 2, the steps following to produce the completed device may either be, as described in connection with FIGURES l6 and FIG- URE 7.
  • FIGURE 9 a similar procedure may be adopted except therein the substrate 91 on which the silicon plateaus 90 are deposited in an insulator.
  • the substrate 91 on which the silicon plateaus 90 are deposited in an insulator either sputtered or epitaxial silicon with oxygen may be deposited, after which either surface may be removed to expose silicon regions in a place which regions are separated by an insulator to a predetermined depth.
  • FIGURE 10 there is shown an insulator substrate 107 which includes grooves in the upper surface 102. Following this single or polycrystal silicon is deposited over the surface 102 thus filling the grooves and providing a layer of silicon 103 thereabove. This layer 103 may then be removed prior to final processing as described hereinbefore.
  • a technique and structure for producing an isolated semiconductor element integrated circuit which avoids the use of PN junctions as an isolation means which is highly reproducible and therefore inherently capable of producing high yields.
  • This structure further results in improved device characteristics such as improved high breakdown voltage, low isolation leakage, low parasitic capacitance and low saturation voltage.
  • each of said regions having a low resistance layer on the bottom and side surfaces of said region, said low resistance layer on said side surfaces extending upwardly to said plane surface of said substrate to facilitate low resistance connection of said element in said region to electrodes on said plane surface.
  • a semiconductor integrated circuit having a plurality of electrically isolated regions comprising:
  • each of said regions being surrounded beneath said surface by electrically insulating material, said insulating material extending upwardly to said surface to separate said regions;
  • each of said regions having a low resistance layer adjacent to said insulating material and extending from the bottom of said region to said upper surface:
  • (f) means to make electrical contact to said low resistance layer at said upper surface to form a low resistance connection to a portion of said semiconductor element within said region which portion is beneath said upper surface.
  • a semiconductor integrated circuit including a dielcctrically isolated region comprising:
  • (e) means to make electrical contact to said low resistonee layer to form a low resistance connection to said semiconductor element.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Description

Feb. 3, 1970 J. BUIE Re. 26,778
DIELECTRIC ISOLATION FOR MONOLITHIC CIRCUIT Original Filed March 30, 1964 v CHMES .11. (80/5 6197 .10. f m? J INVENTBR.
ATTORNEY United States Patent i 20,778 DIELECTRIC ISOLATION FOR MONOLITHIC CIRCUIT James Lang Buie, Panorama City, Calif., assignor to TRW Inc., a corporation of Ohio Original No. 3,320,485, dated May 16, 1967, Ser. No. 355,605, Mar. 30, 1964. Application for reissue Feb. 10, 1969, Ser. No. 822,969
Int. Cl. 1102b 1/00, H04; H01] 5/00 US. Cl. 317l 3 Claims Matter enclosed in heavy brackets appears in the original patent but forms no part of this reissue specification; matter printed in italics indicates the additions made by reissue.
This invention relates to integrated circuits and more particularly to an improved semiconductor structure and method of providing the same.
There are several types of so-called integrated circuits presently being manufactured. The purest type is one in which an entire circuit function is provided within a monolithic block of silicon including both active and passive elements as well as interconnections between the various circuit elements.
While the present invention is of particular value for integrated circuits it is equally applicable to other semiconductor devices, both active and passive, such as transistors, diodes, capacitors and resistors.
This invention is primarily concerned with providing isolation of a [discreet] discrete electrical devices in an integrated circuit.
Most prior art methods for achieving isolation between integrated circuit components employ a reversed biased PN junction as a means for achieving isolation. Among these prior art methods are the triple ditfusion process, the gate diffusion process, the epitaxial process and the buried layer epitaxial process.
Another prior art process involves the use of an insulating buffer layer between the semiconductor substrate and the header of the package in which the integrated circuit is housed. This isolation technique involves an additional number of manufacturing steps thereby increasing cost and decreasing yield. Further this technique can only achieve isolation between the device and the header, but not between [discreet] discrete electrical elements of a device from one another.
It is therefore a primary object of the present invention to provide an improved isolated semiconductor integrated circuit.
Another object of the present invention is to provide a technique for isolating the collector of a transistor.
A further object of the present invention is to provide an economical technique for providing isolation between circuit elements in an integrated circuit.
Yet, a further object of the present invention is to provide an integrated circuit in which all circuit elements terminate in a plane and wherein such elements are electrically isolated from each other and from the header of the package in which the integrated circuit is housed.
A still further object of the present invention is to provide an isolation technique for integrated circuits which results in high breakdown voltage, very low leakage, low parasitic capacitance and very low saturation voltage.
The novel fea ures which are believed to be characteristic of the invention, both as to its organization and method of operation, together with further objects and advantages thereof will be better understood from the following description considered in connection with the accompanying drawing in which a presently preferred embodiment of the invention is illustrated by way of example. It is to be expressly understood, however, that Re. 26,778 Reissured Feb. 3, 1970 the drawing is for the purpose of illustration and description only, and is not intended as a definition of the limits of the invention.
In the drawing:
FIGURE 1 is a sectional view of an N type conductivity silicon body which is the starting material for the present invention integrated circuit;
FIGURE 2 is a perspective view of the body of FIG URE 1 at an early stage of production of an integrated circuit constructed in accordance with the presently preferred embodiment of this invention;
FIGURES 3-5 are sectional views of the silicon body of FIGURES l and 2 during later stages of manufacture;
FIGURE 6 is a sectional view of a portion of a completed integrated circuit constructed in accordance with this invention;
FIGURE 7 is a sectional view of an alternate construction of an integrated circuit made in accordance with this invention; and
FIGURES 8-10 are sectional [view] views of a silicon block during an intermediate stage of production in carrying out [other] another alternate construction of this invention.
Referring now to the drawing and more particularly to FIGURE 1 there is shown a sectional view of an N type conductivity single crystal silicon body. This is the starting material for constructing an integrated circuit in accordance with the presently preferred embodiment of this invention. As was previously mentioned hereinbefore the primary purpose of this invention is to provide a technique for constructing an integrated circuit in which the electrical elements provided within the circuit are electrically isolated one from the other and wherein all the circuit elements terminate in the same plane. A typical resistivity for the starting crystal material of body 10 is from one to ten ohm-cm. This body may be prepared by any conventional prior art method such as by slicing a wafer from Czochralski grown crystal which has an N type impurity, typically arsenic added to the melt prior to the withdrawal of the crystal therefrom.
It is next desired to provide an annular depression or groove within the upper surface 11 of the body 10 wherein the groove is designated by the numeral 12. This groove may be established by a masking and etching process in accordance with well known prior art practices. The purpose of the groove is to define at least one region within the body which is isolated from the remainder thereof. Following the formation of the groove 12 in body 10 there is next formed an N+ diffused layer on the upper and lower surfaces 11 and 14. The layer 15 which is typically 2 microns thick is preferably produced by the diffusion of an N type impurity such as phosphorus from a source of P 0 in order to produce a layer approximately 2 microns thick. The thickness of the starting wafer 10 in FIGURES l and 2 in this example is 8 mils. The depth of the groove 12 is approximately one mi]. The 2 micron diffused layer diffusion step is typically produced by heating the body 10 to a temperature of 1020 C. for three fourths hour in the presence of P 0 Of necessity when the 2 micron layer is formed in the upper surface II another N+ layer will be formed in the lower surface 14. Inasmuch as the surface 14 will be removed by a lapping operation during a later stage in the production [art] of the integrated circuit the formation of the N+ layer on the bottom surface 14 is of no concern. Altcrnately the surface 14 may be removed to a depth greater than 2 microns by chemical etching using, for example, 2 parts HF, 15 parts HNO and 5 parts acetic acid. Following formation of the N+ layer 15 there is deposited atop the upper surface of layer 15 a relatively thick insulation layer 20 which is molecularly bonded to the N+ layer l5. Layer 20 is preferably formed of silicon in the following manner. The body is placed into an epitaxial reactor of a type well known to the art for the deposition of a silicon semiconductor layer. Instead, however, of producing a semiconductor layer the present invention method employs a vapor phase co-deposition of both silicon and oxygen. In the present method silicon is made available to the substrate by the thermal reduction of trichlorosilane by hydrogen and the oxygen is provided by the reaction of carbon dioxide with hydrogen. By controlling the amount of oxygen present which is available to combine wtih the silicon, there is deposited a polycrystalline silicon with grain boundaries of silicon dioxide thus rendering the deposited silicon insulating in character rather than semiconducting. The insulating layer formed by this method is preferably of the thickness of approximately 6 mils. This method is described in Some detail in an article entitled Successive Growth of SiO in Epitaxial Apparatus" by W. Steinmaier and J. Bloem in the February 1964 issue of Journal of the Electrochemical Society.
An alternate method for forming the dielectric layer is by cathodic sputtering. This is a process whereby a material which makes up the cathode of a high voltage gaseous discharge tube is transported to another portion of the system. Typically an atmosphere of inert gas such as argon at a pressure between 20 to 200 microns and a voltage of l0003000 v. is used. The substrate or silicon body 10 is arranged so that the surface 11 is parallel to that of the cathode. During the operation, the inert gas becomes ionized and the gas ions bombard the cathode. The energy of the ions is transferred to the cathodes and as a result particles of the cathode material are dislodged. These particles of atomic dimensions and greater, travel through the gas until they strike the surface 11. By introducing oxygen with the gas in the discharge tube the deposit from the cathode instead of being a semiconductor material, becomes an insulating one.
The dielectric constant of depositions made by the sputtering technique hereinabove described depends upon the oxygen content. Dielectric constants have ranged from 2 to 8. The latter figure was achieved by a deposit which container 4% SiO The maximum rate of deposition observed thus far has been 4 microns per hour.
Following deposition of the insulating layer 20 the silicon body 10 is lapped to the cut line 25a as shown in FIGURE 4. The cut line is just above the lower surface of the groove 12. Thus the body 10 will now appear as shown in FIGURE 6 wherein it is rotated at 180. Thus 3 insulated regions indicated by the numerals 23, 24 and 25 are separated by the insulating material 20. These 3 separate regions are but representative of any given number which may be desirable for forming a particular integrated circuit. Following the lapping to cut line [25] 2511 further diffusion-masking operations are performed in accordance with well known prior art practices including photoresist, oxide masking and diffusion to produce the NPN transistor as shown in FIG- URE 6 in the central island 24. The central island 24 constitutes an NPN transistor whose collector is isolated from the separated diffused elements and 31 which each include P and N regions thus serving as diodes. The NPN transistor includes a plurality of electrodes including a collector region 35, a base region 36 and an emitter region 37. A rnetallized layer to make ohmic contact to each of these three regions is shown connecting to terminals labeled C. B and E standing for collector, base and emitter. [the] The collector electrode has a portion 38 deposited on the plane surface 39 of the insulating material substrate 20. to facilitate easier attachment of the terminal C by presenting a broader plane surface, similar to those attached to B and E. Because of the diffusion of the collector region 35 back along the plane 25 from the N+ region 15 with which it is associated. and because of the extension of the low resistance region 15 up the sides of the isolated region 24 and, if desired, across its top as shown at 37a in FIGURE 6, a far better metal-tosemiconductor attachment is made between the lead C and the collector region 35. Note that there is provided an oxide layer SiO over the entire upper surface of the integrated circuit which serves to passivate the junctions and the active regions of the devices. Metallized contacts are also provided to the two P and N regions of each of the diodes 30 and 31. Thus the three electrical elements, namely, diodes 30, 31 and transistor 24 all terminate in the same surface of the insulating substrate 20. In addition each of these elements are electrically isolated one from the other by the substrate dielectric material which material also serves to isolate these elements from the header on which the substrate is to be mounted for packaging.
In FIGURE 7 there is shown a structure similar to that of FIGURE 6 which may be produced in a series of steps the same as those described in connection with FIGURES 1-6, The only difference is that instead of making the N+ dilfusion after the groove 12 is cut in the surface 11 of the substrate 20 the N-ldiffusion of the two micron thick layer 15 is carried out prior to the cutting of the groove 12. Thus the completed structure will in all regards be the same as that of the structure of FIGURE 6 except that the N-ldiffused region does not extend upwardly as does the N+ difiused region in the FIGURE 6 structure.
Electrically, [the difference between] the structure in FIGURE 6 and that of FIGURE 7 [is] are the same except that FIGURE 6 has a lower collector parasitic resistance. This is due to the fact that the N+ layer extends upward vertically and around to the contacting surface, thus permitting a much lower resistance [control] Contact to the adjacent N region in the FlGURE 6 structure than in the FIGURE 7 structure.
The transistor structure 24 forming part of the integrated circuit shown in FIGURE 6 has been found t result in very much improved electrical characteristics over that which typically result from the manufacture of a planar transistor in an integrated circuit in accordance with prior art practice. For example. the parasitic capacitance of the collector to the substrate in a prior art device is typically something greater than 2 picofarads while the present invention structure results in a parasitic capacitance of something less than 0.1 picofarad. The reverse leakage of the PN junction in the prior art device is typically of the order of l0- amps; the present invention structure results in a reverse leakage of the PN junction of the order Of l l() amps. The breakdown voltage in the present invention junction is typically greater than 200 volts while that of the prior art device is typically of the order of 20 volts. Further the collector parasitic resistance of the present invention device is typically of the order of 5 ohms while that of the prior art device is typically 20 ohms.
While this invention has been described in connection with the manufacture of an integrated circuit from a monolithic block of N type silicon it will be readily apparent to one skilled in the art that P type silicon may be used. Further isolation need not necessarily be brought about by the use of an annular shaped groove; any type of depression which results in the separation of discrete portions of the surface of the starting crystal to at least a predetermined depth will suffice. Other semiconductor materials besides silicon may also be employed and the means for providing the substrate depression upon the surface of the semiconductor starting crystal need not necessarily be limited to insulator growth in an epitaxial reactor and sputtering apparatus although these have been found to be particularly satisfactory.
While this invention has been described with reference to production of an integrated circuit in an N type conductivity block of silicon. it will be readily apparent to one skilled in the semiconductor art that the starting material may be P type silicon or any other semiconductor material upon which an insulating layer may be deposited. It is believed for example, that germanium may he used, although in this instance GeO could not be substituted for Si as Ge0 is not stable, instead silicon with oxygen may again be co-deposited upon a germanium substrate.
Also instead of cutting a groove in the starting wafer, plateau 80 may be deposited thereupon as shown in FIG- URE 8 to thus define isolated regions. Following the deposit of the silicon plateau 80 to define a structure similar to that shown in FIGURE 2, the steps following to produce the completed device may either be, as described in connection with FIGURES l6 and FIG- URE 7.
In FIGURE 9 a similar procedure may be adopted except therein the substrate 91 on which the silicon plateaus 90 are deposited in an insulator. Thus following this step either sputtered or epitaxial silicon with oxygen may be deposited, after which either surface may be removed to expose silicon regions in a place which regions are separated by an insulator to a predetermined depth.
In FIGURE 10 there is shown an insulator substrate 107 which includes grooves in the upper surface 102. Following this single or polycrystal silicon is deposited over the surface 102 thus filling the grooves and providing a layer of silicon 103 thereabove. This layer 103 may then be removed prior to final processing as described hereinbefore. There has thus been described a technique and structure for producing an isolated semiconductor element integrated circuit which avoids the use of PN junctions as an isolation means which is highly reproducible and therefore inherently capable of producing high yields. This structure further results in improved device characteristics such as improved high breakdown voltage, low isolation leakage, low parasitic capacitance and low saturation voltage.
What is claimed is:
1. A monolithic semiconductor integrated circuit device including the following characteristics:
.(a) a monolithic substrate having at least one plane surface;
(b) said substrate [being] including a portion composed of a non-conductive material;
(c) at least two semiconductor elements disposed within respective separate regions of semiconductor beneath said plane surface of said substrate; and
(d) portions of said monolithic substrate extending between said semiconductor [elements] regions;
(c) said portion beings monolithically continuous with said substrate;
(1'') said portions extending between said semiconductor [elements] regions in such manner as to insulate each said semiconductor element from all other said semiconductor elements[.]; and
(g) each of said regions having a low resistance layer on the bottom and side surfaces of said region, said low resistance layer on said side surfaces extending upwardly to said plane surface of said substrate to facilitate low resistance connection of said element in said region to electrodes on said plane surface.
2. A semiconductor integrated circuit having a plurality of electrically isolated regions comprising:
(a) a substrate having an upper surface;
(b) at least two separate regions of semiconductor material beneath said surface;
(c) each of said regions being surrounded beneath said surface by electrically insulating material, said insulating material extending upwardly to said surface to separate said regions;
(d) each of said regions having a low resistance layer adjacent to said insulating material and extending from the bottom of said region to said upper surface:
(e) a semiconductor element disposed within each of at least two of said regions, said elements being dielectrically isolated from each other by said insulating material; and
(f) means to make electrical contact to said low resistance layer at said upper surface to form a low resistance connection to a portion of said semiconductor element within said region which portion is beneath said upper surface.
3. A semiconductor integrated circuit including a dielcctrically isolated region comprising:
(a) a substrate having an upper surface;
(b) a region of semiconductor material beneath said surface, said region being surrounded beneath said surface by electrically insulating material, said insulating material extending upwardly to said surface to separate said region front the rest of said substrate,-
(c) said region having a low resistance layer adjacent to the inner side of said insulating material, said low resistance layer extending to said upper surface;
(d) a semiconductor element disposed within said region, said element being dielectricully isolated from the rest of said substrate by said insulating material; and
(e) means to make electrical contact to said low resistonee layer to form a low resistance connection to said semiconductor element.
References Cited The following references, cited by the Examiner, are of record in the patented file of this patent or the original patent.
UNITED STATES PATENTS 3,078,549 2/1963 Wende 29-l55.5 3,158,788 11/1964 Last 317101 3,176,192 3/1965 Sueur et al 3l7-l(ll 3,178,804 4/1965 Ullery et al 29155.5 3,197,710 7/1965 Lin 3l7l0l X 3,235,428 2/1966 Naymik 317235 3,239,908 3/1966 Nakamura 317-101 X ROBERT K. SCHAEFER, Primary Examiner J. R. SCOTT, Assistant Examiner US. Cl. X.R. 317-234; 29577

Claims (1)

1. A MONOLITHIC SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING THE FOLLOWING CHARACTERISTICS: (A) A MONOLITHIC SUBSTRATE HAVING AT LEAST ONE PLANE SURFACE; (B) SAID SUBSTRATE (BEING) INCLUDING A PORTION COMPOSED OF A NON-CONDUCTIVE MATERIAL; (C) AT LEAST TWO SEMICONDUCTOR ELEMENTS DISPOSED WITHIN RESPECTIVE SEPARATE REGIONS OF SEMICONDUCTOR BENEATH SAID PLANE SURFACE OF SAID SUBSTRATE; AND (D) PORTIONS OF SAID MONOLITHIC SUBSTRATE EXTENDING BETWEEN SAID SEMICONDUCTOR (ELEMENTS) REGIONS; (E) SAID PORTION BEINGS MONOLITHICALLY CONTINUOUS WITH SAID SUBSTRATE; (F) SAID PORTIONS EXTENDING BETWEEN SAID SEMICONDUCTOR (ELEMENTS) REGIONS IN SUCH MANNER AS TO INSULATE EACH SAID SEMICONDUCTOR ELEMENT FROM ALL OTHER SAID SEMICONDUCTOR ELEMENTS(.); AND (G) EACH OF SAID REGIONS HAVING A LOW RESISTANCE LAYER ON THE BOTTOM AND SIDE SURFACES OF SAID REGION, SAID LOW RESISTANCE LAYER ON SAID SIDE SURFACES EXTENDING UPWARDLY TO SAID PLANE SURFACE OF SAID SUBSTRATE TO FACILITATE LOW RESISTANCE CONNECTION OF SAID ELEMENT IN SAID REGION TO ELECTRODES ON SAID PLANE SURFACE.
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Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1030670A (en) * 1964-12-02 1966-05-25 Standard Telephones Cables Ltd Semiconductor devices
GB1073551A (en) * 1964-07-02 1967-06-28 Westinghouse Electric Corp Integrated circuit comprising a diode and method of making the same
DE1439706B2 (en) * 1964-07-29 1975-04-10 Telefunken Patentverwertungsgesellschaft Mbh, 7900 Ulm Process for the production of a microminiaturized circuit arrangement
US3850707A (en) * 1964-09-09 1974-11-26 Honeywell Inc Semiconductors
US3381182A (en) * 1964-10-19 1968-04-30 Philco Ford Corp Microcircuits having buried conductive layers
US3461003A (en) * 1964-12-14 1969-08-12 Motorola Inc Method of fabricating a semiconductor structure with an electrically isolated region of semiconductor material
GB1066911A (en) * 1965-01-01 1967-04-26 Standard Telephones Cables Ltd Semiconductor devices
DE1514488A1 (en) * 1965-06-29 1969-04-24 Siemens Ag Method for manufacturing a compound semiconductor device
US3475664A (en) * 1965-06-30 1969-10-28 Texas Instruments Inc Ambient atmosphere isolated semiconductor devices
FR1486855A (en) * 1965-07-17 1967-10-05
US3370995A (en) * 1965-08-02 1968-02-27 Texas Instruments Inc Method for fabricating electrically isolated semiconductor devices in integrated circuits
US3488834A (en) * 1965-10-20 1970-01-13 Texas Instruments Inc Microelectronic circuit formed in an insulating substrate and method of making same
US3433686A (en) * 1966-01-06 1969-03-18 Ibm Process of bonding chips in a substrate recess by epitaxial growth of the bonding material
US3423651A (en) * 1966-01-13 1969-01-21 Raytheon Co Microcircuit with complementary dielectrically isolated mesa-type active elements
US3471922A (en) * 1966-06-02 1969-10-14 Raytheon Co Monolithic integrated circuitry with dielectric isolated functional regions
US3507713A (en) * 1966-07-13 1970-04-21 United Aircraft Corp Monolithic circuit chip containing noncompatible oxide-isolated regions
GB699545A (en) * 1966-09-08 1953-11-11 Harold Stuart Hallewell Improvements in forming means for profile grinding wheels
US3575646A (en) * 1966-09-23 1971-04-20 Westinghouse Electric Corp Integrated circuit structures including controlled rectifiers
US3489961A (en) * 1966-09-29 1970-01-13 Fairchild Camera Instr Co Mesa etching for isolation of functional elements in integrated circuits
US3905037A (en) * 1966-12-30 1975-09-09 Texas Instruments Inc Integrated circuit components in insulated islands of integrated semiconductor materials in a single substrate
US3508980A (en) * 1967-07-26 1970-04-28 Motorola Inc Method of fabricating an integrated circuit structure with dielectric isolation
JPS4912795B1 (en) * 1968-12-05 1974-03-27
US3571919A (en) * 1968-09-25 1971-03-23 Texas Instruments Inc Semiconductor device fabrication
US3892033A (en) * 1970-02-05 1975-07-01 Philips Corp Method of manufacturing a semiconductor device
US3884733A (en) * 1971-08-13 1975-05-20 Texas Instruments Inc Dielectric isolation process
US4861731A (en) * 1988-02-02 1989-08-29 General Motors Corporation Method of fabricating a lateral dual gate thyristor

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1066282B (en) * 1958-03-26 1900-01-01
US3158788A (en) * 1960-08-15 1964-11-24 Fairchild Camera Instr Co Solid-state circuitry having discrete regions of semi-conductor material isolated by an insulating material
NL122607C (en) * 1961-07-26 1900-01-01
NL291352A (en) * 1962-04-10 1900-01-01
NL128995C (en) * 1962-08-03
US3235428A (en) * 1963-04-10 1966-02-15 Bell Telephone Labor Inc Method of making integrated semiconductor devices
US3197710A (en) * 1963-05-31 1965-07-27 Westinghouse Electric Corp Complementary transistor structure

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