JPH01160051A - Bipolar transistor - Google Patents

Abstract

PURPOSE:To increase a current amplification factor largely by holding a thin film such as a silicon nitride film having a higher tunnel barrier to electrons than holes in an emitter region. CONSTITUTION:A polycrystalline silicon film 10 is formed to the whole surface of a substrate, B ions are implanted from the upper section of the main surface of the substrate 1, and a P-type emitter region 11 is shaped into an N-type semiconductor region 7 as an internal base. The P-type emitter region 11 and one part of the polycrystalline silicon film 10 function as an emitter at that time. Consequently, a base recombination current component is interrupted by a silicon nitride film 9 in a P-N-P transistor having structure in which the silicon nitride film 9 is held as a film having a higher tunnel barrier to electrons than holes between the P-type emitter region 11 and the polycrystalline silicon film 10, thus generating no recombination of carriers on the interface between an emitter relectrode 14a and the polycrystalline silicon film 10. Accordingly, base currents can be reduced, thus improving a current amplification factor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device, and particularly to a structure of a bipolar transistor in which the transistor 41 is improved.

(Prior Art) In a semiconductor device constituting a conventional bipolar integrated circuit, for example, a PNP bipolar transistor, an N-type region serving as a base is formed on the main surface of a P-type semiconductor substrate (collector), and the It is known that a P-type region serving as an emitter is formed on the entire surface of an N-type region. Here, the N-type region and the P-type region are P or A, respectively.
An N-type impurity such as No. 8 and a P-type impurity such as B are formed by ion implantation or diffusion, and a metal layer such as aluminum or a high melting point metal is formed as an emitter electrode on the emitter.

Alternatively, as another conventional transistor, two P-type regions serving as an emitter and a collector are formed on the main surface of an N-type semiconductor substrate (base), and an emitter electrode and a collector electrode are formed on the two P-type regions, respectively. Structures formed are known.

In the emitter of a bipolar transistor of any structure, a phenomenon of recombination of minority carriers occurs at the metal-semiconductor interface between the metal layer of the emitter electrode and the P-type semiconductor region. This is because a small number of carriers from the base current flowing by applying a pace emitter voltage (VBE) between the base and emitter recombine at the aforementioned interface, and the shallower the emitter depth, the less this tendency occurs. Remarkable. In general, the current amplification factor h of bipolar transistors is
From F z=” c/ (here IC=collector current.

(2) B: base current), but lB is also a rare force for the recombination of the minority carriers.

Therefore, even if it is necessary to reduce the depth of the emitter region in the future, there is a limit to the ability to improve hFE due to the minority carrier recombination problem. In other words,
In order to increase the current amplification factor hFK, it is necessary to reduce the base current 1B without reducing the collector current, but the conventional structure described above has a limit.

(Problems to be Solved by the Invention) The present invention has been made in order to solve the above-mentioned problems of conventional bipolar transistors.

The object of the present invention is to provide a bipolar transistor in which the current amplification factor is increased by reducing the base recombination current in the emitter region, and the device performance is greatly improved.

[Structure of the invention]

(Means for Solving the Problems) In order to achieve the above object, the present invention provides a second conductivity type region formed on the whole surface of a first conductivity type semiconductor substrate, and a second conductivity type region formed on the entire surface of a first conductivity type semiconductor substrate;
A first conductivity type region formed on the inner surface of the conductivity type region, a thin film having a high tunnel barrier for electrons, and a hole area formed so as to cover at least the surface of the first conductivity type region; A bipolar transistor having a first conductive type semiconductor film formed thereon and an electrode connected to the first conductive type semiconductor film is provided.

(Function) According to the present invention, for example, in a PNP5i bipolar transistor, a thin film such as a silicon nitride film with a high tunnel barrier is sandwiched between the hole region and the electron region in the emitter region, so that the base recombination current component is reduced. It becomes possible to increase the current amplification factor by a wide range.

(Implementation row) First implementation row The first implementation row according to the present invention will be explained in detail using the drawings. FIGS. 1A to 1E are process cross-sectional views showing the manufacturing method.

First, as shown in FIG.
Form a film with a thickness of . The oxide film (2a) forms an element isolation region, and the film thickness is 4000A for example l@J.
And so.

Next, using a resist mask (3), P ions (4) are selectively implanted into a part of the substrate (1) on which the silicon oxide film (2) is formed from the main surface side of the substrate to form an N-type semiconductor. A region (external base) (5) was formed. here.

The P ions (4) were introduced under the conditions of an accelerating voltage of 30 kV and a driving force of 1014 cm.

Next, after removing the resist mask (3).

Figure 1 (shown in BL↓UniP ions (b) were applied to the entire surface at a speed voltage of 30 kV and an implantation amount of I x 10" cm-
An N-type semiconductor region (internal base) (7) was formed under the following conditions.Here, the accelerating voltage was 30 kV, but at least the N-type semiconductor region (7) that would become the internal base was The type semiconductor region (5) ↓ may also be set to be a shallow region.

Next, as shown in FIG. 1(c), a part of the oxide film (2) on the Nffa semiconductor region (7) which will become the internal base is removed by etching to form an opening (8) with a width of 1.5 μm. .

Subsequently, a silicon nitride film (9) with a thickness of about 1 OA was formed at least on the N-type semiconductor region (7) in which the opening (8) was formed by plasma chemical vapor deposition or the like. Further, heat treatment was performed at 600° C. in an Nt atmosphere for about 30 minutes to remove residual H atoms from the silicon nitride film (9).

In FIG. 1 fcl, the silicon nitride film (9) is shown in a row formed on the entire surface of the substrate, but the silicon nitride film (9)
The N-type semiconductor fJF may be selectively formed on the region (7).

Subsequently, as shown in FIG. 1 d), a film with a thickness of 10
After forming a polycrystalline silicon film (10) of 00A.

B ions are delivered from the main surface of the substrate (1) at a voltage of 25 kV.
.

Implantation was performed under the conditions of implantation lil 5 x 10"cm-" to form a P-type emitter region (11) within the N-type semiconductor region (7) which will serve as the internal base. Here this P
type emitter region (11) and the polycrystalline silicon film (10).
) becomes the emitter.

Furthermore, the polycrystalline silicon film (10) and the silicon nitride film (9) are buttered to form at least the opening (8).
After leaving the silicon nitride film (9) and polycrystalline silicon model (10) formed on the surface, an insulating film (2) such as a silicon oxide film (see Fig. 1) is deposited by chemical vapor deposition, etc. , about 300 OA, and then the emitter (10
) and an N-type semiconductor region (5) serving as an external base, a portion of the insulating film (12) is removed by etching. (13a) and (13b) are openings formed by the etching. Furthermore, electrodes @ (1
As 4a) and (14b), for example, aluminum or the like is buried to form a PNPe bipolar transistor which is an embodiment of the present invention.

As in this example, a silicon nitride film (9), for example, is sandwiched between the P-wall emitter block (11) and the polycrystalline silicon film (10) as a film having a higher tunnel barrier for electrons than the direct ratio. In the case of a PNP transistor with a structure like this, the base recombination current component is blocked by the silicon nitride film (9), and the emitter electrode
No recombination of carriers occurs at the interface between the polycrystalline silicon layer and the polycrystalline silicon layer (10).

Therefore, the base current can be reduced and the current amplification factor hFE can be improved.

Here, the film thickness of the silicon nitride@(9) was set to IOA, and good characteristics of a bipolar transistor were obtained at a thickness of 20 A or less. It is desirable that the film thickness be as thin as possible in order to reduce the resistance as much as possible, but its optimum value depends on the conditions of the shape of the transistor, such as the relationship between the depth of the emitter (11) and the diffusion length, or the Habase emitter voltage ( VB
It may be determined based on the following conditions:

In other words, if the depth of the emitter (11) is 1 m (11) and the diffusion length is short, base recombination current components are likely to occur. It is desirable to do so.

FIG. 3 is an electrical characteristic diagram (Gammel plot) for explaining the PNP transistor effect of this embodiment.

That is, FIG. 3 shows the collector current (( I
e) and base current (IB) were investigated for each.

From this figure, the bipolar transistors of the first implementation column according to the present invention (Ill are the conventional bipolar transistors t
11- It can be seen that the base current (IB) is reduced compared to the above. In the same figure, the range of VBE is 0.6 to 1.0 rV.
), but the effect of reducing the base current is different from other VBE
It can also be obtained within the range of

Regarding the collector current (Ic), the two cases show almost the same characteristics, so it can be seen that the current amplification factor hFB-■C/IB of the first embodiment has been improved. .

Also, if the composition is like this actual row, the internal base (7)
The depth of the emitter region (11) formed therein can be made extremely shallow, which is advantageous for the structure of the semiconductor device.

Second Embodiment A sectional view of the manufacturing process for obtaining the second embodiment of the present invention will be described in detail with reference to FIG.

First, an N-type silicon substrate (3
A silicon oxide film (31) was formed to a thickness of 500 Å on the surface of 0). (31a) is an element isolation region, and the film thickness is 4000A.First, the oxide film (31) excluding the area where the emitter and collector are planned to be formed, (31a)
A resist mask (32) is formed on the top. Furthermore, 8 ions (33) are accelerated from the main surface side of the substrate (30) at a voltage of 35
kV.

The above group II (
P-type semiconductor head mounted on (30) (34), (35a), (3
5b) is formed. here.

(34) is the emitter region, (35a), (3
5b) is the collector area.

Next, as shown in FIG. 3 [bl], the silicon oxide film (31) on the emitter region (34) is removed and an opening (36
) form αD. Furthermore, a silicon nitride film (
37). Although this silicon nitride film (37) is formed on the entire surface of the substrate here, it is sufficient that it is formed well on at least the emitter (34) as in the first embodiment. Subsequently, heat treatment is performed for 30 minutes in a N atmosphere at 600° C. to remove H atoms remaining in the silicon nitride film (37).

Subsequently, after forming a polycrystalline silicon film (38) with a thickness of 100 OA on the entire surface of the substrate (30), B ions (39) were implanted at an acceleration voltage of 25 kV at a rate of 15 x 10" cm. -! The polycrystalline silicon model is made into a P-type child-crystalline silicon film (38a). Here, this P-type child-crystalline silicon film (38a) and the emitter region (34) serve as an emitter.

Thereafter, after removing the silicon nitride film (37) and the P-type crystalline silicon film (38) except on the emitter region (34), a cloudy oxide film (39) is formed on the entire surface as shown in FIG. After forming 3000A by vapor phase growth method etc.
The remaining P-type crystalline silicon film (38) and the collector II (
Opening for connecting with 35b) @ (40a), (
40b) and further the opening (40a).

(40b) Form electrodes (41a) and (41b). The structure of the bipolar transistor thus obtained also provides the same effect as the first implementation column.

FIG. 4 is an electrical characteristic diagram (Gummel plot) of the PNP type bipolar transistor of the second embodiment.

From this figure, the bipolar transistor II of the second embodiment
As with the first implementation column, it can be seen that the base current (IB) is reduced and the current amplification factor is improved compared to the conventional bipolar transistor +Il.

The present invention is not limited to the above-described first and second embodiments, for example, emitters.

The impurities in the collector and base regions are each P type.

Any impurity can be used as long as P-type and N-type can be obtained, and thermal diffusion method, ion implantation method, etc. can be used.

It may be formed by any method.

Further, the same effect can be obtained if the silicon nitride films in the first and second implementation rows are made of a material that has a higher tunneling barrier for electrons than for holes.

〔Effect of the invention〕

According to the present invention E, the base current can be reduced and the current amplification factor hFK can be increased, so that the transistor characteristics are improved.

[Brief explanation of the drawing]

Fig. 1 is a sectional view of the manufacturing process according to one embodiment of the present invention, Fig. 2 is a characteristic diagram for explaining the effects of one embodiment of the present invention, and Fig. 3 is another embodiment according to the present invention. FIG. 4, which is a sectional view of the manufacturing process according to the example, is a characteristic diagram for explaining other effects of the present invention. 1.30...Substrate, 2.31...Oxide film, 5...
External base, 7... Internal base, 9.37... Silicon nitride film, 10.38... Polycrystalline silicon film, 11
゜34...Emitter layer, 35a+35b...Collector. 12, 39-...Oxide film, 14a, 14b--x miv
ll electrode.

Claims (5)

[Claims] (1) a first conductivity type semiconductor substrate, a second conductivity type region formed on one principal surface of the first conductivity type semiconductor substrate, and a second conductivity type region formed on one principal surface of the first conductivity type semiconductor substrate;
a first conductivity type region formed on the inner surface of the conductivity type region; a thin film having a higher tunnel barrier for electrons than for holes and formed to cover at least the surface of the first conductivity type region; A bipolar transistor comprising a first conductivity type semiconductor film formed in the first conductivity type semiconductor film and an electrode connected to the first conductivity type semiconductor film. (2) The bipolar transistor according to claim 1, wherein the first conductivity type and the second conductivity type are P type and N type, respectively. (3) The thin film is a silicon nitride film, and the film thickness is 20 Å.
A bipolar transistor according to claim 1, characterized in that: (4) The bipolar transistor according to claim 1, wherein the thin film is formed using a chemical vapor deposition method or a plasma chemical vapor deposition method. (5) an N-type semiconductor substrate, a plurality of P-type semiconductor regions formed on the main surface of the N-type semiconductor substrate, and a positive electrode formed so as to cover the surface of at least one region of the plurality of P-type semiconductor regions; Claim 1, characterized by having a thin film having a higher tunnel barrier for electrons than for holes, a P-type semiconductor film formed on this thin film, and an electrode connected to this P-type semiconductor film. Bipolar transistor as described in section.