JPH0258772B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a method of manufacturing a semiconductor device having a bipolar transistor.

Recently, as the field of application of electronics has expanded, semiconductor integrated circuits in which various transistors with different characteristics are formed on a single semiconductor substrate are increasingly being manufactured. This tendency is particularly strong in linear semiconductor integrated circuits (hereinafter referred to as LIC) using bipolar transistors. What is important in manufacturing such semiconductor integrated circuits is how to form various transistors with different characteristics on the same semiconductor substrate in fewer steps.

In principle, in order to properly form the active region of a transistor necessary to obtain the desired characteristics, it is possible to selectively introduce impurities as many times as necessary by changing the conditions, but in practice However, it is difficult to perform such a process many times, and the more steps for introducing impurities, the more difficult it is to properly control the active region, and the quality and manufacturing yield of LIC decreases significantly. Therefore, by designing each transistor with a different size, efforts have been made to manufacture each transistor in the same process as much as possible.
The degree of freedom in design is not necessarily large. In particular, it has been extremely difficult to obtain desired characteristics when a normal bipolar transistor and an IIL (Integrated Injection Logic) element are formed on the same semiconductor substrate in the same impurity introduction process.

Figure 1 shows a conventional bipolar transistor and IIL
1 is a schematic cross-sectional view of a semiconductor chip showing an example of a semiconductor device having an element.

As shown in FIG. 1, N ⁺
A type buried region 4 is formed, and an N type epitaxial layer 5 is formed on the surface including the N ⁺ type buried region 4. Next, a P-type impurity is selectively introduced into the surface of the epitaxial layer 5 to provide an element isolation region 20 that reaches the P-type silicon substrate, thereby forming the first and second elements each including an N ⁺ type buried region 4. Forming regions 1 and 2 are defined. Next, P-type impurities are simultaneously introduced selectively into each of the first and second element formation regions 1 and 2 to form a bipolar transistor base region 6 and a second element formation region in the first element formation region 1. 2, the base region 12 and injector region 13 of the IIL element are formed. Next, N-type impurities are simultaneously introduced selectively into the first and second element formation regions 1 and 2 to form a collector contact region 11 in the base region 6 in the vicinity of the emitter region 7 and base region 6 of the bipolar transistor. At the same time, an injector region 13 is formed in the base region 12 in the vicinity of the first collector region 14 and second collector region 15 of the IIL element and the base region 12. next,
A silicon oxide film 21 is deposited on the entire surface and holes are selectively opened to form a base electrode 9 connected to the base region 6 of the bipolar transistor, an emitter electrode 10 connected to the emitter region 7, and a collector connected to the collector contact region 8. An electrode 11 is provided to form a bipolar transistor, and a base electrode 12 is connected to the base region 12 of the IIL element;
A first collector electrode 18 and a second collector electrode connected to the collector region 14 and the second collector region 15, respectively.
A semiconductor device is constructed by providing a collector electrode 19 and an injector electrode 17 connected to the injector region 13 to form an IIL element.

The biggest problem with such a structured LIC is that it is difficult to increase the withstand voltage of the bipolar transistor in order to operate the IIL element at a low voltage.

In order to increase the withstand voltage of a bipolar transistor, it is necessary to increase its base width W _b1 and increase its impurity concentration, but if an IIL element is formed in the same impurity introduction process, a vertical transistor of an IIL element, that is, a reverse NPN transistor. The base width W _b2 of the transistor (hereinafter referred to as an inverse transistor) also increases and the electron injection efficiency decreases, resulting in a decrease in the current amplification factor βu and a decrease in operating characteristics.

Furthermore, if the impurity concentration of the base region 12 of the reverse transistor is lowered, the current amplification factor βu of the reverse transistor increases, but the hole injection efficiency of the lateral transistor composed of the injector region 13, the N-type epitaxial layer 5, and the base region 12 increases. As a result, the gain becomes smaller.

That is, in order to maximize the functionality of this LIC, (A) the base region 6 of the bipolar transistor must have a high impurity concentration and the base width W _b1 is also large; (B) the base region of the reverse transistor of the IIL element must have a high impurity concentration and a large base width W b1; Area 12
(C) The base region 12 of the reverse transistor of the IIL element has a low impurity concentration and a small base width W _b2 in its intrinsic base region (the lower part of the first and second collector regions 14 and 15).
The following three conditions must be satisfied at the same time: the impurity concentration is high in the region other than the intrinsic base region, and the depth of the region is deep (graft base structure).

LIC with a structure that satisfies these conditions is possible by introducing impurities into the base region in two steps, but in addition to the problem of increasing the number of steps, IIL
As a result, the determination of the base width W _b3 of the lateral transistor of the device becomes inaccurate due to misalignment of the mask.
The problem is that the quality and manufacturing yield of LIC are significantly reduced.

An object of the present invention is to form base regions with different impurity concentrations and depths by introducing impurities once, so that a high breakdown voltage bipolar transistor and a high current amplification IIL element can be formed in the same process on the same semiconductor substrate. An object of the present invention is to provide a method for manufacturing a semiconductor device.

A method for manufacturing a semiconductor device according to the present invention includes: (A) selectively introducing an N-type impurity into one main surface of a P-type silicon substrate to form an N-type buried region;
(B) selectively introducing P-type impurities into the surface of the N-type epitaxial layer to form an element isolation region that reaches the P-type silicon substrate; and the above N
(C) selectively and simultaneously introducing P-type impurities into each of the first and second element forming regions; (D) forming a first base region for a bipolar transistor in the element formation region and simultaneously providing a second base region and an injector region for the IIL element in the second element formation region; (E) providing a silicon nitride film on the surface including the second base region, and selectively etching the silicon nitride film on the second base region to form an opening for forming a collector region; The surface of the second base region in the hole is thermally oxidized, and the first and second base regions are indented by heat treatment, and the diffusion depth of the second base region is made shallow just below the oxide film and the nitridation is performed. (F) After the silicon nitride film and oxide film are removed, an insulating film is formed on the entire surface, holes are selectively formed, and N-type impurities are introduced into the first silicon film. Forming the emitter region of the bipolar transistor in the base region,
and on the shallow diffusion region of the second base region.
The method includes a step of forming a collector region of an IIL element.

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 2a to 2f are schematic sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention. However, for the common parts with the conventional example shown in FIG. 1, a part of the cross-sectional view is omitted to simplify the explanation.

First, as shown in FIG. 2, by the same process as explained in FIG. □ Multiple N ⁺ type buried regions are formed, and the surface including the N ⁺ type buried regions has a specific resistance of approximately 1.
An N-type epitaxial layer 5 of Ω·cm is formed to a thickness of about 10 μm. Next, P-type impurities are selectively introduced into the surface of the epitaxial layer 5 to provide element isolation regions 50 that reach the P-type silicon substrate.
A first element formation region 31 for forming a bipolar transistor including an N ⁺ type buried region and a second element formation region 32 for forming an IIL element are divided, and the first and second element formation regions 31 and 32 are separated. A silicon oxide film 51 is formed on the surface including the substrate.

Next, as shown in FIG. 2b, the silicon oxide film 51 is selectively etched with hydrofluoric acid or the like to form an opening, and boron ions are accelerated at an energy of 20 keV and a dose of 5 using the silicon oxide film 51 as a mask. Ion implantation is performed under conditions of ×10 ¹⁴ cm ^-2 to form a base region 36 in the first element formation region 31 and at the same time form a base region 42 and an injector region 43 in the second element formation region 32.

Next, as shown in FIG. 2c, a silicon nitride film 52 is deposited on the entire surface to a thickness of 0.5 μm by CVD, and the silicon nitride film 52 on the base region 42 is selectively etched by plasma etching. Then, an opening for forming a collector region is provided.

Next, as shown in FIG. 2d, the surface of the base region 42 is oxidized in a steam oxygen atmosphere at 1000° C. to form a silicon oxide film 53 with a thickness of several tens of nanometers. Here, the silicon oxide film 53 is formed by penetrating inside the base region 42, and impurities are diffused from the base region 42 into the silicon oxide film 53, and the thickness of the base region 42 directly under the oxide film becomes thinner. The impurity concentration also becomes lower.

Next, as shown in FIG. 2e, after sequentially removing the silicon nitride film 52 and the oxide base film 51, a new silicon oxide film 51 is re-formed on the entire surface.
Intrusion diffusion is performed for about 1 hour in an inert gas atmosphere such as nitrogen at 1140°C.

Note that in this case, it is not necessarily necessary to re-form the silicon oxide film, and this forced diffusion may be performed with the original silicon oxide film and silicon nitride film.
Here, the base region 3 of the first element formation region 31
6, and the base region 4 of the second element formation region 32
2 and an injector region 43 are finally formed. In this case, as described above, the portions of the base region 42 where the collector is to be formed are thin and have a lower impurity concentration than the other portions, so impurities are pushed into these portions less, resulting in a so-called graft base. structure is obtained.

Next, as shown in FIG. 2F, the silicon oxide film 51 is selectively etched to form holes, and N-type impurities are diffused to form the emitter region 37 and collector contact region 38 in the first element forming region 31. are formed to form a bipolar transistor, and first and second collector regions 44 and 45 are formed in the second element forming region 32 to form an IIL element.
Next, holes are selectively opened in the silicon oxide film 51.
Depositing and selectively etching an aluminum layer to form the base electrode 39 of the bipolar transistor;
An emitter electrode 40, a collector electrode 41, a base electrode 46 of an IIL element, an injector electrode 47, a first collector electrode 48, and a second collector electrode 49 are formed to constitute a semiconductor device.

Note that here, instead of the ion implantation method, a thermal diffusion method may be used to introduce impurities for forming the base region.

As described above, according to this embodiment, an oxide film is selectively formed on the base region and heat treated, and the impurity concentration and diffusion depth under the oxide film can be controlled to be different from other parts. Therefore, in a semiconductor device having a bipolar transistor and an IIL element formed on the same semiconductor substrate in the same process, the impurity concentration in the base region of the bipolar transistor is increased and the base width W _b1 is increased to achieve high breakdown voltage. In the base region of the reverse transistor of the IIL element, the impurity concentration of the intrinsic base region directly under the first and second collectors is reduced by controlling the formation conditions of the silicon oxide film, and the base width W _b2 is reduced. Since the parts other than the intrinsic base region are formed simultaneously under the same conditions as the base region of the bipolar transistor, a so-called graft base structure with a high impurity concentration and a deep depth is obtained, so that the current amplification factor βu of the inverse transistor is This has the effect of increasing the .

Further, the injector region of the IIL element is formed in the same process as the base region of the bipolar transistor, and the impurity concentration thereof can be increased and the impurity can be diffused deeply, so that the gain of the lateral transistor can be increased. Furthermore, since impurities are introduced into the base region only once, the base width W _b3 can be accurately set without causing misalignment of the mask, resulting in improved quality.

As explained above, in the present invention, a high breakdown voltage bipolar transistor and a high current amplification IIL element are fabricated on the same semiconductor substrate in the same process by forming base regions with different impurity concentrations and depths by introducing impurities once. This has the effect that it is possible to realize a method for manufacturing a semiconductor device that can be formed using the following steps.

[Brief explanation of drawings]

FIG. 1 is a schematic sectional view of a semiconductor chip showing an example of a conventional semiconductor device, and FIGS. be. DESCRIPTION OF SYMBOLS 1, 31... First element formation region, 2, 32... Second element formation region, 3... P-type silicon substrate, 4...
N ⁺ type buried region, 5, 35...N type epitaxial layer, 6, 12, 36, 42... base region, 7, 3
7... Emitter region, 8, 38... Collector contact region, 9, 16, 39, 46... Base electrode, 1
0,40...Emitter electrode, 11,41...Collector electrode, 13,43...Injector area, 14,4
4...First collector region, 15,45...Second collector region, 20,50...Element isolation region, 21,5
1, 53...Silicon oxide film, 52...Silicon nitride film, _Wb1 , _Wb2 , _Wb3 ...Base width.

Claims (1)

[Claims] 1 (A) N-type impurities are selectively introduced into one main surface of a P-type silicon substrate to form an N-type buried region, and an N-type impurity is formed on the surface including the N-type buried region. a step of forming an epitaxial layer; (B) selectively introducing P-type impurities into the surface of the N-type epitaxial layer to provide element isolation regions reaching the P-type silicon substrate;
(C) selectively and simultaneously introducing P-type impurities into each of the first and second element forming regions; (D) forming a first base region for a bipolar transistor in the element formation region and simultaneously providing a second base region and an injector region for the IIL element in the second element formation region; (E) providing a silicon nitride film on the surface including the second base region, and selectively etching the silicon nitride film on the second base region to form an opening for forming a collector region; The surface of the second base region in the hole is thermally oxidized, and the first and second base regions are indented by heat treatment, and the diffusion depth of the second base region is made shallow just below the oxide film and the nitridation is performed. (F) After the silicon nitride film and oxide film are removed, an insulating film is formed on the entire surface, holes are selectively formed, and N-type impurities are introduced into the first silicon film. Forming the emitter region of the bipolar transistor in the base region,
and on the shallow diffusion region of the second base region.
A method for manufacturing a semiconductor device, comprising the step of forming a collector region of an IIL element.