JPS60192365A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPS60192365A JPS60192365A JP4970384A JP4970384A JPS60192365A JP S60192365 A JPS60192365 A JP S60192365A JP 4970384 A JP4970384 A JP 4970384A JP 4970384 A JP4970384 A JP 4970384A JP S60192365 A JPS60192365 A JP S60192365A
- Authority
- JP
- Japan
- Prior art keywords
- region
- collector
- thin film
- emitter
- ion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000012535 impurity Substances 0.000 claims abstract description 20
- 238000010884 ion-beam technique Methods 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000013078 crystal Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000005468 ion implantation Methods 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 2
- 238000002513 implantation Methods 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 10
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 230000003071 parasitic effect Effects 0.000 abstract description 4
- 230000001681 protective effect Effects 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 2
- 229910052796 boron Inorganic materials 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、集束イオン・ビームを用いて、横型の薄膜
バイポーラ・トランジスタを製造する技術に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a technique for manufacturing lateral thin film bipolar transistors using a focused ion beam.
従来の集積回路中のバイポーラ・トランジスタは、いわ
ゆるプレーナ法で形成されており、その断面構造および
平面構造は第１図（ａ）、（ｂ）に示すようになってい
る。トランジスタ動作は、ｐ型のエミッタ１からその直
下のｐ型の活性ベース領域２ヘキヤリアが注入され、活
性ベース領域２中で再結合しなかったキャリアはｎ−型
のエピタキシャル層３で形成されるコレクタ４に達して
、コレクタ電流となることで達成されている。このよう
に、トランジスタ動作領域はエミッタ１から縦方向に伸
びているが、エミッタ、コレクタ、ベースの各電極Ｅ、
Ｃ，Ｂは半導体基板５の表面において取り出す必要があ
るため、トランジスタの動作領域から各電極Ｃ，Ｂまで
は仮想線で示す抵抗性導体中を電流が流れる。このため
、第１図（ｂ）の平面図に示すように、エミッタ面積と
ほぼ等しいトランジスタ動作領域、すなわち、実質的に
トランジスタ動作に寄与するのはエミッタ面積であるの
に比べて、トランジスタ全体の面積は約２０〜３０倍に
も大きくなり、上記抵抗性導体に起因する寄生抵抗とと
もに、浮遊の接合容量が極めて大きくなり、トランジス
タの高速動作性能に悪影響を及ぼしていた。Bipolar transistors in conventional integrated circuits are formed by a so-called planar method, and their cross-sectional and planar structures are as shown in FIGS. 1(a) and 1(b). In the transistor operation, carriers are injected from the p-type emitter 1 to the p-type active base region 2 immediately below it, and the carriers that have not recombined in the active base region 2 are injected into the collector formed in the n-type epitaxial layer 3. This is achieved by reaching 4 and becoming the collector current. In this way, the transistor operating region extends vertically from the emitter 1, and each of the emitter, collector, and base electrodes E,
Since C and B need to be taken out at the surface of the semiconductor substrate 5, current flows through resistive conductors shown by imaginary lines from the operating region of the transistor to each electrode C and B. For this reason, as shown in the plan view of FIG. 1(b), the transistor operating area is approximately equal to the emitter area, that is, the emitter area substantially contributes to the transistor operation, whereas the entire transistor area is approximately equal to the emitter area. The area becomes about 20 to 30 times larger, and together with the parasitic resistance caused by the resistive conductor, the floating junction capacitance becomes extremely large, which adversely affects the high-speed operation performance of the transistor.
さらに、トランジスタの動作に決定的な影響を及ぼす活
性ベース領域２は、ベースのｐ型不純物拡散層と、エミ
ッタ１のｎ 型不純物拡散層の差で形成されるため、０
．２〜０．５μｍ程度の極めて薄い活性ベース領域２の
形成は制御性に大きな問題があった。Furthermore, the active base region 2, which has a decisive influence on the operation of the transistor, is formed by the difference between the p-type impurity diffusion layer of the base and the n-type impurity diffusion layer of the emitter 1.
．． Formation of the extremely thin active base region 2 of about 2 to 0.5 μm has a major problem in controllability.
また、従来のプレーナ法でも、動作電流を横方向に流す
横型トランジスタを形成することは可能であるが、写真
製版の精度上、縦型トランジスタで実現されている０、
２〜０．５μｍ程度の仙めて薄い活性ベース領域２を形
成することができず、トランジスタの性能は縦型トラン
ジスタに比べて大幅に劣っていた。Furthermore, although it is possible to form horizontal transistors that allow the operating current to flow horizontally using the conventional planar method, due to the precision of photolithography, the 0,
It was not possible to form a very thin active base region 2 of about 2 to 0.5 μm, and the performance of the transistor was significantly inferior to that of a vertical transistor.
この発明は、上記のような従来のプレーナ法によるバイ
ポーラ・トランジスタの欠点を除去するためになされた
もので、集束イオン・ビームを用いることにより、性能
の向上をはかった横型の薄膜バイポーラ・トランジスタ
の製造方法を提供することを目的としている。以下、こ
の発明の一実施例を図面について説明する。This invention was made in order to eliminate the drawbacks of the conventional planar bipolar transistor as described above, and it is a lateral thin film bipolar transistor with improved performance by using a focused ion beam. The purpose is to provide a manufacturing method. An embodiment of the present invention will be described below with reference to the drawings.
第２図（ａ）〜（ｆ）はこの発明の一実施例の製造工程
を示す断面図である。これらの図において、１１は絶縁
基板、１２はｐ−型のシリコン結晶薄膜、１３は素子分
離領域である酸化膜、１４は保護膜、１５はｎ＋型のエ
ミッタ領域、１６はｎ ／ ｎ＋型のコレクタ領域、１
７はベース領域、１８はベース・コンタクト領域、１９
はエミッタ・コンタクト領域、２０はコレクタ・コンタ
クト領域、２１は電極金属配線である。FIGS. 2(a) to 2(f) are cross-sectional views showing the manufacturing process of an embodiment of the present invention. In these figures, 11 is an insulating substrate, 12 is a p-type silicon crystal thin film, 13 is an oxide film which is an element isolation region, 14 is a protective film, 15 is an n+ type emitter region, and 16 is an n/n+ type emitter region. Collector area, 1
7 is a base region, 18 is a base contact region, 19
2 is an emitter contact region, 20 is a collector contact region, and 21 is an electrode metal wiring.
次に、製造方法について説明する。まず、第２図（ａ）
に示すように、酸化シリコン等の絶縁基板１１の上に、
厚さ数ＩＱＯＯＡの第１導電型である、例えばシリコン
結晶薄膜１２を成長させる。Next, the manufacturing method will be explained. First, Figure 2(a)
As shown, on an insulating substrate 11 such as silicon oxide,
For example, a silicon crystal thin film 12 of the first conductivity type with a thickness of several IQOOA is grown.
このシリコン結晶薄膜１２の形成には、ＣＶＤ法でデポ
ジットした多結晶シリコン薄膜を、レーザ・ビームで照
射し、溶融再結晶化させて単結晶薄膜にする技術を用い
る。To form this silicon crystal thin film 12, a technique is used in which a polycrystalline silicon thin film deposited by the CVD method is irradiated with a laser beam and melted and recrystallized to form a single crystal thin film.
次に、第２図（ｂ）に示すように、周知の選択酸化法に
より素子分離領域である厚い酸化膜１３を形成して、ト
ランジスタとなる領域を決定する。Next, as shown in FIG. 2(b), a thick oxide film 13 serving as an element isolation region is formed by a well-known selective oxidation method to determine regions that will become transistors.
シリコン結晶薄膜１２の表面を酸化シリコンなどの薄い
保護膜１４で覆った後、第２図（ｃ）に示すように、集
束イオン・ビーム装置（図示せず）を用いて、例えばＡ
ｓ イオ／のようなｎ型不純物イオン・ビームを０．１
μｍ程度に集束して第２導電型であるｎ型不純物を注入
し、エミッタ領域１５およびコレクタ領域１６を形成す
る。この際、ｎ型不純物を注入しない領域はベース領域
１Ｔとなるが、イオン・ビームは０．１μｍ程度に集束
されており、かつ二次元的な走査精度も０．１μｍ程度
にしうるので、ベース領域１Ｔの幅としては０．１〜０
．２μｍ程度に精度よく制御することができ、また、イ
オン・ビームのエネルギーは、１００〜２００ＫｅＶを
用いるのでイオン・ビームの直進性もよく、深さ方向に
けぼ一様な幅をもつベース領域１７を形成することがで
きる。また、コレクタ領域１６へのイオン注入において
は、ベース領域近傍の不純物濃度を薄くし、ベース領域
１Ｔから遠ざかるにつれて不純物濃度を濃くし、トラン
ジスタのベース・コレクタ耐圧を高くすることができる
。この不純物の濃度変化はイオン・ビームの走査速度を
変えることによって容易に達成でき、任意の耐圧のトラ
ンジスタを形成することが可能である。After covering the surface of the silicon crystal thin film 12 with a thin protective film 14 such as silicon oxide, as shown in FIG.
0.1 n-type impurity ion beam such as s io/
The emitter region 15 and the collector region 16 are formed by implanting n-type impurities of the second conductivity type in a concentrated manner to about μm. At this time, the region where the n-type impurity is not implanted becomes the base region 1T, but since the ion beam is focused to about 0.1 μm and the two-dimensional scanning accuracy can be about 0.1 μm, the base region The width of 1T is 0.1 to 0
．． The ion beam can be precisely controlled to about 2 μm, and since the ion beam energy is 100 to 200 KeV, the ion beam has good straightness, and the base region 17 has a uniform width in the depth direction. can be formed. Furthermore, in the ion implantation into the collector region 16, the impurity concentration near the base region is reduced, and the impurity concentration is increased as the distance from the base region 1T increases, thereby increasing the base-collector breakdown voltage of the transistor. This change in impurity concentration can be easily achieved by changing the scanning speed of the ion beam, making it possible to form a transistor with any desired breakdown voltage.
こうして、ｎ＋型のエミッタ領域１５とｎ ／ ｎ＋型
のコレクタ領域１６がイオン注入により形成された後、
與２図（ｄ）に示すように、ベース領域１７となる領域
をボロンなどのｐ型不純物を集束・ｆオン・ビームによ
ってイオン注入する〇
続い−Ｃ第２図＜ｅ）に示すように、ベース・コンタク
ト領域１８．エミッタ・コンタクト領域１９゜コレクタ
・コンタクト領域２０をエツチングにより開口し、さら
に、この開口部分に第２図（ｆ）のように、電極金属配
線２１を形成して横型の薄膜バイポーラ・トランジスタ
を完成する。After the n+ type emitter region 15 and the n/n+ type collector region 16 are thus formed by ion implantation,
As shown in Figure 2 (d), p-type impurities such as boron are ion-implanted into the region that will become the base region 17 using a focused f-on beam. Base contact area 18. Openings are made in the emitter contact region 19° and the collector contact region 20 by etching, and electrode metal wiring 21 is further formed in this opening as shown in FIG. 2(f) to complete a horizontal thin film bipolar transistor. .
上記のよう罠形成されたトランジスタは、横方向に動作
させるためトランジスタの不活性な領域が極めて少なく
、また、不活性な抵抗性導体も不要なためトランジスタ
の寄生抵抗が極めて小さく、かつ、接合容量もトランジ
スタの動作領域のみに限られ、浮遊容量の極めて小さな
トランジスタとなり、高周波特性の優れたトランジスタ
を形成することが可能である。Since the trap-formed transistor described above operates in the lateral direction, the inactive area of the transistor is extremely small, and there is no need for an inactive resistive conductor, so the parasitic resistance of the transistor is extremely small, and the junction capacitance is This is limited only to the operating region of the transistor, resulting in a transistor with extremely small stray capacitance, making it possible to form a transistor with excellent high frequency characteristics.
なお、上記実施例ではｎｐｎ型のトランジスタについて
説明したが、これはｐｎｐ型のトランジスタも同様に構
成できることはいうまでもない。In the above embodiment, an npn type transistor has been described, but it goes without saying that a pnp type transistor can also be constructed in the same manner.
以上説明したように、この発明は、集束イオン・ビーム
を用いることにより横型のバイポーラ・トランジスタを
形成したので、寄生抵抗や、浮遊容量が少なく、高速動
作性能の優れた薄膜バイポーラ・トランジスタを形成す
ることができる。As explained above, the present invention forms a horizontal bipolar transistor using a focused ion beam, thereby forming a thin film bipolar transistor with low parasitic resistance and stray capacitance and excellent high-speed operation performance. be able to.
また、コレクタ領域のイオン注入量を、ベース領域近傍
の不純物設置を薄くし、ベース領域から遠ざかるに従っ
て不純物濃度を濃くすることによりトランジスタのベー
ス・コレクタ耐圧を高くすることができる等の利点が得
られる。In addition, advantages such as increasing the base-collector breakdown voltage of the transistor can be obtained by reducing the amount of ion implantation in the collector region by thinning the impurity near the base region and increasing the impurity concentration as the distance from the base region increases. .
第１図（ａ） 、（ｂ）は従来のプレーナ型バイポーラ
・トランジスタの構造を示す断面図および平面図、亀２
図（ａ）〜（ｆ）はこの発明の一実施例を示す横をの薄
膜バイポーラ・トランジスタの製造工程を示す断面図で
ある。
図中、１１は絶縁基板、１２はｐ−型のシリコン結晶薄
膜、１３は素子分離用の酸化膜、１４は保護膜、１５は
ｎ＋型のエミッタ領域、１６はｎ／ｒｉ＋型のコレクタ
領域、１７はベース領域、１８はベース・コンタクト領
域、１９はエミッタ・コンタクト領域、２０はコレクタ
・コンタクト領域、２１は電極金属配線である。
なお、図中の同一符号は同一または相当部分を示す。
代理人 大岩増雄 （外２名）Figures 1(a) and 1(b) are a cross-sectional view and a plan view showing the structure of a conventional planar bipolar transistor.
Figures (a) to (f) are cross-sectional views showing the manufacturing process of a horizontal thin film bipolar transistor according to an embodiment of the present invention. In the figure, 11 is an insulating substrate, 12 is a p-type silicon crystal thin film, 13 is an oxide film for element isolation, 14 is a protective film, 15 is an n+ type emitter region, 16 is an n/ri+ type collector region, 17 is a base region, 18 is a base contact region, 19 is an emitter contact region, 20 is a collector contact region, and 21 is an electrode metal wiring. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Masuo Oiwa (2 others)
Claims (1)
薄膜に、素子分離領域を形成する工程、集束イオン・ビ
ームを用いて、前記第１導電型の半導体結晶薄膜に第２
導電型の不純物をイオン注入しエミッタ領域およびコレ
クタ領域を形成する工程、前記第２導電型の不純物のイ
オン注入を行わずに形成した狭いベース領域に連結して
前記第１導電型の不純物をイオン注入しベース・コンタ
クト領域を形成する工程、前記コレクタ領域、エミッタ
領域にそれぞれ連結して第２導電型の不純物をイオン注
入しコレクタ・コンタクト領域およびエミッタ・フンタ
クト領域を形成する工程、前記各フンタクト領域から電
極配線をそれぞれ取り出す工程とを含むことを特徴とす
る薄膜トランジスタの製造方法。 （２）集束イオン・ビームを用いて第２導電型の不純物
をイオン注入する際、コレクタ領域のイオン・注入量を
ベース領域に近接した領域の不純物注入量を下げ、ベー
ス領域から遠ざかるにつれて不純物注入量を増大させる
ことを特徴とする特許請求の範囲第（１）項記載の薄膜
トランジスタの製造方法。[Scope of Claims] (11) A step of forming an element isolation region in a semiconductor crystal thin film of a first conductivity type grown on an insulating substrate; second to
A step of ion-implanting conductivity type impurities to form an emitter region and a collector region, and ion-implanting the first conductivity type impurities by connecting to the narrow base region formed without performing ion implantation of the second conductivity type impurities. a step of implanting an impurity of a second conductivity type to form a collector contact region and an emitter contact region by ion-implanting impurities of a second conductivity type connected to the collector region and the emitter region respectively; a step of forming a collector contact region and an emitter contact region; A method for manufacturing a thin film transistor, comprising the step of taking out electrode wiring from the thin film transistor. (2) When implanting second conductivity type impurities using a focused ion beam, the ion implantation amount in the collector region is lowered in the region close to the base region, and the impurity implantation is continued as the distance from the base region increases. The method for manufacturing a thin film transistor according to claim 1, wherein the amount of the thin film transistor is increased.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59049703A JPH0665218B2 (en) | 1984-03-13 | 1984-03-13 | Method of manufacturing thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59049703A JPH0665218B2 (en) | 1984-03-13 | 1984-03-13 | Method of manufacturing thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60192365A true JPS60192365A (en) | 1985-09-30 |
| JPH0665218B2 JPH0665218B2 (en) | 1994-08-22 |
Family
ID=12838543
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59049703A Expired - Lifetime JPH0665218B2 (en) | 1984-03-13 | 1984-03-13 | Method of manufacturing thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0665218B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62219570A (en) * | 1986-03-19 | 1987-09-26 | Nec Corp | Manufacture of lateral hetero-junction bipolar transistor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS503780A (en) * | 1973-05-15 | 1975-01-16 | ||
| JPS57157570A (en) * | 1981-03-02 | 1982-09-29 | Rockwell International Corp | Lateral transistor |
| JPS58223321A (en) * | 1982-06-22 | 1983-12-24 | Toshiba Corp | Implantation of ion |
-
1984
- 1984-03-13 JP JP59049703A patent/JPH0665218B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS503780A (en) * | 1973-05-15 | 1975-01-16 | ||
| JPS57157570A (en) * | 1981-03-02 | 1982-09-29 | Rockwell International Corp | Lateral transistor |
| JPS58223321A (en) * | 1982-06-22 | 1983-12-24 | Toshiba Corp | Implantation of ion |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62219570A (en) * | 1986-03-19 | 1987-09-26 | Nec Corp | Manufacture of lateral hetero-junction bipolar transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0665218B2 (en) | 1994-08-22 |
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