JPS62219570A - Manufacture of lateral hetero-junction bipolar transistor - Google Patents

Abstract

PURPOSE:To realize a transverse hetero-junction bipolar transistor having a thickness of 0.1-0.2mum that has been impossible according to prior arts, by utilizing convergent ion beams for implanting N- and P-type dopants and for forming a mixed crystal compound semiconductor. CONSTITUTION:Be convergent ion beans 5 are applied to a region 2 on the surface of a semi-insulating GaAs substrate 1 with an accelerating energy of 100keV and in a dosage of 5X10<14>cm<-2>, for example, so as to implant Be ions therein. Then Si convergent ion beams 6 are applied to a region 4 adjacent to the region 2 with an accelerating energy of 200keV and in a dosage of 1X10<13>cm<-2>, for example, so as to implant Si ions therein. Further, Si convergent ion beams 8 are applied to a region 2 adjacent top the region 2 with an accelerating energy of 200keV and in a dosage of 5X10<12>cm<-2>, for example, so as to implant Si ions therein. Further, Al convergent ion beams 7 are applied to the region 4 with an accelerating energy of 200keV and in a dosage of 1X10<22>cm<-2>, for example, so as to implant A ions therein. The structure is then heat treated at a temperature of 850 deg.C for forming ohmic electrodes in the regions 4, 2 and 3 separately. Thus, a transverse hetero-junction bipolar transistor is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a heterojunction bipolar transistor.

(Prior art) Heterojunction bipolar transistors are expected to be used as semiconductor devices for ultra-high-speed integrated circuits and devices for microwave and millimeter waves because they can increase the emitter injection efficiency even if the base layer is highly doped. Research and development is underway. Typically, a heterojunction bipolar transistor is
Although this is a vertical structure in which the emitter, base, and collector layers are formed in a direction perpendicular to the substrate, a horizontal structure in which the width of the emitter electrode can be made finer has also been proposed.

Conventionally, selective epitaxial growth has been used as a method for realizing lateral heterojunction bipolar transistors.

FIGS. 2(1) to 2(4) are device cross-sectional views showing a method of manufacturing a conventional lateral heterojunction bipolar transistor.

In FIG. 2(1), after etching the semi-insulating GaAs substrate 11 using 5i0212 as a mask, an N-type AlGaAs layer 13 is selectively grown by MOCVD. Next, in FIG. 2(2), the semi-insulating GaAs substrate 11 is etched using 5i0217 as a mask, and then a P-type GaAs layer 14 is selectively grown by MOCVD. Further, in FIG. 2(3), the semi-insulating GaAs1 plate 11 is etched using 5i0218 as a mask, and then an N-type GaAs layer 15 is selectively grown. Next, in Figure 2 (4), 5i
When 02 is removed, an emitter layer made of the N-type AlGaAs layer 3, a base layer made of the P-type GaAs layer 14, and a collector layer made of the N-type GaAs layer 15 are formed.

Thereafter, if home electrodes are independently formed in each layer, a heterojunction bipolar transistor is formed.

(Problems to be Solved by the Invention) The above-mentioned prior art uses selective epitaxial growth technology, but this method has two major drawbacks.

One of them is that it is difficult to form a selective epitaxial growth layer in a region thinner than lpm. In order to obtain sufficient device characteristics, the base layer thickness W shown in FIG. 2(2) needs to be 0.2 pm or less, but this cannot be achieved by selective epitaxial method. Furthermore, a second drawback is that the properties of the junction interface of the selective epitaxially grown layer are insufficient, resulting in large interfacial recombination.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a lateral heterojunction bipolar transistor that eliminates the above drawbacks, realizes a base layer thickness of about 0.2 pm or less, and has a junction with little interfacial recombination.

(Means for solving the problem) A step of selectively ion-implanting a P-type (or N-type) dopant into a first region of the surface of a semi-insulating semiconductor substrate using a focused ion beam; Laterally, N type (or P type) dopants are selectively implanted using a focused ion beam. a step of forming a third region;
Elements constituting a binary or higher mixed crystal compound semiconductor having approximately the same lattice constant as the semiconductor substrate are applied to both or one of the third regions at a dose that satisfies the stoichiometry using a focused ion beam. The first step is to perform selective ion implantation and heat treatment. Second. The above-mentioned problem can be solved by a method for manufacturing a lateral heterojunction bipolar transistor characterized by including a step of activating the third region.

(Function) According to the manufacturing method of the present invention, since the beam diameter of the focused ion beam is reduced to about 0.2 pm or less, P-type or N-type dopant can be implanted into a region with a width of 0.2 pm or less. At the same time, it is possible to ion-implant an element for a mixed crystal compound semiconductor whose lattice constant is approximately the same as that of the substrate, so that a lateral heterojunction bipolar transistor having a base layer thickness of 0.2 pm or less can be realized. Furthermore, unlike the selective epitaxial method, this process does not expose the bonding interface, so it is also possible to lower the level of interface states that cause interfacial recombination.

(Embodiment) FIGS. 1(1) to 1(4) are device cross-sectional views showing a method for manufacturing a lateral heterojunction bipolar transistor according to an embodiment of the present invention. In FIG. 1(1), a region 2 on the surface of a semi-insulating GaAs substrate 1 is irradiated with a concentrated Be ion beam 5 at an acceleration energy of 100 keV and a dose of 5.times.10' cm@-2 to implant Be ions. Next, in FIG. 1 (2), an acceleration energy of 2
Si focused ion beam 6 is irradiated to implant Si ions under the condition of 00 keV dose I.times.10.sup.13 cm.sup.-2. Furthermore, a Si focused ion beam 8 is irradiated to a region 3 in contact with the region 2 under conditions of an acceleration energy of 200 keV and a dose of 5×10 12 cm −2 to implant Si ions. Further, in FIG. 1(3), the region 4 is given an acceleration energy of 200 keV dose I x 1022 cm-
AI focused ion beam 6 is irradiated under the conditions of 2 to implant AI ions. Next, in FIG. 1 (4), when heat treated at 850°C, region 4 becomes an emitter layer with a doping amount of 3X.
N-type Alo25Ga (1,75AS
region 2 becomes a base layer with a doping amount of 1×1
019cm-3 becomes a P-type GaAs layer, and region 3 becomes a collector layer.It becomes an N-type GaAs layer with a doping amount of 6 x 1016cm-3.If an ohmic electrode is formed individually in region 4.2.3, a lateral heterojunction is formed. A bipolar transistor is formed. In Fig. 1 (4), the base layer thickness W
A device having an extremely fine structure with a width of 0.2 pm and an emitter electrode width t of 0.1 pm was realized, and characteristics such as an emitter ground current gain cutoff frequency of 150 GHz were realized.

(Effects of the Invention) In the manufacturing method of the present invention, a focused ion beam is used for implanting N-type and P-type dopants and forming a mixed crystal compound semiconductor.
, it has become possible to realize a 1-0.2 pm class lateral heterojunction bipolar transistor. This result = 150GH2
It has become possible to realize high-speed integrated circuit devices, achieved high-speed integrated circuits, and achieved highly efficient oscillation amplification in the millimeter wave band, which is of great significance in semiconductor optics.

[Brief explanation of drawings]

1 and 2 are device cross-sectional views showing a manufacturing method of a lateral heterojunction bipolar transistor according to an embodiment of the present invention and a conventional example, respectively, in which 5.6.7.8 is a focused ion beam;
, 11 is a semi-insulating GaAs substrate, 4.2.3. are the emitter, base, and collector layers, respectively. 13.14.15
are selectively epitaxially grown emitters, respectively.

Claims (1)

[Claims] A process of selectively ion-implanting a P-type (or N-type) dopant into a first region of the surface of a semi-insulating semiconductor substrate using a focused ion beam; forming second and third regions by selectively ion-implanting dopants using a focused ion beam; A step of selectively implanting the elements constituting the above-mentioned mixed crystal compound semiconductor using a focused ion beam at a dose that satisfies stoichiometry, and heat treatment to activate the first, second, and third regions. A method for manufacturing a lateral heterojunction bipolar transistor, comprising the steps of: