GB2056165A - Hot-electron or hot-hole transistor - Google Patents
Hot-electron or hot-hole transistor Download PDFInfo
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- GB2056165A GB2056165A GB7927647A GB7927647A GB2056165A GB 2056165 A GB2056165 A GB 2056165A GB 7927647 A GB7927647 A GB 7927647A GB 7927647 A GB7927647 A GB 7927647A GB 2056165 A GB2056165 A GB 2056165A
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- 239000002784 hot electron Substances 0.000 title abstract description 11
- 230000004888 barrier function Effects 0.000 claims abstract description 130
- 239000012535 impurity Substances 0.000 claims abstract description 22
- 239000000969 carrier Substances 0.000 claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 239000002800 charge carrier Substances 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- 239000002019 doping agent Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 7
- 238000002513 implantation Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- -1 boron ions Chemical class 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 229910001449 indium ion Inorganic materials 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000003801 milling Methods 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004943 liquid phase epitaxy Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/7606—Transistor-like structures, e.g. hot electron transistor [HET]; metal base transistor [MBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
Abstract
A hot-electron or hot-hole transistor includes a base region (2) through which hot majority charge carriers (7) flow. The application of a bias voltage (VBE) is necessary to supply such carriers (7) having energies above the base-collector barrier, thus improving the collection efficiency. The emitter-base barrier- forming means comprises a semiconductor barrier region (4) having a sufficiently large thickness and impurity concentration of the opposite conductivity type to the base region that said barrier region (4) is only partially depleted by the depletion layer or layers present at the emitter-base barrier at zero bias. The hot majority carriers (7) can be produced by punch-through of the depletion layer(s). The emitter may comprise a Schottky contact (5) or an ohmic contact. Low emitter capacitance can be obtained by including a lower-doped zone (6) of either conductivity type to extend the emitter-base depletion layer(s). In another form (see Figures 7 and 8) the emitter-base barrier forming means also includes an insulating layer (14). The base-collector barrier can be formed by a fully depleted barrier region (1). <IMAGE>
Description
SPECIFICATION
Transistors
This invention relates to transistors, particularly but not exclusively transistors for high frequency applications or fast switching appliances. Such transistors may be in the form of discrete devices, or they may be integrated in more complex structures, for example in a monolithic integrated circuit.
United States Patent Specification (US-PS) 4,149,174 (Our Reference: PHB 32542) discloses a transistor comprising a semiconductor body including a base region of one conductivity type through which current flow is by hot majority charge carriers, and barrier-forming means which form with said base region emitter-base and basecollector barriers. Such a transistor may be termed a "hot-electron" or "hot-hole" transistor, depending on whether the hot majority charge carriers are electrons or holes.
A hot charge carrier is one which is not in thermal equilibrium with the lattice. Thus a hot electron has an energy more than a few k.T above the Fermi energy (where k and T are Boltzmann's constant and the lattice temperature respectively), whereas a hot hole has an energy more than a few k.T below the Fermi energy.
Such transistors can have negligible minority storage effects in both the emitter and base regions and therefore be suitable for use at a fast speed or high frequency. They may also have a low base resistance by choosing a high impurity concentration of the one conductivity type for the base region, and may be relatively insensitive to inhomogeneities in base doping. Therefore such transistors can have significant advantages compared with conventional n-p-n or p-n-p bipolar transistors.
In one form described in United States Patent
Specification said emitter-base barrier-forming means comprises a barrier region having an impurity concentration of the opposite conductivity type to the base region. This barrier region separates, and forms depletion layers with, both the base region and an emitter region of the same conductivity type as said base region. The barrier system is sufficiently thin that these depletion layers formed at zero bias merge together in said barrier region to substantially deplete at zero bias the whole of said barrier region
States Patent Specification, the emitter-base opposite conductivity types.
In the transistors disclosed in said United
States Patent Specification, the emitter-base barrier is chosen to be higher than the basecollector barrier so that the energy of the hot carriers emitted into the base region is sufficiently high to surmount the base-collector barrier.
Generally speaking, the higher the energy of the emitted carriers the greater is the collection efficiency. A high collection efficiency is desirable, particularly for obtaining a high common-emitter current gain for the transistor. It is also often desirable to have a low emitter capacitance, particularly for fast switching or high frequency performance.
The present invention provides an improvement in the emitter-base barrier-forming means which raises the energy of the emitted carriers relative to the base-collector barrier and permits the obtaining of structures which can have a low emitter capacitance.
According to a first aspect of the present invention a transistor may be provided comprising a semiconductor body including a base region of one conductivity type through which current flow is by hot majority charge carriers, and barrierforming means which form with said base region emitter-base and base-collector barriers, said emitter-base barrier-forming means comprising a barrier region having an impurity concentration of the opposite conductivity type, and characterized in that the thickness and impurity concentration of said barrier region are sufficiently large that said barrier region is at least over part of its thickness undepleted by the depletion layer or layers present in said emitter-base barrier at zero bias, the application of a bias voltage between the base and emitter of the transistor being necessary to spread said depletion layer(s) across the whole thickness of the barrier region between the emitter and base region thereby raising the energy of the emitted carriers relative to the base-collector barrier.
A bias voltage of a certain magnitude is necessary to spread the depletion layer(s) across the whole thickness of the barrier region. Until this occurs the undepleted part of the barrier region inhibits emission of hot carriers into the base region and the effect of the applied bias voltage is to increase relative to the base-collector barrier the energy of the carrier distribution to be emitted.
In this way when emission occurs the energy of the emitted carriers can be considerably higher than the base-collector barrier, so providing a high collection efficiency. Because the depletion layer or layers present at the emitter-base barrier at zero bias is or are spread during operation over the undepleted thickness of the barrier region, a lower emitter capacitance may also be obtained due to an increased width of the depletion layer(s).
In one form, the barrier region may be present between the base region and an ohmic contact of the emitter, and the barrier region may be separated from the ohmic contact by a lowerdoped zone which is of the one conductivity type and with which the barrier region forms a depletion layer. Due to the spread of the depletion layers in this low-doped zone and in the barrier region, such a structure can have a very low emitter capacitance.
In another form, the emitter-base barrierforming means comprises a Schottky contact at a surface of the body, said barrier region being present between the Schottky contact and the base region, and at least part of the thickness of said barrier region lying outside the depletion layer present at said Schottky contact at zero bias. The combination of the at least partly undepleted barrier region and ths Schottky contact can produce a high emitter-base barrier for injecting very hot majority carriers into the base region so improving the collection efficiency.
Compared with a Schottky emitter without such a barrier region, the emitter capacitance can also be smaller, particularly if further zones are included to further spread the depletion layer.
Thus, said barrier region of the opposite conductivity type may be separated from the
Schottky contact by a lower-doped zone which may be either of said opposite conductivity type or of the one conductivity type.
It is generally preferable for the base region to be highly doped to reduce the spread of depletion layers in the base region and reduce the base resistance. Therefore preferably said base region has a conductivity type determining impurity concentration of at least 1020 dopant atoms/cm3, and may be considered a degenerately-doped semiconductor region.
Instead of using a barrier region which is of said opposite conductivity type and undepeleted over at least part of its thickness, the energy of the emitted carriers may be raised in a similar way relative to the base-collector barrier by using a metal-insulator-semiconductor multiple layer structure.Thus, according to a second aspect of the present invention a transistor may be provided
comprising a semiconductor body including a base region of one conductivity type through which current flow is by hot majority charge carriers, and barrier-forming means which form with said base region emitter-base and base-collector barriers, and characterized in that said emitter-base barrierforming means comprise a metal layer on an insulating layer at a surface of the body, the application of a bias voltage between the base and emitter being necessary to permit injection of the hot charge carriers across the insulating layer from the metal layer to the base region thereby raising the energy of the injected carriers relative to the base-collector barrier.
These and other features in accordance with the invention and some of their advantages will now be described-with reference to the accompanying diagrammatic drawings, illustrating, by way of example, various embodiments of the invention. In these drawings:
Figure 1 is an energy diagram through a transistor in accordance with the first aspect of the invention, both under bias and zero bias conditions;
Figure 2 is a cross-sectional view of one example of such a transistor and showing possible circuit connections;
Figure 3 is a cross-sectional view of another example of such a transistor and showing possible circuit connections;
Figure 4 is an energy diagram through a modified form of the trnsistor of Figure 1, both under bias and zero bias conditions;;
Figure 5 is an energy diagram through a further transistor in accordance with the first aspect of the invention, both under bias and zero bias conditions;
Figure 6 is a cross-sectional view that one example of the transistor of Figure 5;
Figure 7 is an energy diagram through a transistor in accordance with the second aspect of the invention, under bias conditions, and
Figure 8 is a cross-sectional view of one example of the transistor of Figure 7.
It should be noted that all of the Figures are diagrammatic and not drawn to scale; the relative dimensions and proportions of some parts of these
Figures have been shown exaggerated or reduced for the sake of clarity and convenience. The same reference numerals as used in one Figure are generally used to refer to the same or similar parts in the other Figures.
The transistor illustrated in Figure 1 comprises a monocrystalline semiconductor body including semiconductor regions 1 to 4. The region 2 is a highly doped base region of one conductivity type (in this example, n-type). Barrier-forming means 1 and 4, 5 form with the base region 2 a basecollector barrier and an eimitter-base barrier respectively. The current flow through the base region 2 (from the emittrer-base barrier to the base-collector barrier) is by hot majority carriers (in this example, hot electrons for n-type base region 2) which are indicated by arrows 7.
The base-collector barrier is formed by a barrier region 1 having an impurity concentration characteristic of the opposite conductivity type (in this example, p-type) the magnitude of which determines the height of a potential barrier to the flow of charge carriers of the one type (in this example, electrons) from both the base region 2 and a collector region 3. The barrier region 1 is sufficiently thin that depletion layers which it forms at zero bias with both the base and collector regions merge together in the region 1 to substantially deplete even at zero bias the whole of the region 1 of mobile charge carriers of both conductivity types. The collector region 3 is of the same conductivity type (n-type) as the base region 2 but is less highly doped. Preferably the conductivity type determining impurity concentration of the base region is at least 1020 donor atoms/cm3.
The formation and use of such substantially depleted barrier regions 1 for the base-collector barriers of hot-electron (or hot hole) transistors are described in detail in United States Patent
Specification (US-PS) 4,149,174, to which reference is invited and the whole contents of which are hereby incorporated as background material into the present Specification. In order to maintain the barrier region 1 substantially depleted at zero bias the thickness and doping level of the region 1 must satisfy certain conditions as described in US-PS 4,149,1 74.
The emitter-base barrier is formed by both a metal layer 5 forming a Schottky contact and a barrier region 4 having an impurity concentration of opposite conductivity type (p-type) to the base region 2. It should be noted that US-PS 4,149,174 describes transistors having an emitter-base barrier formed either by a Schottky contact or by a substantially depleted barrier region. However in accordance with the present invention the barrier region 4 is present between the Schottky contact 5 and the base region 2 and has a sufficiently large thickness and impurity concentration that at least part of its thickness lies outside the depletion layer present at said
Schottky contact 5 at zero bias.Therefore with no bias voltage applied between the Schottky emitter 5 5 and the base region 2 the barrier region 4 is undepleted over at least part of its thickness and so behaves as a p-type layer, designated p+ in
Figure 1.
Line a in Figure 1 is the electron energy and potential diagram through the transistor structure in this thermal equilibrium, zero bias condition.
Line b in Figure 1 is the corresponding diagram with the base region 2 and collector region 3 biased relative to the emitter 5 by voltages VBE and VCE respectively. Hot electrons 7 are not injected into the base region 2 from the emitter 1 in any significant quantity until the base-emitter bias voltage VBE is of sufficient magnitude to spread the depletion layer across the whole thickness of the barrier region 4. The depletion layer is then said to "punch through" the region 4 between the emitter 5 and the base region 2, so resulting in current flow by thermionic emission of electrons 7. The line b in Figure 1 1 illustrates the situation when VBE is of just sufficient magnitude to deplete the whole of region 4.As can be seen by comparing lines a and b in Figure 1 this need to apply a bias voltage VBE of at least a given magnitude before current flow occurs results in the potential of the base-collector barrier region 1 being shifted to a lower level (more positive) with respect to the emitter 5, so that when carrier injection does occur (line b) the energy of the emitted carriers 7 has been raised to a significant extent relative to the base-collector barrier 1. Thus, the incorporation of an emitterbase barrier region 4 having an undepleted thickness at zero bias increases the collection efficiency of the base-collector barrier 3.
Collection efficiencies as high as 75% and more are possible in this way.
The magnitude of the bias voltage VBE needed to wholly deplete the region 4 depends on the thickness and impurity concentration of region 4 provided between the Schottky contact 5 and the base region 2. In a typical case these may be chosen such that a bias voltage VBE of at least one volt, for example 1.5 volts, is necessary for "punch-through" to occur, so raising the energy of the emitted carriers by a corresponding amount.
Operating the transistor with an emitter-base bias voltage above the minimum level needed for the punch-through reduces the height of the emitter-base barrier and so increases the current flow into the base region 2. This situation is illustrated in Figure 1 by the partial line d.
Figure 2 illustrates one example of such a transistor which apart from the inclusion of the barrier region 4 is similar to transistors described in US-PS 4,149,1 74 and which can be made in a similar manner using ion implementation. The collector region 3 is provided by an n-type silicon epitaxial layer on a highly doped silicon substrate 13 of the same conductivity type. An undepleted p-type annular zone 1 1 which is to act as a guardring around the edge of the barrier region 1 is formed in the epitaxial layer 3, for example by dopant diffusion as described in US-PS 4,149,1 74. Then, via a window in an insulating layer 10 of, for example, silicon dioxide at the epitaxial layer surface, the regions 1, 2 and 4 are formed in the epitaxial layer 3 by ion implementation.
The barrier region 4 may be implanted first using a smaller window in the layer 10, after which the window may be widened for implantation of the base region 2 followed by the barrier region 1. The implanted ion dose and energy for the region 4 must together be sufficiently high to ensure that the region 4 not only overdopes the background n-type impurity resulting from the n-type regions 2 and 3 but also lies at least partly beyond the depletion layer which will be present at the Schottky contact 5 at zero bias so that at zero bias at least part of the region 4 forms an undepleted p-type zone. The ion energy chosen for forming the base region 2 may be such that the resulting impurity concentration has a maximum value spaced from the barrier region 4.When the bias voltages are applied to the emitter 5 and base and collector contacts 8 and 9 this spacing introduces a potential drop between the emitter 5 and the undepleted portion of the base region 2 so that the potential of the collector barrier region 1 is shifted even further to lower levels with respect to the emitter 5 as the bias is increased. This feature further aids the collection efficiency and is described in US-PS 4,149,174.
In a typical example, 1 KeV boron ions or 4 KeV indium ions in a dose of for example at least 1014 per cm2 may be implanted to form the undepleted barrier region 4, 10 KeV arsenic ions in a dose of 1014 to 1015 per cm2 may be implanted to form the base region 2, and 5 KeV boron ions or 20 KeV indium ions may be implanted in a dose of 5 x 1012 to 5 x 1013 per cm2 to form the wholly depleted barrier region 1. The epitaxial layer 3 may have a resistivity of, for example, 5 or 10 ohm-cm and a thickness of, for example, 12 microns.With such implantation conditions and depending on the annealing conditions, the peak of the implanted arsenic distribution can be estimated as occurring at about 1 soy (0.015 micron) or more below the surface of the epitaxial layer with a concentration of about 1020 to 1021 arsenic atoms per cm3. The p-type barrier region 4 is formed within about 1 ooA (0.010 micron) of the surface, and has such a high impurity concentration that it is estimated to be undepleted at zero bias over considerably more than half its thickness. The distance between the barrier regions 4 and 1 can be estimated as being about 250A (0.25 micron) or more. The width of the barrier region 1 may be estimated as being about 1 soy (0.015 micron).
After annealing the implants metal layers 5, 8 and 9 are provided in known manner. The layers 8 and 9 (which may be of for example aluminium) form ohmic contacts to the base region 2 and the collector substrate 13 respectively. The layer 5 forms the Schottky contact for the transistor emitter and may be of for example gold or nickel.
During operation in the circuit configuration illustrated in Figure 2, the emitter 5 is biased negatively with respect to the base contact 8 which is itself biased negatively with respect to the collector contact 9. As discussed hereinbefore significant current flow between the emitter 5 and collector contact 9 does not occur unless the voltage applied between the emitter 5 and base contact 8 is sufficient to deplete the barrier region 4 over its whole thickness. As indicated in Figure 2, an input signal (for example of high frequency) can be applied between the emitter 5 and base contact 8, and an amplified output signal can be derived across a load R between the base and collector contacts 8 and 9. Because of its high collector efficiency the transistor can have a high current gain.
It will be evident that many modifications of this transistor structure are possible in accordance with the invention. Thus, for example as illustrated in Figure 3 the Schottky emitter 5 and its barrier region 4 may be of annular form and extend around the base contact 8. In this form having an outer emitter, the shallow p-type barrier region 4 may merge into the deeperp-type guard ring 11 of the depleted barrier region 1. As illustrated in
Figure 3, the p-type guard ring 1 1 need not be formed in a separate doping step but may be formed in the implantations for the barrier regions 1 and 4, by effecting these implantations after the implantation for the base region 2 and through a slightly widened window in the layer 10; a similar process is described in US-PS 4,149,174.
Other features described in US-PS 4,149,174 may also be incorporated. Thus, for example, the doping concentration of the layer 3 immediately adjacent the barrier region 1 may be increased by a further donor implant. Such a local increase in doping may be contained within approximately
1 50A (0.01 5 micron) of the barrier region 1 and serves to increase the magnitude of the electric field therein so steepening the fall-off of potential in the region 3 and further aiding the collection efficiency.
Figure 4 illustrates a further modification in
accordance with the invention, in which a lower
doped zone 6 is incorporated in the emitter
structure, between the Schottky contact 5 and the
main barrier region 4. This zone 6 must also be fully depleted under emitter-base bias for emission
of hot electrons to occur into the base region 2
from the Schottky contact 5. The addition of zone
6 causes the depletion layer associated with the
emitter-base barrier to be even wider compared
with the Figure 1 structure, so that in operation
the emitter capacitance of the transistor is
reduced. In the form shown in Figure 4, the zone 6 is of the same conductivity type as the barrier region 4 (p-type), although it may alternatively be of the same conductivity type as the base region 2 (n-type). The doping concentration of the zone may be, for example, about 1017 atoms per cm3.
The Figure 4 structure may be manufactured by using slightly hgher ion energies for implantation of the regions 4, 2 and 1 so that the peak concentration of the implanted impurity forming the region 4 is spaced from the surface of the epitaxial layer. The zone 6 may be formed by the impurity present between this peak concentration and the surface, although preferably its impurity concentration is provided in a separate step, for example by a separate lower-dose implantation.
In a modification of the Figure 4 transistor structure, the Schottky contact 5 is replaced by a highly-doped n-type emitter region. In this case the emitter-base barrier is formed solely by the ptype barrier regions 4 and 6 which form p-n junctions with the base region 2 and with this emitter region. It is similarly possible to modify the
Figure 1 transistor structure by replacing the
Schottky contact 5 with a highly-doped n-type emitter region.
Figure 5 illustrates a hot-electron transistor structure in accordance with the invention, in which the emitter-base barrier is formed solely by the p-type barrier region 4 which forms p-n junctions with both the n-type base region 2 and a low cloped n-type emitter zone 6. A layer 15 forms an ohmic contact to the emitter zone 6, and this layer 15 may be for example of metal such as aluminium or of highly-doped n-type semiconductor material. In a manner similar to that for the Schottky-emitter transistors of Figures 1 to 4, the application of a bias voltage VBE between base region 2 and emitter contact 15 is necessary to spread the depletion layers of both these p-n junctions across the whole thickness of the barrier region 4.As with the transistors of Figures 1 to 4, this raises the energy of the emitted carriers 7 relative to the base-collector barrier. However, compared with the transistors of Figures 1 to 4 the ideality factor of the emitter-base barrier can be better (i.e. closer to unity), and the emitter capacitance can be smaller.
A transistor having a structure like that shown in Figure 5 can be manufactured in a similar
manner to those of Figures 1 to 4, using ion implantation. One way of providing the zone 6 and contact layer 1 5 is as follows: after forming the regions 1, 2 and 4 in a silicon epitaxial layer by ion implantation, a high resistivity silicon layer and then a highly-doped n-type silicon layer can be deposited on part of the p-type barrier region 4 at a window in an insulating layer to provide the zone 6 and layer 15 respectively; the highly-doped ntype silicon layer may also be deposited in contact with part of the base region 2 to provide the base contact.
Figure 6 illustrates another form of the transistor structure of Figure 5 which can be manufactured using molecular-beam epitaxy. The transistor comprises a highly-doped n-type substrate 13 of for example gallium arsenide on which a less-highly doped n-type epitaxial layer of the same material is grown in a conventional manner, for example by liquid phase epitaxy.
Layers of gallium arsenide having the thickness and impurity concentrations desired for the regions 1, 2, 4 and 6 are then deposited in succession on the surface of the layer 3 using molecular beam epitaxy. The two upper layers are then removed by an ion beam milling or other etching process over the whole of their thickness, except where they are masked to form the zone 6 and barrier region 4. Then, the other two layers are similarly removed over the whole of their thickness, except where they are masked to form the base region 2 and barrier region 1. Metal layers forming ohmic contacts with the semiconductor are deposited to provide the emitter, base and collector contacts 15, 8 and 9. If desired the contact 15 may be provided before the layer removal and used as a mask while defining the lateral extent of the zone 6 and region 4 by ion-beam milling.Instead of a layer removal treatment for defining the lateral extent of the regions 1 and 2, localized proton bombardment may be effected to form semi-insulating zones around the regions 1 and 2.
The transistors so far described have been hotelectron transistors having n-type base regions 2.
However, hot-hole transistors are also possible in accordance with the invention, in which case the base and collector regions 2 and 3 would be ptype and the barrier regions 1 and 4 would be doped with donor impurity.
The transmitters as shown in Figures 2, 3 and 6 have one emitter-base barrier. However, transistors in accordance with the present invention may have a plurality of emitters and form a plurality of emitter-base barriers with a base region 2. Such multiple-emitter transistors may, for example, be used for higher power operation or as a fast switching transistor in a logic circuit.
Hot-electron or hot-hole transistor structures in accordance with the present invention can be integrated with other semiconductor regions and provided with contacts to form more complex devices, for example a thyristor or an integrated circuit. In the devices illustrated in Figures 2, 3 and 6, the collector region 3 is part of an epitaxial layer which is present on a substrate 13 of the same conductivity type, and an electrode connection 9 to the region 3 contacts the back of the substrate 13.However devices and integrated circuits comprising transistors in accordance with the invention are also possible in which the collector region 3 is part of a layer of one conductivity type which is present on a substrate of the opposite conductivity type, for example for isolation purposes, and in which an electrode connection to the collector region 3 contacts the surface of the epitaxial layer, for example with a more highly doped surface-zone and buried-layer in the epitaxial layer to reduce the series resistance.
In the transistors shown in Figures 2, 3 and 6, the base-collector barrier is buried in the semiconductor body below the emitter-base barrier which is adjacent a surface of the body.
However, transistors in accordance with the present invention are also possible having their emitter-base barrier buried in the semiconductor body below one or more collector-base barriers.
Thus, for example the collector-base barrier(s) may comprise a Schottky contact to the base region 2, and the emitter-base barrier may consist of a barrier region 4 which is not depleted across part of its thickness at zero bias, the emitter region being a semiconductor region of the same conductivity type as the base region 2.
In the transistors so far described, the basecollector barrier is formed by a barrier region 1 which is substantially depleted across the whole of its thickness at zero bias. However, for some applications, it may be preferable to have a basecollector barrier region 1 which is not depleted across part of its thickness at zero bias but which requires a smell minimum bias voltage for punchthrough of the region 1. Before punch-through occurs, very Ittle current would flow into the collector region 3, whereas after punch-through the collector current could rise rapidly.
A further modification is illustrated in Figure 7 which is the energy diagram of a transistor in accordance with the second aspect of the invention. In this transistor, instead of a p-type barrier region 4, the emitter-base barrier forming means comprise a metal layer 25 on an insulating layer 14 on the base region 2 which adjoins the semiconductor body surface. Figure 8 illustrates one example of such a transistor as a modification of the previously-described Figure 2 transistor structure. The application of a bias voltage V8E of a given minimum magnitude between the base region 2 and emitter contact 25 is necessary to permit injection of the hot charge carriers 7 (electrons) across the layer 2, and so the energy of the carriers 7 when emitted is raised in this way relative to the base-collector barrier 1. A thin insulating layer 14 of good quality can be provided on the semiconductor base region 2, for example by deposition or as a generic layer by low temperature oxidation or other chemical conversion of the semiconductor material. The thickness of the layer 14 may be for example about 1 ooA (0.01 micron). The carrier flow across the layer 14 may be by field-assisted hopping.
Claims (10)
1. A transistor comprising a semiconductor body including a base region of one conductivity type through which current flow is by hot majority charge carriers, and barrier-forming means which form with said base region emitter-base and basecollector barriers, characterized in that said emitter-base barrier-forming means comprise a metal layer on an insulating layer at a surface of the body, the insulating layer forming a barrier region between the metal layer and the base region, and the application of a bias voltage between the base and emitter being necessary to permit injection of the hot charge carriers across the insulating layer from the metal layer to the base region thereby establishing a supply of the injected carriers having energies above the basecollector barrier.
2. A transistor comprising a semoconductor body including a base region of one conductivity type through which current flow is by hot majority charge carriers, and barrier-forming means which form with said base region emitter-base and basecollector barriers, said emitter-base barrierforming means comprising a barrier region having an impurity concentration of the opposite conductivity type, characterized in that the thickness and impurity concentration of said barrier region are sufficiently large that said barrier region is at least over part of its thickness undepleted by the depletion layer or layers present at said emitter-base barrier at zero bias, the application of a bias voltage between the base and emitter of the transistor being necessary to establish a supply of said hot majority carriers having energies above the base-collector barrier.
3. A transistor as claimed in Claim 2, further characterized in that the emitter-base barrierforming means comprises a Schottky contact at a surface of the body, in that said region is present between the Schottky contact and the base region, and in that at least part of the thickness of said barrier region lies outside the depletion layer present at said Schottky contact at zero bias.
4. A transistor as claimed in Claim 3, further characterized in that said barrier region of the opposite conductivity type is separated from the
Schottky contact by a lower-doped zone than said barrier region.
5. A transistor as claimed in Claim 2, further characterized in that the barrier region is present between the base region and an ohmic contact of the emitter, and in that the barrier region is separated from the ohmic contact by a lowerdoped zone than the barrier region.
6. A transistor as claimed in Claim 4 or Claim 5 further characterized in that said lower-doped zone is of the one conductivity type and forms a depletion layer with the barrier region.
7. A transistor as claimed in Claim 4 or Claim 5, further characterized in that said lower-doped zone is of said opposite conductivity type.
8. A transistor as claimed in any of Claims 2 to 7, further characterized in that the application of said bias voltage establishes the supply of said hot majority carriers by spreading said depletion layer(s) across the whole thickness of the barrier region between the emitter and base region.
9. A transistor as claimed in any of the preceding Claims, further characterized in that said base region has a conductivity type determining impurity concentration of at least 1020 dopant atoms/cm3.
10. A transistor substantially as described with reference to any of Figures 1 to 8 of the accompanying drawings.
Priority Applications (12)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB7927647A GB2056165A (en) | 1979-08-08 | 1979-08-08 | Hot-electron or hot-hole transistor |
| GB7943911A GB2056166B (en) | 1979-08-08 | 1979-12-20 | Hot-electron or hot-hole transistor |
| DE19803027599 DE3027599A1 (en) | 1979-08-08 | 1980-07-21 | TRANSISTOR WITH HOT CARRIERS |
| CA000357396A CA1157961A (en) | 1979-08-08 | 1980-07-31 | Hot electron or hot hole transistor |
| AU61076/80A AU536182B2 (en) | 1979-08-08 | 1980-08-05 | Transistor utilizing hot charge carriers |
| IT24018/80A IT1132331B (en) | 1979-08-08 | 1980-08-05 | TRANSISTORS |
| JP10684880A JPS5937865B2 (en) | 1979-08-08 | 1980-08-05 | transistor |
| IE1633/80A IE50185B1 (en) | 1979-08-08 | 1980-08-05 | Transistors |
| NLAANVRAGE8004470,A NL186126C (en) | 1979-08-08 | 1980-08-06 | HOT LOAD CARRIER TRANSISTOR. |
| ES494024A ES8104639A1 (en) | 1979-08-08 | 1980-08-06 | Transistors |
| FR8017366A FR2463511A1 (en) | 1979-08-08 | 1980-08-06 | HOT LOAD CARRIER TRANSISTOR |
| US06/487,234 US4862238A (en) | 1979-08-08 | 1983-04-22 | Transistors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB7927647A GB2056165A (en) | 1979-08-08 | 1979-08-08 | Hot-electron or hot-hole transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB2056165A true GB2056165A (en) | 1981-03-11 |
Family
ID=10507070
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB7927647A Withdrawn GB2056165A (en) | 1979-08-08 | 1979-08-08 | Hot-electron or hot-hole transistor |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS5937865B2 (en) |
| GB (1) | GB2056165A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4449140A (en) * | 1981-12-24 | 1984-05-15 | National Research Development Corporation | Semi-conductor barrier switching devices |
| EP0247667A1 (en) * | 1986-05-23 | 1987-12-02 | Philips Electronics Uk Limited | Hot charge-carrier transistors |
| GB2207807A (en) * | 1987-07-22 | 1989-02-08 | Gen Electric Plc | Hot electron transistors |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5872646U (en) * | 1981-11-11 | 1983-05-17 | ロ−ズベイ八重洲ビル石川島建材工業株式会社 | Positioning device for sliding members on loading racks, etc. |
| JPS63268275A (en) * | 1987-04-25 | 1988-11-04 | Nippon Telegr & Teleph Corp <Ntt> | Schottky barrier width control transistor |
-
1979
- 1979-08-08 GB GB7927647A patent/GB2056165A/en not_active Withdrawn
-
1980
- 1980-08-05 JP JP10684880A patent/JPS5937865B2/en not_active Expired
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4449140A (en) * | 1981-12-24 | 1984-05-15 | National Research Development Corporation | Semi-conductor barrier switching devices |
| EP0247667A1 (en) * | 1986-05-23 | 1987-12-02 | Philips Electronics Uk Limited | Hot charge-carrier transistors |
| US4922314A (en) * | 1986-05-23 | 1990-05-01 | U.S. Philips Corp. | Hot charge-carrier transistors |
| GB2207807A (en) * | 1987-07-22 | 1989-02-08 | Gen Electric Plc | Hot electron transistors |
| GB2207807B (en) * | 1987-07-22 | 1990-09-12 | Gen Electric Plc | Hot electron transistors |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5937865B2 (en) | 1984-09-12 |
| JPS5627966A (en) | 1981-03-18 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |