GB2207807A

GB2207807A - Hot electron transistors

Info

Publication number: GB2207807A
Application number: GB08813777A
Authority: GB
Inventors: Adrian Peter Long; Peter Hartley Beton; Michael Joseph Kelly
Original assignee: General Electric Co PLC
Current assignee: General Electric Co PLC
Priority date: 1987-07-22
Filing date: 1988-06-10
Publication date: 1989-02-08
Anticipated expiration: 2008-06-10
Also published as: GB2207807B; GB8717361D0; GB8813777D0

Abstract

In a method of forming a hot electron transistor, a collector electrode structure (6) is formed on a substrate (1) by molecular beam epitaxy (MBE). Over the collector structure a layer (17) of a doped semiconductor material is formed, also by MBE. At least one metallic base contact region (19,20) is formed in the doped layer (17) by diffusion, and a metallic emitter contact (23) is deposited on the doped layer to form an emitter contact and to form a Schottky barrier at the interface between the emitter contact and the doped layer. A layer (18) of undoped semiconductor material may be formed over the doped layer. The base contact region will then be diffused through the undoped layer and into the doped layer. This method of construction avoids the difficulty of very accurate etching away layers to reveal the base region, which has previously been encountered. <IMAGE>

Description

Hot Electron Transistors This invention relates to a method of forming a hot electron transistor.

Hot electron transistors fabricated in semiconductor material generally comprise low-resistance emitter, base and collector electrodes, with an insulating barrier between the emitter and the base, and another insulating barrier between the base and the collector.

The barriers are conventionally formed in either of two ways, namely as a layer of aluminium gallium arsenide, or as a planar doped barrier, i.e. a thin p-doped depleted region surrounded by undoped gallium arsenide. Such transistors may be fabricated by epitaxial growth techniques, with subsequent etching to reveal the base and collector regions so that metallic contacts can be made thereto.

Since the base region must be very thin in order to obtain an acceptable current gain in the device, the end of the etching operation must be very accurately controlled or the underlying portion of the base region will also be removed. Such fine control of the etching operation is very difficult to achieve and may limit the extent to which such devices are commercially exploited.

In another known method of forming a hot electron transistor, base and barrier regions are provided by ion implantation. In this case, the accurate etching mentioned above is not required, but the use of ion implantation techniques is expensive and complicated.

It is an object of the present invention to provide an improved hot electron transistor structure, in which neither etching down to the base region nor ion implantation is required.

According to one aspect of the invention there is provided a method of forming a hot electron transistor, comprising the steps of forming a collector electrode structure on a substrate by molecular beam epitaxy; forming a layer of a doped semiconductor material on the collector electrode structure by molecular beam epitaxy; diffusing a metallic body partially into the layer of doped semiconductor material to act as a base electrode contact; and forming a metallic emitter contact on the layer of doped semiconductor material to form a Schottky barrier at the interface between the emitter contact and the layer of doped semiconductor material.

According to a another aspect of the invention there is provided a method of forming a hot electron transistor, comprising the steps of forming a collector electrode structure on a substrate by molecular beam epitaxy; forming a layer of a doped semiconductor material on the collector electrode structure by molecular beam epitaxy; forming a layer of an undoped semiconductor material over the layer of doped semiconductor material by molecular beam epitaxy; diffusing a metallic body through the layer of undoped semiconductor material and into the layer of doped semiconductor material to act as a base electrode contact; and forming a metallic emitter contact on the layer of undoped semiconductor material to form a Schottky barrier at the interface between the emitter contact and the layer of undoped semiconductor material.

An embodiment of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a schematic cross section of a conventional hot electron transistor; Figure 2 is a schematic cross section of a hot electron transistor according to the invention; and Figures 3a-3d are schematic cross-sectional views of a hot electron injector structure forming part of the transistor of Figure 2, showing respective stages in the construction process.

Referring to Figure 1, a conventional hot electron transistor comprises a substrate 1 of n+ semiconductor material on which is grown a GaAs layer 2 which is heavily doped with silicon at a density of, for example, 1018/cm3. The layer 2 may be 50ooh thick. A layer 3 of GaAs, for example 2400t thick, is grown over the layer 2. A layer 4 of p+ type GaAs of thickness 120t is formed by heavily doping the GaAs with beryllium at a density of, for example, 1018/cm3. A layer 5 of GaAs of, for example, 200A thickness is grown thereover. The layers 2-5 together form a planar doped barrier which constitutes a collector electrode 6. A layer 8 of n-type GaAs of 1000t thickness is formed by doping the GaAs layer with Si at a density of 1018/cm~3.

The layer 8 forms a base electrode. Over the layer 8 a graded layer 9 of AlxGal ps of thickness 5000 is formed, where x decreases from 0.2 to O in a direction away from the layer 8. This layer constitutes a base/emitter barrier. Over the layer 9 an n-type GaAs layer 10 of thickness 50000 and doped with Si at a density of 1018/cm3 is formed. The layers 9 and 10 together form an emitter electrode 11.

The layers may all be formed by epitaxial growth techniques.

After deposition of the layers, regions 12 down each side of the device are etched away, leaving edge portions of the upper surface of the layer 2 uncovered. On those edge portions metallic collector contacts 13 are deposited. Regions 14 are then etched away, leaving edge portions of the upper surface of the base layer uncovered.

Metallic base contacts 15 are deposited on those edge portions. A metallic layer 16 is deposited over the layer 10 to form an emitter contact. As mentioned previously, the etching operations nust be very accurately controlled.

Figure 2 shows schematically the structure of a hot electron transistor according to the present invention. It comprises a substrate 1 and collector layers 2-5, which may be identical to those of Figure 1. A collector barrier layer may be formed by doping or may be formed of AlGaAs or other suitable insulating compositions. A layer 17 of n-type GaAs is formed over the barrier layer by heavily doping a GaAs layer with an n-type dopant, such as Si, at a density within a range of 1 x 1018/cm3 to 5 x 1018/cm3. The thickness of the layer 17 may be, for example, in the range 100-1000A, and is preferably around 500#. Over the layer 17, an insulating layer 18 of undoped GaAs is formed. This layer may have a thickness in the range C O to 200A, and is preferably around 100A thick.The lower limit of the latter range indicates that the layer 18 may, in some applications, be omitted.

Base contact regions 19 and 20, base connections 21 and 22 and an emitter contact 23 are formed by a process which will now be described with reference to Figure 3. For the sake of simplicity, this figure shows only the doped semiconductor layer 17 and the insulating layer 18 of the device of Figure 2. Figure 3(a) shows the untreated layers 17 and 18. In a first stage in the process (Figure 3(b)) two spaced-apart metal lines 24 and 25 are deposited on the layer 18. The metal may be, for example, a gold/germanium alloy.

In the next stage (Figure 3(c)), the structure is heated to a sufficiently high temperature for the metal lines to melt and for the metal to diffuse into the layers 18 and 17, thereby forming the base contact regions 19 and 20 within the layers, and the external base connections 21 and 22. In the final stage (Figure 3(d)), the metal contact 23, which may be, for example, of gold/titanium alloy, is deposited on the layer 18, centrally between the base connections, to form an emitter contact.

It will be apparent that the whole of the described layer structure is formed by molecular beam epitaxy from the same semiconductor material, namely GaAs. Alternatively, however, other semiconductor materials might be used.

The operation of the device is as follows. The metal/semiconductor interface at the emitter contact 23 forms a Schottky barrier. This acts as an energy barrier which prevents the passage of electrons from the metal to the semiconductor. The shape of the barrier depends on the thickness of the layer 18 and on the doping density of the layer 17. A depletion region is set up in the layer 17 due to the presence of this Schottky barrier. The thickness of the layer 17 and the doping density in the layer are chosen such that the thickness of the depletion region is less than that of the layer 17. If a potential difference of sufficient magnitude is applied between the base connections and the emitter contact, electrons can tunnel through the Schottky barrier and will be accelerated through the layer 17 to the collector 6.

The magnitude of the potential difference which is necessary to cause significant numbers of electrons to tunnel through the Schottky barrier, thereby giving rise to a significant current, is determined by the shape of the barrier. The electrons which pass through the barrier are injected into the layer 17 with an energy level which is approximately equal to this potential difference.

This energy is generally much greater than the ambient thermal energy, so that the device operates as a hot electron transistor in which the Schottky barrier at the emitter metal/semiconductor interface, in conjunction with the layers 17 and 18, operates as a hot electron injector. The injection properties of this injector depend upon the doping density and thickness of the layers 17 and 18. In particular, the presence of the undoped layer 18 allows the electron energy to be controlled; the wider the energy barrier caused by the undoped layer 18, the greater the applied potential difference required to cause significant current flow.

If, as mentioned above, the undoped semiconductor layer 18 is omitted, the base connections 21 and 22 will project from the exposed surface of the doped semiconductor layer 17, and the emitter contact 23 will be deposited on the surface of that layer. The Schottky barrier will then be formed between the contact 23 and the layer 17, still causing a depletion region to occur in that layer. In this case, however, the control of the energy barrier shape is partially lost; the shape in this case is determined only by the doping density in the layer 18.

It will be apparent that in the device of the present invention no etching is required in order to make contact with a thin base electrode layer, as is the case in the prior hot electron transistor structure of Figure 1. Furthermore, by providing the Schottky barrier at the emitter, it is possible to provide base and emitter contacts which lie substantially in a common plane, while electrical isolation between them is maintained. More especially, the layers are all formed by molecular beam epitaxy, so the use of expensive and difficult ion implantation is avoided.

Claims

1. A method of forming a hot electron transistor, comprising the steps of forming a collector electrode structure on a substrate by molecular beam epitaxy; forming a layer of a doped semiconductor material on the collector electrode structure by molecular beam epitaxy; diffusing a metallic body partially into the layer of doped semiconductor material to act as a base electrode contact; and forming a metallic emitter contact on the layer of doped semiconductor material to form a Schottky barrier at the interface between the emitter contact and the layer of doped semiconductor material.

2. A method of forming a hot electron transistor, comprising the steps of forming a collector electrode structure on a substrate by molecular beam epitaxy; forming a layer of a doped semiconductor material on the collector electrode structure by molecular beam epitaxy; forming a layer of an undoped semiconductor material over the layer of doped semiconductor material by molecular beam epitaxy; diffusing a metallic body through the layer of undoped semiconductor material and into the layer of doped semiconductor material to act as a base electrode contact; and forming a metallic emitter contact on the layer of undoped semiconductor material to form a Schottky barrier at the interface between the emitter contact and the layer of undoped semiconductor material.

3. A method according to Claim 1 or Claim 2, wherein the substrate, the collector electrode structure and the layers of doped and undoped (where provided) semiconductor material are all formed of the same basic semiconductor material.

4. A method according to Claim 3, wherein the basic semiconductor material is gallium arsenide.

5. A method of forming a hot electron transistor, substantially as hereinbefore described with reference to the accompanying drawings.