JPS58101493A - 基板 - Google Patents

基板

Info

Publication number
JPS58101493A
JPS58101493A JP57159722A JP15972282A JPS58101493A JP S58101493 A JPS58101493 A JP S58101493A JP 57159722 A JP57159722 A JP 57159722A JP 15972282 A JP15972282 A JP 15972282A JP S58101493 A JPS58101493 A JP S58101493A
Authority
JP
Japan
Prior art keywords
solder
chip
substrate
bonding
aluminum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57159722A
Other languages
English (en)
Other versions
JPS6352776B2 (ja
Inventor
ロバ−ト・マ−クス
ダグラス・ウオ−レス・フエルプス・ジユニア
ウイリアム・キヤロル・ワ−ド
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS58101493A publication Critical patent/JPS58101493A/ja
Publication of JPS6352776B2 publication Critical patent/JPS6352776B2/ja
Granted legal-status Critical Current

Links

Classifications

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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明の分野 半導体チップのパンケージングにおける主要な技術は、
チップを装着するために用いら几るセラミック又はプラ
スチックの基板上にチップを装着しそして必要なピンの
入出力Ｃｌ１０）接続を設けることである。基板は又、
〒ヤパシタ及び抵抗の如き回路構成素子を含み得る。多
くの場合において、所与の基板上に１種以上のチップを
パンケージソゲし、又は単一のチップに種々の型の接続
を設けることが必要とさｎるっ従って、必要な相互接続
路と同様に、各チップのための装着パッドが設けらｎね
ばならない。
基板にチップを接続するために、２つの主なシステムが
用いう几ている。その１つのシステムはいわゆるフリッ
プ・チップはんだボンディング・システムであり、この
場合にはチップ表面上のはんだ接続体が基板上に形成さ
れたはんだバンドにはんだ付けさｒる。その結果、チッ
プと基板との間に機械的接着（ｂｏｎｄ　ｉｎｇ）及び
電気的接続が得うレるつもう１つのシステムはワイヤ・
ボンディング・システムであり、この場合には典型的に
はアルミニウム又は金から成るワイヤが超音波溶接の如
き方法によシチップ上及び基板上のアルミニウム、金又
は他の適合する金属に接続さｎる。チップは又、機械的
強度を増すために、接着剤を用いて接着さｎてもよい。
しかしながら、アルミニウム及び金はいず几もはんだと
適合しないので相互に接続Ｇｎ得す、即ち金のワイヤ及
びアルミニウムのワイヤはいず几も従来のＰ　ｂ　／　
Ｓ　ｎはんだに良好に接着さ几得ない。従って、従来に
おいては、単一の基板上に上記２つのシステムによる接
続を併用することは不可能であり、即ち、多数のチップ
を含む基板はすべてフリップ・チップはんだボンデ１ン
グ・システム又はワイヤ・ボンデ１ング・システムのい
すルかにより接着さｎねばならず、又１つのチップは１
つの型の接続しか有することができなかった。
本発明の要旨 本発明に従って、はんだボンディング及びワイヤ・ボン
デ１ングの両方が同一の基板上に施され得る技術が達成
さ几るっそのためには、はんだパッドの配置１体が基板
上に設けられる。ワイヤ・ボンデ１ングが施さ几るべき
各パッドには、多層金属パッドがはんだ付けさ几ている
。各金属パッドは、その対応するパッドにはんだ付けさ
几ているはんだの下層と、ワイヤ・ボンデ１ングさｎる
チップのワイヤに接着さ几る金属の上層と、そ几らの２
つの層の間に挿入さ几てそれらの各層に接着さ几る、上
記下層のはんだ及び上記上層の金属に対して不浸透性の
金属の障壁層とを有する。こ几は、ワイヤに不適合なは
んだパッドを、ワイヤ・ボンデ１ングさ几得るパッドに
変ｆヒさせるっこの技術は、所望であルば、所与のチッ
プがフリップ・チップはんだ接着部およびワイヤ接着部
を有することを可能にし、又所与の基板がそｎらの両シ
ステムによシ装着さｔ’したチップを有することを可能
にする。
本発明の好実施例 第１図太び第２図において、本発明に従って半導体チッ
プを装着するための従来のセラミック基板１０が設けら
１ている。セラミック基板１０は、フリップ・チップ・
ボンデづング表面１６上に形成さ几た従来のＰ　ｂ　／
　Ｓ　ｎはんだボール１４を有するクリップ・チップ・
ボンデ１ング型チツプ１２と、ワイヤ・ボンディング表
面２４上の適当な接続体２２に接着さｎｆＣアルミニウ
ム・ワイヤ２０とを装着する様に構成さｎている。
基板１０は、表面上のある位置に形成されたｐｂ／Ｓｎ
はんだパッド２６の第１配列体を有し、そｎらのはんだ
パッド２６はチップ１２上のはんだボール１４と組合わ
される様に配置さｎているっはんだパッド２６をはんだ
ボール１４にはんだ付けするために従来のはんだ再流動
技術が用いらｎ。
その結果チップ１２が基板１０に機械的に接着さｎ且つ
電気的に接続さｎるっ 基板１０は又、チップ１８上のワイヤ２０の外方端部に
゛対応する様に構成さｎているはんだバンド２８の第２
配列体を有している。パッド２８の配列体における各パ
ッドには、その１つが第３図に示さｎている、３層金属
ペデスタル３０が接続されている。各ペデスタルは、従
来のＰｂ／Ｓｎはんだの下層３２と、アルミニウムの上
層３４と、そ几らの層３２及び３４の間に挿入さｎてい
るニッケルの中間層３６とを有する。
各ペデスタル６０のはんだ下層３２は、チップ１８のワ
イヤ２０に接着さｎる様に配置さ几たアルミニウム上層
６４の上面を有するペデスタル６０のゲタ１」体が設け
ら几る様に、はんだパッド２８の配列体におけるパッド
の１つにはんだ接続さ−ｒＬ％そしてペデスタル３０の
アルミニウム上層とチップ１８のアルミニウム・ワイヤ
２０との間に、超音波浴接の如き溶接接続が施さ几る。
チップ１８は又、所望ならば、例えばエポヤシ又ははん
だ型合金３７の如き、接着剤又は金属を用いて、基板１
０の表面にポンディングさ几得る。
配列体におけるはんだバンド２６及び２８の一部は、そ
の一部が５９として示さ几ている導体によって、互いに
相互接続さル、又金属で充填さルた貫通孔３８に相互接
続されているうそルらの貫通孔には入出力ピン４０がろ
う付けさｎているっスウエージさ几たピン（ａｗａｇｅ
ｄ　　ｐｉｎ）の如き仙のピンも用いら几、又ピン型で
ない接続体も用いら１得ることはもちろんであるつ アルミニウム及び金はいずれもはんだに効果的に接着さ
れ得ないので、典型的にはアルミニウム、場合によって
金のワイヤを用いるワイヤ・ボンデ１ング型チンプに適
しているバンドにはんだパッド２８を接続するためには
、ペデスタル６０を用いることが必要である。アルミニ
ウム中Ｐ　ｂ　／　Ｓ　ｎはんだとの間には、目立った
メタラジカルな接着作用が何ら生じず、金とＰｂ／Ｓｎ
はんだとの間では、金がはんだ中に相互溶解し、金のワ
イヤは短時間のうちに完全に溶解名し得るので、接続体
が破壊さ几てしまり。従って、ワイヤ・ボンデ１ングヲ
要する各パッドには別個のペデスタルが設けらルる。は
んだの下層６２は、はんだパッドにはんだ接続さ几るっ
中間層６６ははんだの下層６２及び金属の上層３４０両
方に接着せねばならず、又はんだ金属が上層の金又はア
ルミニウム中に移動しない様に七ｎらの層の間の障壁層
として働かねばならないっニッケル又はニッケル合金が
好ましいが、銅、銅合金及びステンレス鋼の如き他の金
属も用いらル得る。
上層６４はワイヤ・ボンディング型チップのワイヤに接
着され得る金属であるべきであり、それらのワイヤは典
型的にはアルミニウム又は金のワイヤである。従って、
上面の金属は、最適な同−金層間の接着を得るために１
．ワイヤの組成に応じて、アルミニウム又は金であるべ
きであるっ処理又は再加工中に用いら几る例えば約５４
０℃の如き高温において、金及びアルミニウムは迅速に
望ましくない金属間化合物を形成するので、金のワイヤ
の接着には上面に金を有するペデスタルが用いら几、ア
ルミニウム・ワイヤの接着には上面にアルミニウムを有
するペデスタルが用いらルることか好ましい。
第４図は、単一のチップにワイヤ・ボンデ１ング及びク
リップ・チップはんだボンデ１ングの両方による接続が
行なわルる様に適合さ几ている、本発明のもう１つの実
施例を示している。この場合には、クリップ・チップ・
ボンディング型半導体チップ４４上のはんだポール４２
と組合わされる、前述の如きはんだパッド２６の配列体
が基板１０に設けらルている。更に、チップ４４は、基
板に接続さ几ねばならないチップの裏側に接続さ几てい
るアルミニウム命ワ４ヤ４６を有しているっこのワ４ヤ
は、接地等の如き多くの目的に用いら几得る。その様な
接続を設けるには、ペデスタル３０がはんだ付けさ几る
はんだバンド４８が更に設けらｎる。ペデスタル６０の
アルミニウム上層３４は、例えば超音波技術によシ、ア
ルミニウム・ワイヤ４６に接着さＣる。
この技術を用いることによって、はんだパッド接続を設
ける几めに基板を従来の技術に従って処理することが出
来、そ１らが適当でない場合には、はんだパッド技術を
ワイヤ・ボンデ１ング技術に変えるためにペデスタル３
０を用いることができ、又そｎらの両技術を同一基板上
で併用することが可能でおる。この様に同一チップ上に
両技術を併用し得ることの大きな利点の１つは、モジュ
ールが、他に悪影響を与えることなく、６４０℃μ上に
おける加熱並びに７リツプ・チップ・ボンデ１ング又は
ワイヤ・ボンデ１ングされているチップの除去及び交換
によって、処理又は再加工さｎ得ることである。
又、この技術は、基板上にフリップ・チップ・ボンデト
ングが全く用いられず、ワイヤ・ボンディングだけが用
いら几る場合にも適用式れ得るっこの様な技術は、製造
において１つの型の技術だけを基板に用いたいが、場合
によってフリップ・チップ・ボンディング技術及びクリ
ップ・チップ・ボンデ１ング技術とワイヤ・ボンデ１ン
グ技術との組合せでなく、ワイヤ・ボンデ１ング型チン
プだけを基板に接着する必要があるときでも、コストを
節減する技術として用いられ得るっその場合には、はん
だバンドを有するフリップ・チップ・ボンデ１ング型の
基板が、本発明によるペデスタルを用いることにより、
ワイヤ・ボンディングさｎたチイプだけを装着する友め
に用いらｎ得るっ
【図面の簡単な説明】
第１図は本発明に従ってパンケージングさｎている１つ
のセラミック基板及び２つの半導体チップを示す分解斜
視図、第２図は第１図の線２−２における断面図、第３
図はセラミック基板上の選択さｆ’Ｌ７’ｃパッドに取
付けら几る本発明によるペデスタルの斜視図、第４図は
単一のチップがフリップ・チップ・ボンデ１ング及びワ
イヤ・ボンデ１ングの両技術を用いて基板に接続さｎて
いる、第２図と同様な断面図である。 １０・・・・セラミック基板、１２，４４・・・・フリ
ップ・チップ・ボンデ１ング型チツプ、１４．４２・・
・・はんだボール、１６・・・・フリップ・チップ・ボ
ンデ１ング表面、１８・・・・ワイヤ・ボンディング型
チップ、２０．４６・・・・アルミニウム・ワ＜−’ｖ
、２２・・・・接続体、２４・・・・ワイヤ・ボンデ１
ング表面、２６，２Ｂ、４８・・・・はんだバンド、５
０・・・・３層金属ペデスタル、３２・・・・はんだ下
層、３４・・・・アルミニウム上層、６６・・・・ニン
ケル中間層、３７・・・・エポ千シ又ははんだ型合金、
３８・・・・金属で充填さ几た貫通孔、３９・・・・導
体、４０・・・・入出力ピンっ

Claims (1)

    【特許請求の範囲】
  1. 入出力手段と、少なくとも一部が集積回路チップを相互
    接続するためのパターンに配置さｎている複数のはんだ
    パッドとを有している。集積回路チップを装着するため
    の基板において、少なくとも１つの上記はんだバンドに
    多層金属ペデスタルが接続さｎておシ、上記ペデスタル
    は上記はんだパッドに接続さ几ているはんだの下層と、
    アルミニウム又は金のワイヤに接着さｎるに適している
    金属の上層と、上記両層間に挿入さ几ていて上記下層の
    はんだ及び上記上層の金属に対して不浸透性の金属の中
    間層とを有することヲ肴徴とする、集積回路チップ装着
    用基板。
JP57159722A 1981-12-09 1982-09-16 基板 Granted JPS58101493A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US328889 1981-12-09
US06/328,889 US4447857A (en) 1981-12-09 1981-12-09 Substrate with multiple type connections

Publications (2)

Publication Number Publication Date
JPS58101493A true JPS58101493A (ja) 1983-06-16
JPS6352776B2 JPS6352776B2 (ja) 1988-10-20

Family

ID=23282896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57159722A Granted JPS58101493A (ja) 1981-12-09 1982-09-16 基板

Country Status (4)

Country Link
US (1) US4447857A (ja)
EP (1) EP0081135B1 (ja)
JP (1) JPS58101493A (ja)
DE (1) DE3275789D1 (ja)

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Also Published As

Publication number Publication date
DE3275789D1 (en) 1987-04-23
EP0081135B1 (en) 1987-03-18
EP0081135A2 (en) 1983-06-15
JPS6352776B2 (ja) 1988-10-20
US4447857A (en) 1984-05-08
EP0081135A3 (en) 1984-07-25

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