JPS5760851A - Dielectric isolation of semiconductor integrated circuit - Google Patents

Dielectric isolation of semiconductor integrated circuit

Info

Publication number
JPS5760851A
JPS5760851A JP12798780A JP12798780A JPS5760851A JP S5760851 A JPS5760851 A JP S5760851A JP 12798780 A JP12798780 A JP 12798780A JP 12798780 A JP12798780 A JP 12798780A JP S5760851 A JPS5760851 A JP S5760851A
Authority
JP
Japan
Prior art keywords
etching
oxide film
nitride film
groove
eaves
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12798780A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6212660B2 (enrdf_load_stackoverflow
Inventor
Yoichi Tamaoki
Tokuo Kure
Akira Sato
Hisayuki Higuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12798780A priority Critical patent/JPS5760851A/ja
Priority to EP81304255A priority patent/EP0048175B1/en
Priority to DE8181304255T priority patent/DE3174468D1/de
Publication of JPS5760851A publication Critical patent/JPS5760851A/ja
Priority to US06/733,406 priority patent/US4635090A/en
Priority to US06/891,174 priority patent/US5128743A/en
Publication of JPS6212660B2 publication Critical patent/JPS6212660B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
JP12798780A 1980-09-17 1980-09-17 Dielectric isolation of semiconductor integrated circuit Granted JPS5760851A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP12798780A JPS5760851A (en) 1980-09-17 1980-09-17 Dielectric isolation of semiconductor integrated circuit
EP81304255A EP0048175B1 (en) 1980-09-17 1981-09-16 Semiconductor device and method of manufacturing the same
DE8181304255T DE3174468D1 (en) 1980-09-17 1981-09-16 Semiconductor device and method of manufacturing the same
US06/733,406 US4635090A (en) 1980-09-17 1985-05-13 Tapered groove IC isolation
US06/891,174 US5128743A (en) 1980-09-17 1986-07-31 Semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12798780A JPS5760851A (en) 1980-09-17 1980-09-17 Dielectric isolation of semiconductor integrated circuit

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP371488A Division JPS63313834A (ja) 1988-01-13 1988-01-13 半導体集積回路

Publications (2)

Publication Number Publication Date
JPS5760851A true JPS5760851A (en) 1982-04-13
JPS6212660B2 JPS6212660B2 (enrdf_load_stackoverflow) 1987-03-19

Family

ID=14973638

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12798780A Granted JPS5760851A (en) 1980-09-17 1980-09-17 Dielectric isolation of semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5760851A (enrdf_load_stackoverflow)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58206136A (ja) * 1982-05-25 1983-12-01 Toshiba Corp 半導体装置の製造方法
JPS58215053A (ja) * 1982-06-08 1983-12-14 Nec Corp 半導体集積回路装置
JPS5984435A (ja) * 1982-11-04 1984-05-16 Matsushita Electric Ind Co Ltd 半導体集積回路及びその製造方法
JPS59189626A (ja) * 1983-04-13 1984-10-27 Matsushita Electronics Corp 半導体装置の製造方法
US4696095A (en) * 1986-03-27 1987-09-29 Advanced Micro Devices, Inc. Process for isolation using self-aligned diffusion process
US4810668A (en) * 1986-07-18 1989-03-07 Kabushiki Kaisha Toshiba Semiconductor device element-isolation by oxidation of polysilicon in trench
JPH0294445U (enrdf_load_stackoverflow) * 1989-01-12 1990-07-26
JPH02231739A (ja) * 1989-03-03 1990-09-13 Mitsubishi Electric Corp 半導体装置の製造方法
US6265316B1 (en) 1998-04-03 2001-07-24 Nec Corporation Etching method
JP2009302528A (ja) * 2008-06-11 2009-12-24 Magnachip Semiconductor Ltd 半導体素子のトリプルゲート形成方法
CN119560418A (zh) * 2025-01-22 2025-03-04 荣芯半导体(宁波)有限公司 半导体结构及其制作方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4920631B2 (ja) * 2008-04-28 2012-04-18 シャープ株式会社 半導体装置の製造方法
TWI833828B (zh) 2018-10-29 2024-03-01 日商積水化學工業股份有限公司 氮化硼奈米材料及樹脂組成物

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5432277A (en) * 1977-08-15 1979-03-09 Ibm Method of forming silicon area isolated from dielectric

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5432277A (en) * 1977-08-15 1979-03-09 Ibm Method of forming silicon area isolated from dielectric

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58206136A (ja) * 1982-05-25 1983-12-01 Toshiba Corp 半導体装置の製造方法
JPS58215053A (ja) * 1982-06-08 1983-12-14 Nec Corp 半導体集積回路装置
JPS5984435A (ja) * 1982-11-04 1984-05-16 Matsushita Electric Ind Co Ltd 半導体集積回路及びその製造方法
JPS59189626A (ja) * 1983-04-13 1984-10-27 Matsushita Electronics Corp 半導体装置の製造方法
US4696095A (en) * 1986-03-27 1987-09-29 Advanced Micro Devices, Inc. Process for isolation using self-aligned diffusion process
US4810668A (en) * 1986-07-18 1989-03-07 Kabushiki Kaisha Toshiba Semiconductor device element-isolation by oxidation of polysilicon in trench
JPH0294445U (enrdf_load_stackoverflow) * 1989-01-12 1990-07-26
JPH02231739A (ja) * 1989-03-03 1990-09-13 Mitsubishi Electric Corp 半導体装置の製造方法
US6265316B1 (en) 1998-04-03 2001-07-24 Nec Corporation Etching method
JP2009302528A (ja) * 2008-06-11 2009-12-24 Magnachip Semiconductor Ltd 半導体素子のトリプルゲート形成方法
CN119560418A (zh) * 2025-01-22 2025-03-04 荣芯半导体(宁波)有限公司 半导体结构及其制作方法

Also Published As

Publication number Publication date
JPS6212660B2 (enrdf_load_stackoverflow) 1987-03-19

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