JPS5721826A - Manufacture of semiconductor single crystal wafer - Google Patents

Manufacture of semiconductor single crystal wafer

Info

Publication number
JPS5721826A
JPS5721826A JP9669980A JP9669980A JPS5721826A JP S5721826 A JPS5721826 A JP S5721826A JP 9669980 A JP9669980 A JP 9669980A JP 9669980 A JP9669980 A JP 9669980A JP S5721826 A JPS5721826 A JP S5721826A
Authority
JP
Japan
Prior art keywords
wafer
back surface
grooves
crystalline
front surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9669980A
Other languages
Japanese (ja)
Other versions
JPS6127900B2 (en
Inventor
Mitsuru Sakamoto
Kuniyuki Hamano
Masahiko Nakamae
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9669980A priority Critical patent/JPS5721826A/en
Publication of JPS5721826A publication Critical patent/JPS5721826A/en
Publication of JPS6127900B2 publication Critical patent/JPS6127900B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To form a crystalline surface approximating to no defect to control the deformation of the shape of a semiconductor wafer by selectively forming grooves on the back surface of the wafer, heat treating it to deform the front surface in recess state and the back surface in raised state and correcting the crystalline defects on the front surface of the wafer to the back surface groove region. CONSTITUTION:Grooves 12 are concentrically formed on the back surface of the silicon single crystal wafer 11. The groove has a depth of 0.5-10mum, a width of 0.5mum to several mm., and interval between the grooves of 0.5mum to several mm.. The wafer 11 is the heat treated in inert gas, the back surface of the wafer is deformed in recess state and the front surface is deformed in raised state, and strong crystal stress field is produced in the vicinity of the periphery 13 of the grooves 12. This region becomes the center of collecting the crystalline defect existing in the surface region 14 of the wafer. Thus, the surface defects of the wafer can be reduced, and the control of the deformation of the shape can be simultaneously performed, and a large sized semiconductor wafer adapted for high density integrated and finely machined configuration can be obtained.
JP9669980A 1980-07-15 1980-07-15 Manufacture of semiconductor single crystal wafer Granted JPS5721826A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9669980A JPS5721826A (en) 1980-07-15 1980-07-15 Manufacture of semiconductor single crystal wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9669980A JPS5721826A (en) 1980-07-15 1980-07-15 Manufacture of semiconductor single crystal wafer

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP1330186A Division JPS61198637A (en) 1986-01-24 1986-01-24 Manufacture of semiconductor single crystal wafer

Publications (2)

Publication Number Publication Date
JPS5721826A true JPS5721826A (en) 1982-02-04
JPS6127900B2 JPS6127900B2 (en) 1986-06-27

Family

ID=14172005

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9669980A Granted JPS5721826A (en) 1980-07-15 1980-07-15 Manufacture of semiconductor single crystal wafer

Country Status (1)

Country Link
JP (1) JPS5721826A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5938492U (en) * 1982-08-31 1984-03-10 富士通株式会社 Plasma display panel drive circuit
JPS61198637A (en) * 1986-01-24 1986-09-03 Nec Corp Manufacture of semiconductor single crystal wafer
KR20030002847A (en) * 2001-06-29 2003-01-09 주식회사 하이닉스반도체 Method for fabricating semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5568837B2 (en) * 2008-02-29 2014-08-13 株式会社Ｓｕｍｃｏ Silicon substrate manufacturing method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5938492U (en) * 1982-08-31 1984-03-10 富士通株式会社 Plasma display panel drive circuit
JPS61198637A (en) * 1986-01-24 1986-09-03 Nec Corp Manufacture of semiconductor single crystal wafer
JPH0235456B2 (en) * 1986-01-24 1990-08-10 Nippon Electric Co
KR20030002847A (en) * 2001-06-29 2003-01-09 주식회사 하이닉스반도체 Method for fabricating semiconductor device

Also Published As

Publication number Publication date
JPS6127900B2 (en) 1986-06-27

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