JPS5745242A - Method and apparatus for manufacturing semiconductor integrated circuit - Google Patents

Method and apparatus for manufacturing semiconductor integrated circuit

Info

Publication number
JPS5745242A
JPS5745242A JP11980980A JP11980980A JPS5745242A JP S5745242 A JPS5745242 A JP S5745242A JP 11980980 A JP11980980 A JP 11980980A JP 11980980 A JP11980980 A JP 11980980A JP S5745242 A JPS5745242 A JP S5745242A
Authority
JP
Japan
Prior art keywords
substrate
grinding
ground
wafers
insular
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11980980A
Other languages
Japanese (ja)
Inventor
Hironori Inoue
Takaya Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11980980A priority Critical patent/JPS5745242A/en
Publication of JPS5745242A publication Critical patent/JPS5745242A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting

Abstract

PURPOSE:To separate an insular region uniformly by a method wherein finishing grinding is treated in a batch manner up to its midway when grinding substrates, the thickness of wafers is measured every one substrate, the remaining amounts of each substrate ground are calculated from the results and the substrates are ground separately. CONSTITUTION:The surface of a supporter layer is ground and a reference plane is prepared in the substrate 11 to which the supporter layer 8 is formed. The substrate is upset, and a great part of an unnecessary Si single crystal wafer are removed through rough grinding. The surface is finishing-ground until the Si single crystal insular regions are separated through batch treatment. The thickness of the wafers is measured every one sheet through an infrared interference method, and the remaining amounts of grinding, at which the insular regions of the whole regions in the substrate are separated completely and from which the desired thickness of islands is obtained, are calculated. The surfaces are finishing-ground every one sheet in response to the amounts of grinding. Accordingly, the insular regions of the wafers can uniformly be separated excellently and the islands can be thickened with superior accuracy, and mass-producing capability is improved.
JP11980980A 1980-09-01 1980-09-01 Method and apparatus for manufacturing semiconductor integrated circuit Pending JPS5745242A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11980980A JPS5745242A (en) 1980-09-01 1980-09-01 Method and apparatus for manufacturing semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11980980A JPS5745242A (en) 1980-09-01 1980-09-01 Method and apparatus for manufacturing semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS5745242A true JPS5745242A (en) 1982-03-15

Family

ID=14770760

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11980980A Pending JPS5745242A (en) 1980-09-01 1980-09-01 Method and apparatus for manufacturing semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5745242A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6063207A (en) * 1983-09-19 1985-04-11 Toho Titanium Co Ltd Preparation of catalyst component for polymerization of olefin
US5387817A (en) * 1991-12-02 1995-02-07 Oki Electric Industry Co., Ltd. Dielectric isolation substrate having single-crystal silicon islands surrounded by groove and lower conductive layer filling the groove therewith
CN111195852A (en) * 2018-11-19 2020-05-26 江苏鲁汶仪器有限公司 Device and method for polishing dense device side wall in direction parallel to device side wall

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4831374A (en) * 1971-08-26 1973-04-24

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4831374A (en) * 1971-08-26 1973-04-24

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6063207A (en) * 1983-09-19 1985-04-11 Toho Titanium Co Ltd Preparation of catalyst component for polymerization of olefin
JPH059445B2 (en) * 1983-09-19 1993-02-05 Toho Titanium Co Ltd
US5387817A (en) * 1991-12-02 1995-02-07 Oki Electric Industry Co., Ltd. Dielectric isolation substrate having single-crystal silicon islands surrounded by groove and lower conductive layer filling the groove therewith
CN111195852A (en) * 2018-11-19 2020-05-26 江苏鲁汶仪器有限公司 Device and method for polishing dense device side wall in direction parallel to device side wall

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