JPS57143844A - Chip composition of wafer - Google Patents

Chip composition of wafer

Info

Publication number
JPS57143844A
JPS57143844A JP2885781A JP2885781A JPS57143844A JP S57143844 A JPS57143844 A JP S57143844A JP 2885781 A JP2885781 A JP 2885781A JP 2885781 A JP2885781 A JP 2885781A JP S57143844 A JPS57143844 A JP S57143844A
Authority
JP
Japan
Prior art keywords
wafer
chips
hexagonal
cut out
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2885781A
Other languages
Japanese (ja)
Inventor
Tomizo Terasawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP2885781A priority Critical patent/JPS57143844A/en
Publication of JPS57143844A publication Critical patent/JPS57143844A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)

Abstract

PURPOSE:To take more chips out of a wafer of an identical area and improve the yield by a method wherein hexagonal chips are formed on the wafer and are cut out. CONSTITUTION:A disc wafer 2 is sliced out of a cylindrical semiconductor single crystal substance 1. The wafer is divided into hexagonal semiconductor chips 3 in which integrated circuits or like are composed. The impurity density in the circumference area of the substance 1 is differnt from that in the inner area, but the chips obtained by dividing the wafer into hexagons can be arranged in the circumference area at the relatively uniform intervals, so that the deviation of the impurity density for respective chips can be avoided. And, for instance, 153 hexagonal chips can be cut out of a three-inch wafer, while 150 square chips can be cut out of the same wafer.
JP2885781A 1981-02-28 1981-02-28 Chip composition of wafer Pending JPS57143844A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2885781A JPS57143844A (en) 1981-02-28 1981-02-28 Chip composition of wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2885781A JPS57143844A (en) 1981-02-28 1981-02-28 Chip composition of wafer

Publications (1)

Publication Number Publication Date
JPS57143844A true JPS57143844A (en) 1982-09-06

Family

ID=12260046

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2885781A Pending JPS57143844A (en) 1981-02-28 1981-02-28 Chip composition of wafer

Country Status (1)

Country Link
JP (1) JPS57143844A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0268859A2 (en) * 1986-10-27 1988-06-01 Kabushiki Kaisha Toshiba Method of dividing semiconductor wafers
US5329157A (en) * 1992-07-17 1994-07-12 Lsi Logic Corporation Semiconductor packaging technique yielding increased inner lead count for a given die-receiving area
US5532934A (en) * 1992-07-17 1996-07-02 Lsi Logic Corporation Floorplanning technique using multi-partitioning based on a partition cost factor for non-square shaped partitions
US5561086A (en) * 1993-06-18 1996-10-01 Lsi Logic Corporation Techniques for mounting semiconductor dies in die-receiving areas having support structure having notches
KR100562223B1 (en) * 1997-09-25 2006-06-13 지멘스 악티엔게젤샤프트 Method of maximizing chip yield for semiconductor wafers
US7622779B2 (en) * 2002-09-10 2009-11-24 The Regents Of The University Of California Interconnection architecture and method of assessing interconnection architecture

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0268859A2 (en) * 1986-10-27 1988-06-01 Kabushiki Kaisha Toshiba Method of dividing semiconductor wafers
EP0268859A3 (en) * 1986-10-27 1988-11-09 Kabushiki Kaisha Toshiba Method of dividing semiconductor wafers
US5329157A (en) * 1992-07-17 1994-07-12 Lsi Logic Corporation Semiconductor packaging technique yielding increased inner lead count for a given die-receiving area
US5341024A (en) * 1992-07-17 1994-08-23 Lsi Logic Corporation Method of increasing the layout efficiency of dies on a wafer, and increasing the ratio of I/O area to active area per die
US5340772A (en) * 1992-07-17 1994-08-23 Lsi Logic Corporation Method of increasing the layout efficiency of dies on a wafer and increasing the ratio of I/O area to active area per die
EP0583625A3 (en) * 1992-07-17 1994-08-24 Lsi Logic Corp Method of increasing the layout efficiency of dies on a wafer, and increasing the ratio of i/o area to active area per die
US5532934A (en) * 1992-07-17 1996-07-02 Lsi Logic Corporation Floorplanning technique using multi-partitioning based on a partition cost factor for non-square shaped partitions
US5561086A (en) * 1993-06-18 1996-10-01 Lsi Logic Corporation Techniques for mounting semiconductor dies in die-receiving areas having support structure having notches
KR100562223B1 (en) * 1997-09-25 2006-06-13 지멘스 악티엔게젤샤프트 Method of maximizing chip yield for semiconductor wafers
US7622779B2 (en) * 2002-09-10 2009-11-24 The Regents Of The University Of California Interconnection architecture and method of assessing interconnection architecture

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