JPS52155982A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS52155982A
JPS52155982A JP7369576A JP7369576A JPS52155982A JP S52155982 A JPS52155982 A JP S52155982A JP 7369576 A JP7369576 A JP 7369576A JP 7369576 A JP7369576 A JP 7369576A JP S52155982 A JPS52155982 A JP S52155982A
Authority
JP
Japan
Prior art keywords
scribing
semiconductor device
dielectric layer
separating
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7369576A
Other languages
Japanese (ja)
Inventor
Kazutoshi Kamibayashi
Masashi Mukogawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7369576A priority Critical patent/JPS52155982A/en
Publication of JPS52155982A publication Critical patent/JPS52155982A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: To reduce the production of broken chips during scribing by providing a dielectric layer of the same depth as that of the dielectric layer isolating each semiconductor element in scribing regions and scribing and separating from there, in semiconductor devices of dielectric isolation structure.
COPYRIGHT: (C)1977,JPO&Japio
JP7369576A 1976-06-21 1976-06-21 Semiconductor device Pending JPS52155982A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7369576A JPS52155982A (en) 1976-06-21 1976-06-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7369576A JPS52155982A (en) 1976-06-21 1976-06-21 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS52155982A true JPS52155982A (en) 1977-12-24

Family

ID=13525600

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7369576A Pending JPS52155982A (en) 1976-06-21 1976-06-21 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS52155982A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS635634U (en) * 1986-06-28 1988-01-14
JPS6459947A (en) * 1987-08-31 1989-03-07 Toshiba Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS635634U (en) * 1986-06-28 1988-01-14
JPS6459947A (en) * 1987-08-31 1989-03-07 Toshiba Corp Semiconductor device

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