JPS5720841A - Memory controlling circuit - Google Patents
Memory controlling circuitInfo
- Publication number
- JPS5720841A JPS5720841A JP9634580A JP9634580A JPS5720841A JP S5720841 A JPS5720841 A JP S5720841A JP 9634580 A JP9634580 A JP 9634580A JP 9634580 A JP9634580 A JP 9634580A JP S5720841 A JPS5720841 A JP S5720841A
- Authority
- JP
- Japan
- Prior art keywords
- counter
- blocks
- page
- address
- registers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Image Input (AREA)
- Image Processing (AREA)
- Memory System (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9634580A JPS5720841A (en) | 1980-07-15 | 1980-07-15 | Memory controlling circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9634580A JPS5720841A (en) | 1980-07-15 | 1980-07-15 | Memory controlling circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5720841A true JPS5720841A (en) | 1982-02-03 |
JPS6314386B2 JPS6314386B2 (enrdf_load_stackoverflow) | 1988-03-30 |
Family
ID=14162412
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9634580A Granted JPS5720841A (en) | 1980-07-15 | 1980-07-15 | Memory controlling circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5720841A (enrdf_load_stackoverflow) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS603081A (ja) * | 1983-06-18 | 1985-01-09 | Dainippon Printing Co Ltd | Icカ−ド |
JPS60140421A (ja) * | 1983-12-28 | 1985-07-25 | Hitachi Ltd | 出力制御装置 |
JPS61851A (ja) * | 1984-06-14 | 1986-01-06 | Nec Corp | ダイレクトメモリアクセス回路のデ−タチエ−ン方式 |
JPS6265172A (ja) * | 1985-09-17 | 1987-03-24 | Nippon Telegr & Teleph Corp <Ntt> | デ−タ符号・復号化制御方式 |
JPH02135540A (ja) * | 1988-11-16 | 1990-05-24 | Rohm Co Ltd | データ処理装置のテスト方法 |
JPH09167970A (ja) * | 1995-08-09 | 1997-06-24 | Korea Telecommun | 多チャンネルオーディオデコーダの逆正規化装置及びそれに用いる逆正規化方法 |
-
1980
- 1980-07-15 JP JP9634580A patent/JPS5720841A/ja active Granted
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS603081A (ja) * | 1983-06-18 | 1985-01-09 | Dainippon Printing Co Ltd | Icカ−ド |
JPS60140421A (ja) * | 1983-12-28 | 1985-07-25 | Hitachi Ltd | 出力制御装置 |
JPS61851A (ja) * | 1984-06-14 | 1986-01-06 | Nec Corp | ダイレクトメモリアクセス回路のデ−タチエ−ン方式 |
JPS6265172A (ja) * | 1985-09-17 | 1987-03-24 | Nippon Telegr & Teleph Corp <Ntt> | デ−タ符号・復号化制御方式 |
JPH02135540A (ja) * | 1988-11-16 | 1990-05-24 | Rohm Co Ltd | データ処理装置のテスト方法 |
JPH09167970A (ja) * | 1995-08-09 | 1997-06-24 | Korea Telecommun | 多チャンネルオーディオデコーダの逆正規化装置及びそれに用いる逆正規化方法 |
Also Published As
Publication number | Publication date |
---|---|
JPS6314386B2 (enrdf_load_stackoverflow) | 1988-03-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO1989005488A3 (en) | A memory system | |
JPS5720841A (en) | Memory controlling circuit | |
JPS5592012A (en) | Variable delay circuit | |
JPS5223235A (en) | Input/output multiprocessor | |
JPS5447443A (en) | Semiconductor memory unit | |
JPS57157325A (en) | Microcomputer | |
JPS5714957A (en) | Memory device | |
SU1234882A1 (ru) | Распределитель | |
JPS5276837A (en) | Buffer register transfer control | |
SU1716536A1 (ru) | Устройство дл умножени матриц | |
JPS5525840A (en) | Decoder circuit | |
SU1128253A1 (ru) | Устройство дл формировани адресов регистровой пам ти | |
SU398947A1 (ru) | УСТРОЙСТВО дл | |
JPS573293A (en) | Delay circuit | |
JPS5629892A (en) | Clear control circuit | |
JPS54122944A (en) | Logic circuit | |
SU1485231A1 (ru) | УСТРОЙСТВО ДЛЯ ДЕЛЕНИЯ НА ДВА КОДОВ &quot;ЗОЛОТОЙ&quot; ПРОПОРЦИИ | |
JPS5556220A (en) | Data input system | |
JPS6490644A (en) | Multiple access line exchange | |
JPS6419596A (en) | Shift register with variable word length | |
JPS54151333A (en) | Memory system | |
JPS643734A (en) | Multiplication circuit | |
KR930014075A (ko) | 버스와 메모리사이에서 데이타의 버스트 전송을 제어하기 위한 모듈시스템 | |
JPS54142018A (en) | Memory control system | |
JPS5755438A (en) | Data processing unit |