JPS5720841A - Memory controlling circuit - Google Patents

Memory controlling circuit

Info

Publication number
JPS5720841A
JPS5720841A JP9634580A JP9634580A JPS5720841A JP S5720841 A JPS5720841 A JP S5720841A JP 9634580 A JP9634580 A JP 9634580A JP 9634580 A JP9634580 A JP 9634580A JP S5720841 A JPS5720841 A JP S5720841A
Authority
JP
Japan
Prior art keywords
counter
blocks
page
address
registers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9634580A
Other languages
Japanese (ja)
Other versions
JPS6314386B2 (en
Inventor
Yoshio Maniwa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP9634580A priority Critical patent/JPS5720841A/en
Publication of JPS5720841A publication Critical patent/JPS5720841A/en
Publication of JPS6314386B2 publication Critical patent/JPS6314386B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Image Input (AREA)
  • Image Processing (AREA)

Abstract

PURPOSE:To increase the using efficiency of a memory, by dividing a memory region into plural blocks and then giving random access to thes blocks with plural input/output ports to form a connecting link among the blocks. CONSTITUTION:Buffers 6 and 7 corresponding to page registers 3 and 4 are switched with an output Q of a binary counter 2, and a page address is supplied to the register 3 or 4 from a CPU. Thus an address counter 1 is counted with the increment clock, and the addresses within a page are renewed successively to be shifted to address buffers 6 and 7. The counter 2 is inverted with reception of a set input and with each circulation of the counter 1. Thus the registers 3 and 4 are alternately switched synchronously with a strobe STROB.
JP9634580A 1980-07-15 1980-07-15 Memory controlling circuit Granted JPS5720841A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9634580A JPS5720841A (en) 1980-07-15 1980-07-15 Memory controlling circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9634580A JPS5720841A (en) 1980-07-15 1980-07-15 Memory controlling circuit

Publications (2)

Publication Number Publication Date
JPS5720841A true JPS5720841A (en) 1982-02-03
JPS6314386B2 JPS6314386B2 (en) 1988-03-30

Family

ID=14162412

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9634580A Granted JPS5720841A (en) 1980-07-15 1980-07-15 Memory controlling circuit

Country Status (1)

Country Link
JP (1) JPS5720841A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS603081A (en) * 1983-06-18 1985-01-09 Dainippon Printing Co Ltd Ic card
JPS60140421A (en) * 1983-12-28 1985-07-25 Hitachi Ltd Output controller
JPS61851A (en) * 1984-06-14 1986-01-06 Nec Corp Data chain system of direct memory access circuit
JPS6265172A (en) * 1985-09-17 1987-03-24 Nippon Telegr & Teleph Corp <Ntt> Control system for data coding and decoding
JPH02135540A (en) * 1988-11-16 1990-05-24 Rohm Co Ltd Method for testing data processor
JPH09167970A (en) * 1995-08-09 1997-06-24 Korea Telecommun Inverse-normalization device of multichannel audio decoder, and inverse-normalization method used therefor

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS603081A (en) * 1983-06-18 1985-01-09 Dainippon Printing Co Ltd Ic card
JPH0554158B2 (en) * 1983-06-18 1993-08-11 Dainippon Printing Co Ltd
JPS60140421A (en) * 1983-12-28 1985-07-25 Hitachi Ltd Output controller
JPS61851A (en) * 1984-06-14 1986-01-06 Nec Corp Data chain system of direct memory access circuit
JPS6265172A (en) * 1985-09-17 1987-03-24 Nippon Telegr & Teleph Corp <Ntt> Control system for data coding and decoding
JPH02135540A (en) * 1988-11-16 1990-05-24 Rohm Co Ltd Method for testing data processor
JPH09167970A (en) * 1995-08-09 1997-06-24 Korea Telecommun Inverse-normalization device of multichannel audio decoder, and inverse-normalization method used therefor

Also Published As

Publication number Publication date
JPS6314386B2 (en) 1988-03-30

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