JPS57199242A - Method of connecting and forming integrated circuit in multiple levels - Google Patents
Method of connecting and forming integrated circuit in multiple levelsInfo
- Publication number
- JPS57199242A JPS57199242A JP57038251A JP3825182A JPS57199242A JP S57199242 A JPS57199242 A JP S57199242A JP 57038251 A JP57038251 A JP 57038251A JP 3825182 A JP3825182 A JP 3825182A JP S57199242 A JPS57199242 A JP S57199242A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- integrated circuit
- metallurgy
- multiple levels
- via holes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/269,230 US4423547A (en) | 1981-06-01 | 1981-06-01 | Method for forming dense multilevel interconnection metallurgy for semiconductor devices |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57199242A true JPS57199242A (en) | 1982-12-07 |
Family
ID=23026369
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57038251A Pending JPS57199242A (en) | 1981-06-01 | 1982-03-12 | Method of connecting and forming integrated circuit in multiple levels |
Country Status (5)
Country | Link |
---|---|
US (1) | US4423547A (ja) |
EP (1) | EP0066069B1 (ja) |
JP (1) | JPS57199242A (ja) |
CA (1) | CA1168916A (ja) |
DE (1) | DE3276733D1 (ja) |
Families Citing this family (49)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0177562A4 (en) * | 1984-03-22 | 1987-06-03 | Mostek Corp | NITRIDE BINDING LAYER. |
US4659585A (en) * | 1985-06-24 | 1987-04-21 | International Business Machines Corporation | Planarized ceramic substrates |
US4723197A (en) * | 1985-12-16 | 1988-02-02 | National Semiconductor Corporation | Bonding pad interconnection structure |
DE3782904T2 (de) * | 1986-09-17 | 1993-04-08 | Fujitsu Ltd | Verfahren zur ausbildung einer kupfer enthaltenden metallisierungsschicht auf der oberflaeche eines halbleiterbauelementes. |
JPS63104425A (ja) * | 1986-10-09 | 1988-05-09 | インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション | バイアの形成方法 |
FR2617635B1 (fr) * | 1987-07-03 | 1990-03-09 | Thomson Semiconducteurs | Procede de contact entre deux couches conductrices ou semi-conductrices deposees sur un substrat |
EP0331908A1 (en) * | 1988-03-07 | 1989-09-13 | International Business Machines Corporation | Method for forming high density, ohmic contact multi-level metallurgy for semiconductor devices |
US5386623A (en) * | 1990-11-15 | 1995-02-07 | Hitachi, Ltd. | Process for manufacturing a multi-chip module |
US5114754A (en) * | 1991-01-14 | 1992-05-19 | International Business Machines Corporation | Passivation of metal in metal/polyimide structures |
US5194928A (en) * | 1991-01-14 | 1993-03-16 | International Business Machines Corporation | Passivation of metal in metal/polyimide structure |
US5284801A (en) * | 1992-07-22 | 1994-02-08 | Vlsi Technology, Inc. | Methods of moisture protection in semiconductor devices utilizing polyimides for inter-metal dielectric |
US6147393A (en) * | 1993-05-05 | 2000-11-14 | Ixys Corporation | Isolated multi-chip devices |
US6107674A (en) * | 1993-05-05 | 2000-08-22 | Ixys Corporation | Isolated multi-chip devices |
US6429120B1 (en) * | 2000-01-18 | 2002-08-06 | Micron Technology, Inc. | Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals |
US5956605A (en) * | 1996-09-20 | 1999-09-21 | Micron Technology, Inc. | Use of nitrides for flip-chip encapsulation |
US5924005A (en) * | 1997-02-18 | 1999-07-13 | Motorola, Inc. | Process for forming a semiconductor device |
JP3298472B2 (ja) * | 1997-09-26 | 2002-07-02 | 関西日本電気株式会社 | 絶縁ゲート型半導体装置の製造方法 |
US6211073B1 (en) | 1998-02-27 | 2001-04-03 | Micron Technology, Inc. | Methods for making copper and other metal interconnections in integrated circuits |
US6284656B1 (en) | 1998-08-04 | 2001-09-04 | Micron Technology, Inc. | Copper metallurgy in integrated circuits |
US6288442B1 (en) | 1998-09-10 | 2001-09-11 | Micron Technology, Inc. | Integrated circuit with oxidation-resistant polymeric layer |
US6228758B1 (en) * | 1998-10-14 | 2001-05-08 | Advanced Micro Devices, Inc. | Method of making dual damascene conductive interconnections and integrated circuit device comprising same |
US6965165B2 (en) * | 1998-12-21 | 2005-11-15 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
US6495442B1 (en) * | 2000-10-18 | 2002-12-17 | Magic Corporation | Post passivation interconnection schemes on top of the IC chips |
US7405149B1 (en) * | 1998-12-21 | 2008-07-29 | Megica Corporation | Post passivation method for semiconductor chip or wafer |
US7381642B2 (en) * | 2004-09-23 | 2008-06-03 | Megica Corporation | Top layers of metal for integrated circuits |
US6936531B2 (en) | 1998-12-21 | 2005-08-30 | Megic Corporation | Process of fabricating a chip structure |
US20020127845A1 (en) * | 1999-03-01 | 2002-09-12 | Paul A. Farrar | Conductive structures in integrated circuits |
JP3387478B2 (ja) * | 1999-06-30 | 2003-03-17 | セイコーエプソン株式会社 | 半導体装置およびその製造方法 |
US6383945B1 (en) * | 1999-10-29 | 2002-05-07 | Advanced Micro Devices, Inc. | High selectivity pad etch for thick topside stacks |
US7211512B1 (en) * | 2000-01-18 | 2007-05-01 | Micron Technology, Inc. | Selective electroless-plated copper metallization |
US6420262B1 (en) | 2000-01-18 | 2002-07-16 | Micron Technology, Inc. | Structures and methods to enhance copper metallization |
US7262130B1 (en) | 2000-01-18 | 2007-08-28 | Micron Technology, Inc. | Methods for making integrated-circuit wiring from copper, silver, gold, and other metals |
US6376370B1 (en) | 2000-01-18 | 2002-04-23 | Micron Technology, Inc. | Process for providing seed layers for using aluminum, copper, gold and silver metallurgy process for providing seed layers for using aluminum, copper, gold and silver metallurgy |
US6423629B1 (en) * | 2000-05-31 | 2002-07-23 | Kie Y. Ahn | Multilevel copper interconnects with low-k dielectrics and air gaps |
US6674167B1 (en) * | 2000-05-31 | 2004-01-06 | Micron Technology, Inc. | Multilevel copper interconnect with double passivation |
US7372161B2 (en) * | 2000-10-18 | 2008-05-13 | Megica Corporation | Post passivation interconnection schemes on top of the IC chips |
US7271489B2 (en) * | 2003-10-15 | 2007-09-18 | Megica Corporation | Post passivation interconnection schemes on top of the IC chips |
US7932603B2 (en) | 2001-12-13 | 2011-04-26 | Megica Corporation | Chip structure and process for forming the same |
US20040150096A1 (en) * | 2003-02-03 | 2004-08-05 | International Business Machines Corporation | Capping coating for 3D integration applications |
US7319277B2 (en) * | 2003-05-08 | 2008-01-15 | Megica Corporation | Chip structure with redistribution traces |
US7220665B2 (en) | 2003-08-05 | 2007-05-22 | Micron Technology, Inc. | H2 plasma treatment |
US7459790B2 (en) * | 2003-10-15 | 2008-12-02 | Megica Corporation | Post passivation interconnection schemes on top of the IC chips |
US7759251B2 (en) * | 2004-06-03 | 2010-07-20 | Tel Epion Corporation | Dual damascene integration structure and method for forming improved dual damascene integration structure |
US7521805B2 (en) * | 2004-10-12 | 2009-04-21 | Megica Corp. | Post passivation interconnection schemes on top of the IC chips |
US7514725B2 (en) * | 2004-11-30 | 2009-04-07 | Spire Corporation | Nanophotovoltaic devices |
US7569422B2 (en) | 2006-08-11 | 2009-08-04 | Megica Corporation | Chip package and method for fabricating the same |
US8688058B2 (en) * | 2008-11-24 | 2014-04-01 | Chiewcharn Narathong | Techniques for improving transmitter performance |
US8502314B2 (en) | 2011-04-21 | 2013-08-06 | Fairchild Semiconductor Corporation | Multi-level options for power MOSFETS |
US8502313B2 (en) | 2011-04-21 | 2013-08-06 | Fairchild Semiconductor Corporation | Double layer metal (DLM) power MOSFET |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5615052A (en) * | 1979-07-18 | 1981-02-13 | Hitachi Ltd | Semiconductor device with multilayer wiring |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1230421A (ja) | 1967-09-15 | 1971-05-05 | ||
JPS5144871B2 (ja) | 1971-09-25 | 1976-12-01 | ||
US4001870A (en) | 1972-08-18 | 1977-01-04 | Hitachi, Ltd. | Isolating protective film for semiconductor devices and method for making the same |
US3844831A (en) | 1972-10-27 | 1974-10-29 | Ibm | Forming a compact multilevel interconnection metallurgy system for semi-conductor devices |
GB1468346A (en) | 1973-02-28 | 1977-03-23 | Mullard Ltd | Devices having conductive tracks at different levels with interconnections therebetween |
DE2638799C3 (de) * | 1976-08-27 | 1981-12-03 | Ibm Deutschland Gmbh, 7000 Stuttgart | Verfahren zur Verbesserung der Haftung von metallischen Leiterzügen auf Polyimidschichten in integrierten Schaltungen |
DE2642471A1 (de) * | 1976-09-21 | 1978-03-23 | Siemens Ag | Verfahren zur herstellung von mehrlagenverdrahtungen bei integrierten halbleiterschaltkreisen |
US4070501A (en) * | 1976-10-28 | 1978-01-24 | Ibm Corporation | Forming self-aligned via holes in thin film interconnection systems |
US4242698A (en) * | 1977-11-02 | 1980-12-30 | Texas Instruments Incorporated | Maximum density interconnections for large scale integrated circuits |
DE2923995C2 (de) * | 1979-06-13 | 1985-11-07 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum Herstellen von integrierten MOS-Schaltungen mit MOS-Transistoren und MNOS-Speichertransistoren in Silizium-Gate-Technologie |
-
1981
- 1981-06-01 US US06/269,230 patent/US4423547A/en not_active Expired - Lifetime
-
1982
- 1982-03-12 JP JP57038251A patent/JPS57199242A/ja active Pending
- 1982-04-13 CA CA000400827A patent/CA1168916A/en not_active Expired
- 1982-04-15 EP EP82103175A patent/EP0066069B1/en not_active Expired
- 1982-04-15 DE DE8282103175T patent/DE3276733D1/de not_active Expired
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5615052A (en) * | 1979-07-18 | 1981-02-13 | Hitachi Ltd | Semiconductor device with multilayer wiring |
Also Published As
Publication number | Publication date |
---|---|
EP0066069B1 (en) | 1987-07-08 |
EP0066069A3 (en) | 1984-09-19 |
DE3276733D1 (en) | 1987-08-13 |
EP0066069A2 (en) | 1982-12-08 |
US4423547A (en) | 1984-01-03 |
CA1168916A (en) | 1984-06-12 |
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