EP0177562A4 - Nitride bonding layer. - Google Patents

Nitride bonding layer.


Publication number
EP0177562A4 EP19850901781 EP85901781A EP0177562A4 EP 0177562 A4 EP0177562 A4 EP 0177562A4 EP 19850901781 EP19850901781 EP 19850901781 EP 85901781 A EP85901781 A EP 85901781A EP 0177562 A4 EP0177562 A4 EP 0177562A4
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Patent type
Prior art keywords
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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German (de)
French (fr)
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EP0177562A1 (en )
Daniel J Quinn
Ilya L Tsitovsky
Barbara R Mozdzen
Linda S Wilson
Charles F Held
Wayne A Mulholland
Yen T Nguyen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thomson Components-Mostek Corp
Original Assignee
Mostek Corp
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Publication date



    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329Insulating materials
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00


An integrated circuit chip includes a layer of silicon nitride (4-20) deposited above the upper metallization and silicon oxide intermetallic dielectric (4-10), above which a layer of polyimide (4-50) supports a network of electrical leads; the layer of nitride (4-20) extending completely over the silicon oxide (4-10) from the streets (4-200) at the edge of the die to overlap metallic contacts (4-05) connected from the metallization layer to the upper electrical leads.


Nitride Bonding Layer

Technical Field

The field of the invention is the encapsulation and packaging of integrated circuits.

Background Art

The use of silicon nitride for passivation of active P-N junctions in integrated circuits is known, as is the use of silicon nitride as a dielectric and as an intermediate aperture-defining layer. An article by R. L. Van Tuyl et al in the IEEE Transactions on Microwave Theory, Vol. MTT-30, No. 7, page 935, 1982, discloses the use of silicon nitride as an intermetallic dielectric for the purpose of forming capacitors in a double-level metallization circuit.

Disclosure of Invention

The invention relates to the use of a layer of silicon nitride as a bond improving agent between a silicon oxide glass and an outer covering of polyimide or other polymer.

Another feature of the invention is the encapsulation of a silicon oxide glass layer by nitride.

Brief Description of Drawings Figure 1 illustrates the process flow in the subject invention.

Figure 2 illustrates the steps in Figure 1 in more detail.

Figures 3A and 3B illustrate different forms of a chip used in the subject invention. Figures 4A and 4B illustrate cross sections of dice used in the invention.

Figure 5 illustrates a portion of a leadframe.

Figure 6 shows the time dependence of bond strength of the subject invention and of the prior art.

Figure 7 illustrates a carrier used to hold a leadframe and die during the bonding step.

Best Mode for Carrying Out the Invention The present invention was developed together with other components of a system for assembling and testing integrated circuits. Other features of the system are the subject of copending patent applications, filed the same day herewith and assigned to the assignee hereof. In order to convey the invention in context, discussion of the overall system is included in this specification.

An overall flow chart of the steps used in the back-end assembly is illustrated in Figure 1, in which a number of steps are illustrated schematically and are performed by a variety of different machines in communication with and sometimes controlled by a computer for storing test and other data.

In the first major step, represented by the box labelled I, a process that may be part of the "front-end" or the "back-end", accepts as input a wafer that has been completed with all the conventional steps (including passivation - etc.) and applies a further layer of dielectric having a thickness sufficient to protect the chip circuits and to insulate them electrically from signals being carried on the top surface of the dielectric. A pattern of metal leads is formed that extends from the contact pads on the previous chip to a standard array of contact pads on the top of the dielectric. The standard array is the same for all chips having the same number of pins, regardless of the size of the chip die.

The wafer is then probe tested, in major step II with the results of the probe test being stored electrically, such as in a computer. The conventional ink-dot marking system for bad chips is not used.

The wafer is then adhesively mounted on an adhesive film in a frame holder that is shaped to allow for automatic insertion and orientation in various fixtures further along in the process and cut apart in an automatic sawing process (Step III) that cuts through the entire thickness of the wafer.

The good dice are then removed from the wafer in an automatic sequence (Step IV) that presses from above against the tape to selectively pick a die down into a dedicated carrier where it rests circuit side down. This is not a problem since the active circuitry is protected by the standard pad dielectric and standard pads. The wafer and punch-out device are moved under computer control to put the dice into the correct positions in the carrier.

The dice are transferred to a mating carrier simultaneously in an inversion operation that rotates the two-carrier "sandwich" by 180 degrees, so that the dice resting in the second carrier have contacts on the top side. A set of dice are transferred to a bonding fixture that holds a convenient number, illustratively 14 dice. Once loading is complete, a leadframe matching the spacing of the dice in the fixture is positioned above the dice in the soldering fixture and an upper bonding fixture is added to maintain lead to pad contact during the bonding process.

The bonding fixture is heated to reflow the solder and form the interconnection (Step V).

The leadframe with dice attached is placed in a transfer or injection molding machine that encapsulates the die together with the interconnections to the leadframe (Step VI).

The molded strip of devices is then trimmed and formed conventionally (Step VII).

There is a representation in Figure 1 of data communication between the machines that perform the steps listed above and the controlling computer. Most data communication steps are optional. The step may indeed be performed under operator control and data may be written down manually. The benefits of automatic recording of data and error-free recall of data from a previous step will be evident to those skilled in the art.

The different steps of the invention are set forth in more detail below and in copending patent applications filed on the same date herewith and assigned to the assignee hereof.

Figure 2 sets out the steps in Figure 1 in more detail and also illustrates the material and data flow. A convention used in this figure is that a broken line indicates a material transport step of the sort of loading the material into a container and moving the container to another location and a double arrow indicates data flow into or out of a computer or other storage device. The three material inputs to the process are the wafers, leadframes and plastic for encapsulation. Two recirculation loops involve, respectively, a frame used to support the wafers during the sawing and die selection steps and a positioning fixture used to maintain a set of dice in alignment with a leadframe segment during the bonding operation.

S tandard Contact Pads Returning to the first major step, the illustrative dielectric layer is a polyimide such as Dupont 2525 applied with the thickness of 6 microns and cured at a temperature of greater than 260 C. There may be a nitride or other layer below the polyimide to improve adhesion to the reflow glass or other top layer. The electrical contact pads that have been previously formed in the integrated circuit chip by conventional processing techniques are exposed by applying a photoresist, either liquid or in the form of a tape, on top of the dielectric and etching down through it a passageway to the metal contact pad in the circuit in a conventional manner. A "via" will be formed by filling the contact holes wi th a me ta l or other conductor until the surface of the dielectric is reached. The photoresist is stripped off and a layer of metal is applied by any technique, such as sputtering, over the surface of the polyimide. In one example, the polyimide was back sputtered to prepare the surface, after which 600 Angstroms of 10% titanium +90% tungsten followed by 1000 Angstroms of copper and titanium-tungsten sputtered simultaneously, followed by typically 3 microns of copper were sputtered on. A second layer of photoresist is applied and patterned to define a set of metal leads in the metal layer. The leads reach from the vias penetrating the dielectric to an area in the center of the chip which has a standard pad array of pad contacts that is the same for all the chips that have the same number of leads. For example, a 16 pin chip will have the same standard pad array, of size about .016" by .016" in a standard configuration having dimensions of .126" by .126", whether it is a memory or any other logic device. The standard pad array will be sized so that it fits on the smallest chip that is to be used with that leadframe. Optional versions of the invention employ a pad array that is arranged for some particular purpose.

The exposed areas of the metal are plated with a solder composed of a standard mixture of lead and tin in a conventional electrolytic plating process that employs a mixture of 95% tin and 5% lead. The photoresist is stripped and the plated areas of the metal layer are used as an etching mask in the next step in which the remaining unwanted area of the metal layer is etched away in a bath of hydrogen peroxide plus ammonium hydroxide followed by hydrogen peroxide, which does not attack the solder.

There now remains a chip 300 of the form illustrated in Figure 3A, in which die 310 has on it a thick layer of polyimide 320 and a network of metal lines 326 leading from the contact areas 330 on the outside of the chip to the standard pad array 340. The metal lines 326 have lower inductance greater thermal conductivity and greater strength compared to the wires that were previously used. In the example shown in Figure 3A, the first contacts and the vias through the polyimide layer are all formed on the perimeter of the chip. This figure illustrates a chip in which the layout design was made for the old wire-bonding method in which the contact areas had to be on the perimeter of the chip. An advantage of retaining the old design, besides saving the expense of a new layout, is that it is possible to use conventional wirebonding processes when added capacity is required. To do this however, requires that the additional dielectric and metallizations for the standard pad process is not used.

It is also possible to use the invention and put the contact areas through the dielectric at any convenient location, as shown in Figure 3B. The vias for these leads are shown as originating at different locations on the chip surface, not exclusively at the edge as was the case in the prior art. Lead 348 is shown as connecting a via that is located within the standard pad array. Lead 343 is connected to a via-section 344 through a bridge, not shown in the drawing, that is placed on top of the passivation layer of the underlying chip below the polyimide. This illustrates an additional degree of freedom in routing leads and placing components that is provided by the invention.

A via 305 is shown in Figure 3A in a cut-away portion of the figure as extending from a lower contact area 304 to an upper contact 306 at an end of one of leads 326. The lower contact pads in current practice are typically 4 mils by 4 mils. With such a large area to make contact, the alignment tolerance for the formation and location of the vias and the placement of leads 326 are typically ± 2 mils to 3 mils, which is much greater than a typical tolerance of ± 1/2 mil to 1 mil for connecting leads in the precision processes that are used with conventional wirebonding.

The steps of forming vias and putting down leads may be performed in the front-end using the standard machines for photolithography, if that is convenient. Since the requirements for putting down these metal leads are much less stringent in position alignment than the usual front-end work, it may be preferable to use thick-film technology, such as screen printing, to pattern the dielectric and top leads. Typically, the thick-film technique will be 1/4 to 1/2 the cost of the precision techniques.

A cross section of a portion of a die is shown in Figure 4A, in which substrate 4-100 is the silicon substrate and aperture 4-200 is the "street" that separates adjacent dice. The width of a street is typically 100 microns, to allow room for the saw kerf in the separation step that is performed with a diamond saw having a width of .001 inch.

A contact pad, 4-05, is shown with a series of apertures defined above it. Pad 4-05, which is typically a conventional aluminum s i l icon-copper alloy and is connected by metallization strips, not shown, to the rest of the circuit, is surrounded by oxide 4-10, which has a conventional composition of SiO2 plus phosphorous and other additives (referred to as siticon glass) and a thickness of 1 micron. Oxide 4-10 has a top surface 4-15 on which polyimide layer 4-50 was, at first, applied directly. Early tests showed significant difficulty, in that polyimide layer 4-50 (layer 320 in Figure 3) often disbonded, causing the leadframe to pull the polyimide away from the underlying layer. Figure 6 compares the time dependence of bond strength in a high-temperature, high-humidity environment for leadframes bonded according to the invention and for those bonded as in the prior art. The test was performed by pulling on an epoxied nail head until the polyimide tore away from the layer below. The graphs are normalized to the strength of a new bond, before exposure to moisture.

As can be seen, the prior art bond of polyimide directly to silicon oxide glass (curve 610) was initially as strong as the bond of the invention, but deteriorated to half the strength after only 20 hours in a moisture-saturated environment of two atmospheres at 120 degrees centigrade.

In contrast, the bond of the present invention (curve 620) maintained its original strength after 1000 hours in the same environment. Curve 620 shows the results of a bond using an intermediate layer of silicon nitride 4,000 Angstroms in thickness. Data obtained with a layer of 2000 Angstroms thickness did not differ significantly.

Oxide 4-10 functions as the top dielectric layer in the circuit. It not only coats the substrate and contacts, as shown in Figure 4, but also the circuit elements and metallization. Passivation of the active elements of the circuit is effected in the usual manner of silicon MOSFETS by the thin oxide over source, drain and active area so that oxide 4-10 functions purely as a dielectric, not as a passivating layer. It does not matter in the practice of the invention if there is metallization between portions of the silicon oxide and the polyimide because the metallization does not cover that much area. Nor does it matter if the circuit uses single or double level metallization. The essential feature is the improved bond provided by the encapsulation layer of silicon nitride between a top surface that is all or mostly silicon oxide and an upper layer of polyimide. Nitride layer 4-20 is deposited by plasma-assisted CVD at a temperature less than 400 C, in a conventional manner, to a thickness of typically .3 micron after street 4-200 has been etched through oxide 4-10 to the substrate. A layer of Dupont VM-651 polyimide adhesion promotor solution was spun on and dried. Aperture 4-40 is opened through nitride layer 4-20 by plasma etching in CF4. A layer of 2525 polyimide from Dupont was then applied and spun to produce a relatively flat top surface. Aperture 4-45 above contact 4-05 and 4-55 above street 4-200 are opened through the uncured polyimide by wet etching with a conventional basic solution such as Shipley 312 developer. Typical dimensions for the top of aperture 4-55 and 4-45 are 100 and 87 microns, respectively. A typical dimension of aperture 4-40 is 75 microns, so that aperture 4-40 is surrounded by nitride 4-20 and does not expose any of oxide 4-10.

It has been found that the adhesion of polyimide to top surface 4-25 of nitride 4-20 is greatly improved over the adhesion of polymide to oxide 4-10 at surface 4-15. Nitride 4-20 adheres well to oxide at surface 4-15. the function of nitride 4-20 is thus to improve the adhesion of the polymide by means of a structure that totally encloses the oxide 4-10, not only at the vias but also at the saw cuts on the streets. An alternate embodiment of the invention in illustrated in cross section in Figure 4B, which shows the same portion of a chip as Figure 4A. In

Figure 4B, oxide 4-10 is enclosed by a combination of nitride layer 4-20 together with metal layer 4-60.

Aperture 4-40', the aperture through the nitride layer is shown as being considerably oversized compared with aperture 4-40'', the aperture in oxide 4-10, resulting in easier alignment, since pad 4-05 is much larger than aperture 4-40'. The nitride serves as a bonding agent as before, but the oxide is now protected by the metal layers sputtered over polyimide 4-50 and into the aperture. As described above, the metal is a series of layers: 4-60 - 10% titanium and 90% tungsten; 4-65 - a mixed region of titanium, tungsten and copper; and 4-70 - copper. Layer 4-80 is the solder layer that is used to define the leads.

Bond The assembly for the final bonding step (Step V in Figure 1 and Leadframe Fixture Assemble, Bond, Disassemble in Figure 2) is shown in an exploded view in Figure 7, in which holder 7-110, represented schematically, holds 14 chips with the correct spacing, only two of the receptacles 7-225 being shown. Above receptacle 7-225, there is positioned chip 7-230 and, above the chip, a set of finger contacts 5-122 in leadframe 5-100, part of leadframe strip 5-125. The details of the leadframe will be described below. Cover 7-120 presses down on edge 5-110 of leadframe strip 5-125, which edges rest on shelves 7-112 to position the outer parts of the strip so that the contact tips will be deflected slightly. This deflection is done to compensate for inevitable fluctuations in the position of the tips during the manufacturing process, so that reliable contact is ensured during the bonding operation. The deflection is effected by making the depth of receptacle 7-225 such that the top of chip 7-230 projects above the plane of shelves 7-112 by a set amount. The amount of deflection, (.005 inch to .007 inch) is illustratively several standard deviations of the nominal fluctuation of the tip position to ensure reliable joint formation. The edges 5-110 of leadframe strip 5-125 will be forced on to shelves 7-112 by cover 7-120 and tips 5-122 will thus be pressed against the pads by the spring constant of the leads.

A typical leadframe used in the invention is illustrated in Figure 5, in which half of an individual frame is shown. The individual leadframes are stamped out of a ribbon of metal that may be an inexpensive copper alloy, in contrast to the expensive alloy having the correct thermal properties that is used in the standard prior art process. Strips 5-110 on either side of the ribbon serve to carry the actual leads 5-120 along. Leads 5-120 have an exterior end 5-123, shaped insertion in a socket or for surface-mounting, and an interior portion 5-121 for attachment to a die. The two portions are joined by segments 5-124 that will be severed after the bonding step. Holes 5-112 are provided to give a reference in positioning the leadframe. At the end of each lead 5-120, there is a region, 5-122, in which the lead is bent in a quarter circle (or bent twice to form a parallel contact section) to form a standard dimension flat contact area. Each of the different leads 5-120, with its different length, has been shaped to provide substantially the same spring constant so that the contact areas 5-122 will be uniformly pressed against the mating pads on the die to give correct alignment for the soldering operation. The leads 5-120 have been tinned with solder in a previous step in the fabrication of the lead frame ribbon.

It is an advantageous feature of the invention, but not an essential one, that a family of chips that have the same number of pins have the same standard pad array on top of the dielectric. For illustration, two dice 5-130 and 5-132 of different size are shown together with the leadframe. With this feature, it will then be necessary to have only one ribbon of leadframes for the entire family of chips, with substantial savings in inventory. Both the contact pads 342 of the die and the tips

5-122 have been tinned and are ready to be heated.

The bonding is done by a vapor phase reflow soldering technique or other means of heating the materials to reflow the fusible alloys. These alternative techniques include infra-red heating, conveyor ovens, hot gas heating or laser heating. In vapor phase reflow, a liquid such as Flourinert FC-71 is maintained at its boiling point, the liquid having been selected so that its boiling point is above the soldering temperature. The soldering assembly of holders 7-110 and 7-120, with chips plus leadframe maintained in alignment, is inserted into a container or oven that is filled with the vapor at the boiling-point temperature and held there until the solder has melted and flowed to form a bond. A typical length of time for the heating cycle is 5 to 15 seconds. This boiling point temperature is typically above 225 degrees C but below 300 degrees C. In contrast, the present wire bonding and die attach steps are performed at temperatures of up to 460 degrees C and performed individually. In order to reduce the length of the heating cycle, the bonding fixture should have low mass and many apertures to permit the vapor to flow freely about the solder joints. Holders 7-110 and 7-120 have been shown schematically in order to reduce the complexity of the drawing. An important economic benefit of this invention is that all the leads are soldered at the same time. This is in contrast to the wire-bonding technique, in which the leads must be bonded one by one. The soldering step takes no longer for a 28 pin chip than it does for a 16 pin chip.


After the bonding step, (Step VII in Figure 1), leadframe 5-100, with 14 chips attached, is placed into a transfer or injection molding machine to mold plastic about it, thus encapsulating and protecting the chip. The molding process will be done using conventional techniques and equipment. It is an advantageous feature of this invention that the chips can be moved about at a greater rate and with less delicacy required than would be the case for prior art bonding.


1. An integrated circuit comprising: a silicon substrate having active electrical devices formed thereon; a layer of passivation material disposed above active junctions in said substrate; a network of conductors connecting said active devices and including at least one contact pad having a predetermined pad area; a layer of silicon glass, having a glass top surface and a glass chip boundary at the perimeter of said integrated circuit, disposed above said network of conductors exclusive of said predetermined pad area; a layer of silicon nitride, having a nitride top surface, deposited on said glass top surface; and a layer of dielectric deposited on said nitride top surface and firmly adhering thereto.
2. An integrated circuit according to claim 1, in which said layer of silicon nitride extends continuously over said glass top surface, extending outwardly over said glass chip boundary onto said silicon substrate and having nitride apertures therein only over said contact pads, said nitride apertures having a predetermined aperture area less than said pad area, whereby said silicon glass layer is completely covered by said nitride layer.
3. An integrated circuit according to claim 1, in which said layer of silicon nitride extends continuously over said glass top surface, extending outwardly over said glass chip boundary onto said silicon substrate and having at least one nitride aperture therein over said contact pads, said nitride apertures having a predetermined aperture area comparable to said pad area; having a glass aperture extending through silicon glass within said nitride aperture and extending downwardly to expose an aperture portion of said contact pad and an aperture-perimeter portion of said silicon glass within said nitride aperture and outside said aperture portion of said contact pad; and at least one layer of metal disposed within said nitride aperture and covering said aperture portion of said contact pad and said aperture-perimeter portion of said silicon glass, whereby said silicon glass is completely covered by the combination of said nitride layer and said metal layer.
EP19850901781 1984-03-22 1985-03-19 Nitride bonding layer. Withdrawn EP0177562A4 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US59215284 true 1984-03-22 1984-03-22
US592152 1984-03-22

Publications (2)

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EP0177562A1 true EP0177562A1 (en) 1986-04-16
EP0177562A4 true true EP0177562A4 (en) 1987-06-03



Family Applications (1)

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EP (1) EP0177562A4 (en)
JP (1) JPS61501537A (en)
WO (1) WO1985004519A1 (en)

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DE102006016812A1 (en) * 2006-04-10 2007-10-11 Robert Bosch Gmbh Component having a semiconductor substrate and process for its preparation

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5421073B2 (en) * 1974-04-15 1979-07-27
JPS5519850A (en) * 1978-07-31 1980-02-12 Hitachi Ltd Semiconductor
JPS55150259A (en) * 1979-05-11 1980-11-22 Hitachi Ltd Semiconductor device and method of fabricating the same
JPS6244690B2 (en) * 1979-12-26 1987-09-22 Hitachi Ltd
JPH0347732B2 (en) * 1980-04-25 1991-07-22 Hitachi Ltd
JPS5768059A (en) * 1980-10-15 1982-04-26 Mitsubishi Electric Corp Semiconductor device
US4423547A (en) * 1981-06-01 1984-01-03 International Business Machines Corporation Method for forming dense multilevel interconnection metallurgy for semiconductor devices

Also Published As

Publication number Publication date Type
WO1985004519A1 (en) 1985-10-10 application
EP0177562A1 (en) 1986-04-16 application
JPS61501537A (en) 1986-07-24 application

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