JPS57190341A - Circuit borad composition - Google Patents
Circuit borad compositionInfo
- Publication number
- JPS57190341A JPS57190341A JP7425581A JP7425581A JPS57190341A JP S57190341 A JPS57190341 A JP S57190341A JP 7425581 A JP7425581 A JP 7425581A JP 7425581 A JP7425581 A JP 7425581A JP S57190341 A JPS57190341 A JP S57190341A
- Authority
- JP
- Japan
- Prior art keywords
- gold
- tin alloy
- electrodes
- plating
- constitution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000203 mixture Substances 0.000 title abstract 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract 6
- 239000010931 gold Substances 0.000 abstract 6
- 229910001020 Au alloy Inorganic materials 0.000 abstract 4
- 229910001128 Sn alloy Inorganic materials 0.000 abstract 4
- 238000007747 plating Methods 0.000 abstract 3
- 229910052737 gold Inorganic materials 0.000 abstract 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract 1
- 239000011889 copper foil Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7425581A JPS57190341A (en) | 1981-05-19 | 1981-05-19 | Circuit borad composition |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7425581A JPS57190341A (en) | 1981-05-19 | 1981-05-19 | Circuit borad composition |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57190341A true JPS57190341A (en) | 1982-11-22 |
| JPS6342852B2 JPS6342852B2 (en, 2012) | 1988-08-25 |
Family
ID=13541854
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7425581A Granted JPS57190341A (en) | 1981-05-19 | 1981-05-19 | Circuit borad composition |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57190341A (en, 2012) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5208186A (en) * | 1989-02-09 | 1993-05-04 | National Semiconductor Corporation | Process for reflow bonding of bumps in IC devices |
| US6333554B1 (en) | 1997-09-08 | 2001-12-25 | Fujitsu Limited | Semiconductor device with gold bumps, and method and apparatus of producing the same |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105340089B (zh) * | 2013-07-03 | 2021-03-12 | 亮锐控股有限公司 | 具有在金属化层之下的应力缓冲层的led |
-
1981
- 1981-05-19 JP JP7425581A patent/JPS57190341A/ja active Granted
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5208186A (en) * | 1989-02-09 | 1993-05-04 | National Semiconductor Corporation | Process for reflow bonding of bumps in IC devices |
| US6333554B1 (en) | 1997-09-08 | 2001-12-25 | Fujitsu Limited | Semiconductor device with gold bumps, and method and apparatus of producing the same |
| US6344690B1 (en) | 1997-09-08 | 2002-02-05 | Fujitsu Limited | Semiconductor device with gold bumps, and method and apparatus of producing the same |
| US6495441B2 (en) | 1997-09-08 | 2002-12-17 | Fujitsu Limited | Semiconductor device with gold bumps, and method and apparatus of producing the same |
| US6786385B1 (en) | 1997-09-08 | 2004-09-07 | Fujitsu Limited | Semiconductor device with gold bumps, and method and apparatus of producing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6342852B2 (en, 2012) | 1988-08-25 |
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