JPS57178359A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS57178359A
JPS57178359A JP56062501A JP6250181A JPS57178359A JP S57178359 A JPS57178359 A JP S57178359A JP 56062501 A JP56062501 A JP 56062501A JP 6250181 A JP6250181 A JP 6250181A JP S57178359 A JPS57178359 A JP S57178359A
Authority
JP
Japan
Prior art keywords
type
resistance value
region
potential
load resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56062501A
Other languages
Japanese (ja)
Inventor
Tomohiro Okubo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56062501A priority Critical patent/JPS57178359A/en
Publication of JPS57178359A publication Critical patent/JPS57178359A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices

Landscapes

  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To enable to control the resistance value positively utilizing the existence of the inversion layer generated by field-effect by a method wherein the resistance value of a semiconductor layer, as the load resistor of memory cell, is controlled by applying the voltage of FET diffusion region through an insulating film. CONSTITUTION:A thin gate oxide film is formed directly below load resistors R1 and R2, and a P<+> type semiconductor regions 17 and 18, which will be coupled to drain regions 3 and 4, are formed below the gate oxide film using ion-implanting technique. In other words, an insulating gate type FET structure, wherein a P<+> type region 17 of the potential same as the drain region 4 of MOS2 is used on the side of the load resistor R1 and a a polysilicon layer R1 is used as a channel, is formed. Also, in the same manner as above, the P<+> type region 18 of the same potential as the drain region 3 of MOS1 is used as a gate on the side of the load resistor R2, and an insulating gate type FET structure having a polysilicon layer R2 as a channel is formed, thereby enabling to control the resistance value of the load resistors R1 and R2 by changing the potential of the P<+> type regions 17 and 18.
JP56062501A 1981-04-27 1981-04-27 Semiconductor integrated circuit device Pending JPS57178359A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56062501A JPS57178359A (en) 1981-04-27 1981-04-27 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56062501A JPS57178359A (en) 1981-04-27 1981-04-27 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS57178359A true JPS57178359A (en) 1982-11-02

Family

ID=13201970

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56062501A Pending JPS57178359A (en) 1981-04-27 1981-04-27 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS57178359A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0817208B2 (en) * 1987-09-14 1996-02-21 モトローラ・インコーポレーテツド Trench cell for integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0817208B2 (en) * 1987-09-14 1996-02-21 モトローラ・インコーポレーテツド Trench cell for integrated circuit

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